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drm/amd/ras: Add amdgpu ras system functions
Add amdgpu ras system functions. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
YiPeng Chai
committed by
Alex Deucher
Alex Deucher
parent
b658fadf1c
commit
ffdab7f4e5
268
drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c
Normal file
268
drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c
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@@ -0,0 +1,268 @@
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// SPDX-License-Identifier: MIT
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/*
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* Copyright 2025 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "ras_sys.h"
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#include "amdgpu_ras_mgr.h"
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#include "amdgpu_ras.h"
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#include "amdgpu_reset.h"
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static int amdgpu_ras_sys_detect_fatal_event(struct ras_core_context *ras_core, void *data)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
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uint64_t seq_no;
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seq_no = amdgpu_ras_mgr_gen_ras_event_seqno(adev, RAS_SEQNO_TYPE_UE);
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RAS_DEV_INFO(adev,
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"{%llu} Uncorrectable hardware error(ERREVENT_ATHUB_INTERRUPT) detected!\n",
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seq_no);
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return amdgpu_ras_process_handle_unexpected_interrupt(adev, data);
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}
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static int amdgpu_ras_sys_poison_consumption_event(struct ras_core_context *ras_core,
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void *data)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
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struct ras_event_req *req = (struct ras_event_req *)data;
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pasid_notify pasid_fn;
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if (!req)
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return -EINVAL;
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if (req->pasid_fn) {
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pasid_fn = (pasid_notify)req->pasid_fn;
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pasid_fn(adev, req->pasid, req->data);
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}
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return 0;
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}
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static int amdgpu_ras_sys_gen_seqno(struct ras_core_context *ras_core,
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enum ras_seqno_type seqno_type, uint64_t *seqno)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
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struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev);
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struct ras_event_manager *event_mgr;
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struct ras_event_state *event_state;
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struct amdgpu_hive_info *hive;
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enum ras_event_type event_type;
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uint64_t seq_no;
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if (!ras_mgr || !seqno ||
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(seqno_type >= RAS_SEQNO_TYPE_COUNT_MAX))
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return -EINVAL;
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switch (seqno_type) {
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case RAS_SEQNO_TYPE_UE:
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event_type = RAS_EVENT_TYPE_FATAL;
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break;
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case RAS_SEQNO_TYPE_CE:
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case RAS_SEQNO_TYPE_DE:
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event_type = RAS_EVENT_TYPE_POISON_CREATION;
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break;
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case RAS_SEQNO_TYPE_POISON_CONSUMPTION:
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event_type = RAS_EVENT_TYPE_POISON_CONSUMPTION;
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break;
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default:
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event_type = RAS_EVENT_TYPE_INVALID;
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break;
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}
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hive = amdgpu_get_xgmi_hive(adev);
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event_mgr = hive ? &hive->event_mgr : &ras_mgr->ras_event_mgr;
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event_state = &event_mgr->event_state[event_type];
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if ((event_type == RAS_EVENT_TYPE_FATAL) && amdgpu_ras_in_recovery(adev)) {
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seq_no = event_state->last_seqno;
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} else {
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seq_no = atomic64_inc_return(&event_mgr->seqno);
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event_state->last_seqno = seq_no;
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atomic64_inc(&event_state->count);
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}
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amdgpu_put_xgmi_hive(hive);
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*seqno = seq_no;
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return 0;
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}
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static int amdgpu_ras_sys_event_notifier(struct ras_core_context *ras_core,
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enum ras_notify_event event_id, void *data)
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{
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struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(ras_core->dev);
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int ret = 0;
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switch (event_id) {
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case RAS_EVENT_ID__BAD_PAGE_DETECTED:
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schedule_delayed_work(&ras_mgr->retire_page_dwork, 0);
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break;
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case RAS_EVENT_ID__POISON_CONSUMPTION:
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amdgpu_ras_sys_poison_consumption_event(ras_core, data);
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break;
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case RAS_EVENT_ID__RESERVE_BAD_PAGE:
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ret = amdgpu_ras_reserve_page(ras_core->dev, *(uint64_t *)data);
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break;
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case RAS_EVENT_ID__FATAL_ERROR_DETECTED:
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ret = amdgpu_ras_sys_detect_fatal_event(ras_core, data);
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break;
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case RAS_EVENT_ID__UPDATE_BAD_PAGE_NUM:
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ret = amdgpu_dpm_send_hbm_bad_pages_num(ras_core->dev, *(uint32_t *)data);
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break;
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case RAS_EVENT_ID__UPDATE_BAD_CHANNEL_BITMAP:
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ret = amdgpu_dpm_send_hbm_bad_channel_flag(ras_core->dev, *(uint32_t *)data);
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break;
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case RAS_EVENT_ID__DEVICE_RMA:
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ras_log_ring_add_log_event(ras_core, RAS_LOG_EVENT_RMA, NULL, NULL);
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ret = amdgpu_dpm_send_rma_reason(ras_core->dev);
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break;
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case RAS_EVENT_ID__RESET_GPU:
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ret = amdgpu_ras_mgr_reset_gpu(ras_core->dev, *(uint32_t *)data);
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break;
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default:
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RAS_DEV_WARN(ras_core->dev, "Invalid ras notify event:%d\n", event_id);
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break;
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}
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return ret;
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}
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static u64 amdgpu_ras_sys_get_utc_second_timestamp(struct ras_core_context *ras_core)
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{
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return ktime_get_real_seconds();
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}
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static int amdgpu_ras_sys_check_gpu_status(struct ras_core_context *ras_core,
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uint32_t *status)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
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uint32_t gpu_status = 0;
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if (amdgpu_in_reset(adev) || amdgpu_ras_in_recovery(adev))
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gpu_status |= RAS_GPU_STATUS__IN_RESET;
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if (amdgpu_sriov_vf(adev))
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gpu_status |= RAS_GPU_STATUS__IS_VF;
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*status = gpu_status;
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return 0;
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}
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static int amdgpu_ras_sys_get_device_system_info(struct ras_core_context *ras_core,
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struct device_system_info *dev_info)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
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dev_info->device_id = adev->pdev->device;
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dev_info->vendor_id = adev->pdev->vendor;
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dev_info->socket_id = adev->smuio.funcs->get_socket_id(adev);
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return 0;
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}
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static int amdgpu_ras_sys_gpu_reset_lock(struct ras_core_context *ras_core,
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bool down, bool try)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
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int ret = 0;
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if (down && try)
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ret = down_read_trylock(&adev->reset_domain->sem);
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else if (down)
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down_read(&adev->reset_domain->sem);
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else
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up_read(&adev->reset_domain->sem);
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return ret;
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}
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static bool amdgpu_ras_sys_detect_ras_interrupt(struct ras_core_context *ras_core)
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{
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return !!atomic_read(&amdgpu_ras_in_intr);
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}
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static int amdgpu_ras_sys_get_gpu_mem(struct ras_core_context *ras_core,
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enum gpu_mem_type mem_type, struct gpu_mem_block *gpu_mem)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
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struct psp_context *psp = &adev->psp;
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struct psp_ring *psp_ring;
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struct ta_mem_context *mem_ctx;
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if (mem_type == GPU_MEM_TYPE_RAS_PSP_RING) {
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psp_ring = &psp->km_ring;
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gpu_mem->mem_bo = adev->firmware.rbuf;
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gpu_mem->mem_size = psp_ring->ring_size;
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gpu_mem->mem_mc_addr = psp_ring->ring_mem_mc_addr;
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gpu_mem->mem_cpu_addr = psp_ring->ring_mem;
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} else if (mem_type == GPU_MEM_TYPE_RAS_PSP_CMD) {
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gpu_mem->mem_bo = psp->cmd_buf_bo;
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gpu_mem->mem_size = PSP_CMD_BUFFER_SIZE;
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gpu_mem->mem_mc_addr = psp->cmd_buf_mc_addr;
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gpu_mem->mem_cpu_addr = psp->cmd_buf_mem;
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} else if (mem_type == GPU_MEM_TYPE_RAS_PSP_FENCE) {
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gpu_mem->mem_bo = psp->fence_buf_bo;
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gpu_mem->mem_size = PSP_FENCE_BUFFER_SIZE;
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gpu_mem->mem_mc_addr = psp->fence_buf_mc_addr;
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gpu_mem->mem_cpu_addr = psp->fence_buf;
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} else if (mem_type == GPU_MEM_TYPE_RAS_TA_FW) {
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gpu_mem->mem_bo = psp->fw_pri_bo;
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gpu_mem->mem_size = PSP_1_MEG;
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gpu_mem->mem_mc_addr = psp->fw_pri_mc_addr;
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gpu_mem->mem_cpu_addr = psp->fw_pri_buf;
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} else if (mem_type == GPU_MEM_TYPE_RAS_TA_CMD) {
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mem_ctx = &psp->ras_context.context.mem_context;
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gpu_mem->mem_bo = mem_ctx->shared_bo;
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gpu_mem->mem_size = mem_ctx->shared_mem_size;
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gpu_mem->mem_mc_addr = mem_ctx->shared_mc_addr;
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gpu_mem->mem_cpu_addr = mem_ctx->shared_buf;
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} else {
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return -EINVAL;
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}
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if (!gpu_mem->mem_bo || !gpu_mem->mem_size ||
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!gpu_mem->mem_mc_addr || !gpu_mem->mem_cpu_addr) {
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RAS_DEV_ERR(ras_core->dev, "The ras psp gpu memory is invalid!\n");
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return -ENOMEM;
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}
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return 0;
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}
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static int amdgpu_ras_sys_put_gpu_mem(struct ras_core_context *ras_core,
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enum gpu_mem_type mem_type, struct gpu_mem_block *gpu_mem)
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{
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return 0;
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}
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const struct ras_sys_func amdgpu_ras_sys_fn = {
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.ras_notifier = amdgpu_ras_sys_event_notifier,
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.get_utc_second_timestamp = amdgpu_ras_sys_get_utc_second_timestamp,
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.gen_seqno = amdgpu_ras_sys_gen_seqno,
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.check_gpu_status = amdgpu_ras_sys_check_gpu_status,
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.get_device_system_info = amdgpu_ras_sys_get_device_system_info,
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.gpu_reset_lock = amdgpu_ras_sys_gpu_reset_lock,
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.detect_ras_interrupt = amdgpu_ras_sys_detect_ras_interrupt,
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.get_gpu_mem = amdgpu_ras_sys_get_gpu_mem,
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.put_gpu_mem = amdgpu_ras_sys_put_gpu_mem,
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};
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109
drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h
Normal file
109
drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h
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@@ -0,0 +1,109 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright 2025 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
|
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
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* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
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* The above copyright notice and this permission notice shall be included in
|
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* all copies or substantial portions of the Software.
|
||||
*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __RAS_SYS_H__
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#define __RAS_SYS_H__
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#include <linux/stdarg.h>
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#include <linux/printk.h>
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#include <linux/dev_printk.h>
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#include "amdgpu.h"
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#define RAS_DEV_ERR(device, fmt, ...) \
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do { \
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if (device) \
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dev_err(((struct amdgpu_device *)device)->dev, fmt, ##__VA_ARGS__); \
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else \
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printk(KERN_ERR fmt, ##__VA_ARGS__); \
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} while (0)
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#define RAS_DEV_WARN(device, fmt, ...) \
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do { \
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if (device) \
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dev_warn(((struct amdgpu_device *)device)->dev, fmt, ##__VA_ARGS__); \
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else \
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printk(KERN_WARNING fmt, ##__VA_ARGS__); \
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} while (0)
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#define RAS_DEV_INFO(device, fmt, ...) \
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do { \
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if (device) \
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dev_info(((struct amdgpu_device *)device)->dev, fmt, ##__VA_ARGS__); \
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else \
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printk(KERN_INFO fmt, ##__VA_ARGS__); \
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} while (0)
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#define RAS_DEV_DBG(device, fmt, ...) \
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do { \
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if (device) \
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dev_dbg(((struct amdgpu_device *)device)->dev, fmt, ##__VA_ARGS__); \
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else \
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printk(KERN_DEBUG fmt, ##__VA_ARGS__); \
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} while (0)
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#define RAS_INFO(fmt, ...) printk(KERN_INFO fmt, ##__VA_ARGS__)
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#define RAS_DEV_RREG32_SOC15(dev, ip, inst, reg) \
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({ \
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struct amdgpu_device *adev = (struct amdgpu_device *)dev; \
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__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
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0, ip##_HWIP, inst); \
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})
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#define RAS_DEV_WREG32_SOC15(dev, ip, inst, reg, value) \
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({ \
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struct amdgpu_device *adev = (struct amdgpu_device *)dev; \
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__WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), \
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value, 0, ip##_HWIP, inst); \
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})
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/* GET_INST returns the physical instance corresponding to a logical instance */
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#define RAS_GET_INST(dev, ip, inst) \
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({ \
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struct amdgpu_device *adev = (struct amdgpu_device *)dev; \
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adev->ip_map.logical_to_dev_inst ? \
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adev->ip_map.logical_to_dev_inst(adev, ip##_HWIP, inst) : inst; \
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})
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#define RAS_GET_MASK(dev, ip, mask) \
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({ \
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struct amdgpu_device *adev = (struct amdgpu_device *)dev; \
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(adev->ip_map.logical_to_dev_mask ? \
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adev->ip_map.logical_to_dev_mask(adev, ip##_HWIP, mask) : mask); \
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})
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static inline void *ras_radix_tree_delete_iter(struct radix_tree_root *root, void *iter)
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{
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return radix_tree_delete(root, ((struct radix_tree_iter *)iter)->index);
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}
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static inline long ras_wait_event_interruptible_timeout(void *wq_head,
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int (*condition)(void *param), void *param, unsigned int timeout)
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{
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return wait_event_interruptible_timeout(*(wait_queue_head_t *)wq_head,
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condition(param), timeout);
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}
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extern const struct ras_sys_func amdgpu_ras_sys_fn;
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#endif
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