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drm/amd/ras: Amdgpu handle ras ioctl command
Amdgpu handle ras ioctl command. V2: Remove non-standard device information. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
YiPeng Chai
committed by
Alex Deucher
Alex Deucher
parent
764e868928
commit
b658fadf1c
363
drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c
Normal file
363
drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c
Normal file
@@ -0,0 +1,363 @@
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// SPDX-License-Identifier: MIT
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/*
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* Copyright 2025 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
|
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
|
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <linux/pci.h>
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#include "amdgpu.h"
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#include "amdgpu_ras.h"
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#include "ras_sys.h"
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#include "amdgpu_ras_cmd.h"
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#include "amdgpu_ras_mgr.h"
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/* inject address is 52 bits */
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#define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52)
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#define AMDGPU_RAS_TYPE_RASCORE 0x1
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#define AMDGPU_RAS_TYPE_AMDGPU 0x2
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#define AMDGPU_RAS_TYPE_VF 0x3
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static int amdgpu_ras_query_interface_info(struct ras_core_context *ras_core,
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struct ras_cmd_ioctl *cmd)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
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struct ras_query_interface_info_rsp *output_data =
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(struct ras_query_interface_info_rsp *)cmd->output_buff_raw;
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int ret;
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if (cmd->input_size != sizeof(struct ras_query_interface_info_req))
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return RAS_CMD__ERROR_INVALID_INPUT_SIZE;
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ret = ras_cmd_query_interface_info(ras_core, output_data);
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if (!ret) {
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output_data->plat_major_ver = 0;
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output_data->plat_minor_ver = 0;
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output_data->interface_type = amdgpu_sriov_vf(adev) ?
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RAS_CMD_INTERFACE_TYPE_VF : RAS_CMD_INTERFACE_TYPE_AMDGPU;
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cmd->output_size = sizeof(struct ras_query_interface_info_rsp);
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}
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return ret;
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}
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static struct ras_core_context *ras_cmd_get_ras_core(uint64_t dev_handle)
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{
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struct ras_core_context *ras_core;
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if (!dev_handle || (dev_handle == RAS_CMD_DEV_HANDLE_MAGIC))
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return NULL;
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ras_core = (struct ras_core_context *)(dev_handle ^ RAS_CMD_DEV_HANDLE_MAGIC);
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if (ras_cmd_get_dev_handle(ras_core) == dev_handle)
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return ras_core;
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return NULL;
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}
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static int amdgpu_ras_get_devices_info(struct ras_core_context *ras_core,
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struct ras_cmd_ioctl *cmd)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
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struct ras_cmd_devices_info_rsp *output_data =
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(struct ras_cmd_devices_info_rsp *)cmd->output_buff_raw;
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struct ras_cmd_dev_info *dev_info;
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dev_info = &output_data->devs[0];
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dev_info->dev_handle = ras_cmd_get_dev_handle(ras_core);
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dev_info->oam_id = adev->smuio.funcs->get_socket_id(adev);
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dev_info->ecc_enabled = 1;
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dev_info->ecc_supported = 1;
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output_data->dev_num = 1;
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output_data->version = 0;
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cmd->output_size = sizeof(struct ras_cmd_devices_info_rsp);
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return 0;
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}
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static int amdgpu_ras_trigger_error_prepare(struct ras_core_context *ras_core,
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struct ras_cmd_inject_error_req *block_info)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
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int ret;
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if (block_info->block_id == TA_RAS_BLOCK__XGMI_WAFL) {
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if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
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RAS_DEV_WARN(adev, "Failed to disallow df cstate");
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ret = amdgpu_dpm_set_pm_policy(adev, PP_PM_POLICY_XGMI_PLPD, XGMI_PLPD_DISALLOW);
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if (ret && (ret != -EOPNOTSUPP))
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RAS_DEV_WARN(adev, "Failed to disallow XGMI power down");
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}
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return 0;
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}
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static int amdgpu_ras_trigger_error_end(struct ras_core_context *ras_core,
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struct ras_cmd_inject_error_req *block_info)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
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int ret;
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if (block_info->block_id == TA_RAS_BLOCK__XGMI_WAFL) {
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if (amdgpu_ras_intr_triggered())
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return 0;
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ret = amdgpu_dpm_set_pm_policy(adev, PP_PM_POLICY_XGMI_PLPD, XGMI_PLPD_DEFAULT);
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if (ret && (ret != -EOPNOTSUPP))
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RAS_DEV_WARN(adev, "Failed to allow XGMI power down");
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if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW))
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RAS_DEV_WARN(adev, "Failed to allow df cstate");
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}
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return 0;
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}
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static uint64_t local_addr_to_xgmi_global_addr(struct ras_core_context *ras_core,
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uint64_t addr)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
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struct amdgpu_xgmi *xgmi = &adev->gmc.xgmi;
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return (addr + xgmi->physical_node_id * xgmi->node_segment_size);
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}
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static int amdgpu_ras_inject_error(struct ras_core_context *ras_core,
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struct ras_cmd_ioctl *cmd, void *data)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
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struct ras_cmd_inject_error_req *req =
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(struct ras_cmd_inject_error_req *)cmd->input_buff_raw;
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int ret = RAS_CMD__ERROR_GENERIC;
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if (req->block_id == RAS_BLOCK_ID__UMC) {
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if (amdgpu_ras_mgr_check_retired_addr(adev, req->address)) {
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RAS_DEV_WARN(ras_core->dev,
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"RAS WARN: inject: 0x%llx has already been marked as bad!\n",
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req->address);
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return RAS_CMD__ERROR_ACCESS_DENIED;
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}
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if ((req->address >= adev->gmc.mc_vram_size &&
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adev->gmc.mc_vram_size) ||
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(req->address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
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RAS_DEV_WARN(adev, "RAS WARN: input address 0x%llx is invalid.",
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req->address);
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return RAS_CMD__ERROR_INVALID_INPUT_DATA;
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}
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/* Calculate XGMI relative offset */
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if (adev->gmc.xgmi.num_physical_nodes > 1 &&
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req->block_id != RAS_BLOCK_ID__GFX) {
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req->address = local_addr_to_xgmi_global_addr(ras_core, req->address);
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}
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}
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amdgpu_ras_trigger_error_prepare(ras_core, req);
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ret = rascore_handle_cmd(ras_core, cmd, data);
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amdgpu_ras_trigger_error_end(ras_core, req);
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if (ret) {
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RAS_DEV_ERR(adev, "ras inject block %u failed %d\n", req->block_id, ret);
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ret = RAS_CMD__ERROR_ACCESS_DENIED;
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}
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return ret;
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}
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static int amdgpu_ras_get_ras_safe_fb_addr_ranges(struct ras_core_context *ras_core,
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struct ras_cmd_ioctl *cmd, void *data)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
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struct ras_cmd_dev_handle *input_data =
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(struct ras_cmd_dev_handle *)cmd->input_buff_raw;
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struct ras_cmd_ras_safe_fb_address_ranges_rsp *ranges =
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(struct ras_cmd_ras_safe_fb_address_ranges_rsp *)cmd->output_buff_raw;
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struct amdgpu_mem_partition_info *mem_ranges;
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uint32_t i = 0;
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if (cmd->input_size != sizeof(*input_data))
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return RAS_CMD__ERROR_INVALID_INPUT_DATA;
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mem_ranges = adev->gmc.mem_partitions;
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for (i = 0; i < adev->gmc.num_mem_partitions; i++) {
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ranges->range[i].start = mem_ranges[i].range.fpfn << AMDGPU_GPU_PAGE_SHIFT;
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ranges->range[i].size = mem_ranges[i].size;
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ranges->range[i].idx = i;
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}
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ranges->num_ranges = adev->gmc.num_mem_partitions;
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ranges->version = 0;
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cmd->output_size = sizeof(struct ras_cmd_ras_safe_fb_address_ranges_rsp);
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return RAS_CMD__SUCCESS;
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}
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static int ras_translate_fb_address(struct ras_core_context *ras_core,
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enum ras_fb_addr_type src_type,
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enum ras_fb_addr_type dest_type,
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union ras_translate_fb_address *src_addr,
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union ras_translate_fb_address *dest_addr)
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{
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uint64_t soc_phy_addr;
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int ret = RAS_CMD__SUCCESS;
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/* Does not need to be queued as event as this is a SW translation */
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switch (src_type) {
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case RAS_FB_ADDR_SOC_PHY:
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soc_phy_addr = src_addr->soc_phy_addr;
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break;
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case RAS_FB_ADDR_BANK:
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ret = ras_cmd_translate_bank_to_soc_pa(ras_core,
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src_addr->bank_addr, &soc_phy_addr);
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if (ret)
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return RAS_CMD__ERROR_GENERIC;
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break;
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default:
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return RAS_CMD__ERROR_INVALID_CMD;
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}
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switch (dest_type) {
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case RAS_FB_ADDR_SOC_PHY:
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dest_addr->soc_phy_addr = soc_phy_addr;
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break;
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case RAS_FB_ADDR_BANK:
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ret = ras_cmd_translate_soc_pa_to_bank(ras_core,
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soc_phy_addr, &dest_addr->bank_addr);
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if (ret)
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return RAS_CMD__ERROR_GENERIC;
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break;
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default:
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return RAS_CMD__ERROR_INVALID_CMD;
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}
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return ret;
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}
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static int amdgpu_ras_translate_fb_address(struct ras_core_context *ras_core,
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struct ras_cmd_ioctl *cmd, void *data)
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{
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struct ras_cmd_translate_fb_address_req *req_buff =
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(struct ras_cmd_translate_fb_address_req *)cmd->input_buff_raw;
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struct ras_cmd_translate_fb_address_rsp *rsp_buff =
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(struct ras_cmd_translate_fb_address_rsp *)cmd->output_buff_raw;
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int ret = RAS_CMD__ERROR_GENERIC;
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if (cmd->input_size != sizeof(struct ras_cmd_translate_fb_address_req))
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return RAS_CMD__ERROR_INVALID_INPUT_SIZE;
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if ((req_buff->src_addr_type >= RAS_FB_ADDR_UNKNOWN) ||
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(req_buff->dest_addr_type >= RAS_FB_ADDR_UNKNOWN))
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return RAS_CMD__ERROR_INVALID_INPUT_DATA;
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ret = ras_translate_fb_address(ras_core, req_buff->src_addr_type,
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req_buff->dest_addr_type, &req_buff->trans_addr, &rsp_buff->trans_addr);
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if (ret)
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return RAS_CMD__ERROR_GENERIC;
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rsp_buff->version = 0;
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cmd->output_size = sizeof(struct ras_cmd_translate_fb_address_rsp);
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return RAS_CMD__SUCCESS;
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}
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static struct ras_cmd_func_map amdgpu_ras_cmd_maps[] = {
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{RAS_CMD__INJECT_ERROR, amdgpu_ras_inject_error},
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{RAS_CMD__GET_SAFE_FB_ADDRESS_RANGES, amdgpu_ras_get_ras_safe_fb_addr_ranges},
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{RAS_CMD__TRANSLATE_FB_ADDRESS, amdgpu_ras_translate_fb_address},
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};
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int amdgpu_ras_handle_cmd(struct ras_core_context *ras_core, struct ras_cmd_ioctl *cmd, void *data)
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{
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struct ras_cmd_func_map *ras_cmd = NULL;
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int i, res;
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for (i = 0; i < ARRAY_SIZE(amdgpu_ras_cmd_maps); i++) {
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if (cmd->cmd_id == amdgpu_ras_cmd_maps[i].cmd_id) {
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ras_cmd = &amdgpu_ras_cmd_maps[i];
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break;
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}
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}
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if (ras_cmd)
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res = ras_cmd->func(ras_core, cmd, NULL);
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else
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res = RAS_CMD__ERROR_UKNOWN_CMD;
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return res;
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}
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int amdgpu_ras_cmd_ioctl_handler(struct ras_core_context *ras_core,
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uint8_t *cmd_buf, uint32_t buf_size)
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{
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struct ras_cmd_ioctl *cmd = (struct ras_cmd_ioctl *)cmd_buf;
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struct ras_core_context *cmd_core = NULL;
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struct ras_cmd_dev_handle *cmd_handle = NULL;
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int timeout = 60;
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int res;
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cmd->cmd_res = RAS_CMD__ERROR_INVALID_CMD;
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cmd->output_size = 0;
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if (!ras_core_is_enabled(ras_core))
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return RAS_CMD__ERROR_ACCESS_DENIED;
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if (cmd->cmd_id == RAS_CMD__QUERY_INTERFACE_INFO) {
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cmd->cmd_res = amdgpu_ras_query_interface_info(ras_core, cmd);
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} else if (cmd->cmd_id == RAS_CMD__GET_DEVICES_INFO) {
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cmd->cmd_res = amdgpu_ras_get_devices_info(ras_core, cmd);
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} else {
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cmd_handle = (struct ras_cmd_dev_handle *)cmd->input_buff_raw;
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cmd_core = ras_cmd_get_ras_core(cmd_handle->dev_handle);
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if (!cmd_core)
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return RAS_CMD__ERROR_INVALID_INPUT_DATA;
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while (ras_core_gpu_in_reset(cmd_core)) {
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msleep(1000);
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if (!timeout--)
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return RAS_CMD__ERROR_TIMEOUT;
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}
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if (!ras_core_is_enabled(cmd_core))
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return RAS_CMD__ERROR_ACCESS_DENIED;
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res = amdgpu_ras_handle_cmd(cmd_core, cmd, NULL);
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if (res == RAS_CMD__ERROR_UKNOWN_CMD)
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res = rascore_handle_cmd(cmd_core, cmd, NULL);
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cmd->cmd_res = res;
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}
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if ((cmd->cmd_res == RAS_CMD__SUCCESS) &&
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((cmd->output_size + sizeof(*cmd)) > buf_size)) {
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RAS_INFO("Insufficient command buffer size 0x%x!\n", buf_size);
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return RAS_CMD__SUCCESS_EXEED_BUFFER;
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}
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return RAS_CMD__SUCCESS;
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}
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55
drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.h
Normal file
55
drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.h
Normal file
@@ -0,0 +1,55 @@
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/* SPDX-License-Identifier: MIT */
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/*
|
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* Copyright 2025 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
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#ifndef __AMDGPU_RAS_CMD_H__
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#define __AMDGPU_RAS_CMD_H__
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#include "ras.h"
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enum amdgpu_ras_cmd_id {
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RAS_CMD__AMDGPU_BEGIN = RAS_CMD_ID_AMDGPU_START,
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RAS_CMD__TRANSLATE_MEMORY_FD,
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RAS_CMD__AMDGPU_SUPPORTED_MAX = RAS_CMD_ID_AMDGPU_END,
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};
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struct ras_cmd_translate_memory_fd_req {
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struct ras_cmd_dev_handle dev;
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uint32_t type;
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uint32_t fd;
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uint64_t address;
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uint32_t reserved[4];
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};
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struct ras_cmd_translate_memory_fd_rsp {
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||||
uint32_t version;
|
||||
uint32_t padding;
|
||||
uint64_t start;
|
||||
uint64_t size;
|
||||
uint32_t reserved[2];
|
||||
};
|
||||
|
||||
int amdgpu_ras_handle_cmd(struct ras_core_context *ras_core,
|
||||
struct ras_cmd_ioctl *cmd, void *data);
|
||||
int amdgpu_ras_cmd_ioctl_handler(struct ras_core_context *ras_core,
|
||||
uint8_t *cmd_buf, uint32_t buf_size);
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user