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arm64: dts: renesas: r9a08g045: Add TSU node

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Add TSU node along with thermal zones and keep it enabled in the SoC DTSI.
The temperature reported by the TSU can only be read through channel 8 of
the ADC. Therefore, enable the ADC by default.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://patch.msgid.link/20250810122125.792966-4-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Claudiu Beznea
2025-08-10 15:21:24 +03:00
committed by Geert Uytterhoeven
parent 3a86608788
commit ee9bfab464
2 changed files with 48 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

49
arch/arm64/boot/dts/renesas/r9a08g045.dtsi
View File

@@ -233,7 +233,6 @@
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
status = "disabled";
channel@0 {
reg = <0>;
@@ -272,6 +271,17 @@
};
};
tsu: thermal@10059000 {
compatible = "renesas,r9a08g045-tsu";
reg = <0 0x10059000 0 0x1000>;
clocks = <&cpg CPG_MOD R9A08G045_TSU_PCLK>;
resets = <&cpg R9A08G045_TSU_PRESETN>;
power-domains = <&cpg>;
#thermal-sensor-cells = <0>;
io-channels = <&adc 8>;
io-channel-names = "tsu";
};
i3c: i3c@1005b000 {
compatible = "renesas,r9a08g045-i3c";
reg = <0 0x1005b000 0 0x1000>;
@@ -753,6 +763,43 @@
"hyp-virt";
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsu>;
sustainable-power = <423>;
cooling-maps {
map0 {
trip = <&cpu_alert0>;
cooling-device = <&cpu0 0 2>;
contribution = <1024>;
};
};
trips {
cpu_crit: cpu-critical {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
cpu_alert1: trip-point1 {
temperature = <90000>;
hysteresis = <1000>;
type = "passive";
};
cpu_alert0: trip-point0 {
temperature = <85000>;
hysteresis = <1000>;
type = "passive";
};
};
};
};
vbattb_xtal: vbattb-xtal {
compatible = "fixed-clock";
#clock-cells = <0>;

4
arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
View File

@@ -84,10 +84,6 @@
};
};
&adc {
status = "okay";
};
#if SW_CONFIG3 == SW_ON
&eth0 {
pinctrl-0 = <&eth0_pins>;