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Merge tag 'mtk-dts64-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt

Browse Source 
MediaTek ARM64 Device Tree updates

This adds support for new boards and variants based on different
already supported MediaTek SoCs, and improves support for current
boards.

In particular:
 - New machines:
    - MT7988 BananaPi R4 Pro eMMC and SD router board with support
      for both Key-M and Key-E M.2 slots through DTB Overlays
    - MT8370 Grinn GenioSBC-510 (GenioSOM-510 + GenioBoard Edge AI)
    - MT8390 Grinn GenioSBC-700 (GenioSOM-700 + GenioBoard Edge AI)
 - New variant: MT8395 MediaTek Genio 1200 EVK with UFS

...preparation for new SoCs (MT8196 Kompanio Ultra, a clone of the
   MT6991 Dimensity 9400, and MT6878 Dimensity 7300) with the
   addition of GCE/PIO definitions

...improvements for already supported SoCs and machines:
 - MT7622/7981b/7986a/7988a gain support for reading SoC UUID from
   eFuse, used to generate a persistent MAC address on boards that
   don't have any factory-assigned addresses.
 - MT7986 BananaPi R3 gets changes to its default fan PWM speed to
   improve compatibility with cheaper fans (usually coming with the
   heatsink+fan combos)
 - The MT7981b OpenWRT One router sees general support improvements
   with the enablement of its UART-0 console and correct pinmuxing
   for the same, addition of reserved memory for Trusted Firmware A,
   its SPI NOR Flash (for recovery system, WiFi eeprom data and ETH
   MAC address from factory), and board LEDs.
 - MT8365 gets support for its Mali G52 MC1 GPU, which gets enabled
   in the MediaTek Genio 350 EVK board

...and a dt-bindings warning fix for MT8183 machines through trivial
changes to rename the audiosys and afe nodes to reflect bindings.

* tag 'mtk-dts64-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux: (27 commits)
  arm64: dts: mediatek: mt7981b-openwrt-one: Enable software leds
  arm64: dts: mediatek: mt7981b-openwrt-one: Enable SPI NOR
  arm64: dts: mediatek: mt7988a-bpi-r4pro: Add mmc overlays
  arm64: dts: mediatek: mt7988a-bpi-r4-pro: Add PCIe overlays
  arm64: dts: mediatek: mt7988: Add devicetree for BananaPi R4 Pro
  arm64: dts: mediatek: mt7988: Disable 2.5G phy and enable at board layer
  dt-bindings: arm: mediatek: add BPI-R4 Pro board
  arm64: dts: mediatek: Add GCE header for MT8196
  arm64: dts: mediatek: mt7981b: Add reserved memory for TF-A
  arm64: dts: mediatek: mt7981b: Configure UART0 pinmux
  arm64: dts: mediatek: mt8365-evk: Enable GPU support
  arm64: dts: mediatek: mt8365: Add GPU support
  arm64: dts: mediatek: mt8395-genio-1200-evk: Describe CPU supplies
  arm64: dts: mediatek: Add MT6878 pinmux macro header file
  arm64: dts: mediatek: mt7986-bpi-r3: Change fan PWM value for mid speed
  arm64: dts: mediatek: mt8370-grinn-genio-510-sbc: Add Grinn GenioSBC-510
  arm64: dts: mediatek: mt8390-genio-700-evk: Add Grinn GenioSBC-700
  arm64: dts: mediatek: mt7988a: add 'soc-uuid' cell to efuse
  arm64: dts: mediatek: mt7981b: add 'soc-uuid' cell to efuse
  arm64: dts: mediatek: mt7986a: add 'soc-uuid' cell to efuse
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2025-11-21 16:39:35 +01:00
parent c4aee1ad41 9b2d2beaef
commit 3350e81c62
28 changed files with 4798 additions and 1198 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
Documentation/devicetree/bindings/arm/mediatek.yaml
View File

@@ -114,6 +114,12 @@ properties:
- const: bananapi,bpi-r4-2g5
- const: bananapi,bpi-r4
- const: mediatek,mt7988a
- items:
- enum:
- bananapi,bpi-r4-pro-4e
- bananapi,bpi-r4-pro-8x
- const: bananapi,bpi-r4-pro
- const: mediatek,mt7988a
- items:
- enum:
- mediatek,mt8127-moose
@@ -446,6 +452,7 @@ properties:
- enum:
- kontron,3-5-sbc-i1200
- mediatek,mt8395-evk
- mediatek,mt8395-evk-ufs
- radxa,nio-12l
- const: mediatek,mt8395
- const: mediatek,mt8195

11
arch/arm64/boot/dts/mediatek/Makefile
View File

@@ -24,6 +24,12 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-2g5.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-emmc.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-4e.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-8x.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-cn15.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-cn18.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-emmc.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-sd.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-sd.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb
@@ -99,8 +105,11 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-genio-510-evk.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-grinn-genio-510-sbc.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk-ufs.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-genio-700-evk.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-grinn-genio-700-sbc.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-kontron-3-5-sbc-i1200.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l-8-hd-panel.dtbo
@@ -111,4 +120,6 @@ DTC_FLAGS_mt7986a-bananapi-bpi-r3 := -@
DTC_FLAGS_mt7986a-bananapi-bpi-r3-mini := -@
DTC_FLAGS_mt7988a-bananapi-bpi-r4 := -@
DTC_FLAGS_mt7988a-bananapi-bpi-r4-2g5 := -@
DTC_FLAGS_mt7988a-bananapi-bpi-r4-pro-4e := -@
DTC_FLAGS_mt7988a-bananapi-bpi-r4-pro-8x := -@
DTC_FLAGS_mt8395-radxa-nio-12l := -@

1201
arch/arm64/boot/dts/mediatek/mt6878-pinfunc.h Normal file
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File diff suppressed because it is too large Load Diff

4
arch/arm64/boot/dts/mediatek/mt7622.dtsi
View File

@@ -278,6 +278,10 @@
#address-cells = <1>;
#size-cells = <1>;
soc-uuid@140 {
reg = <0x140 0x8>;
};
thermal_calibration: calib@198 {
reg = <0x198 0xc>;
};

150
arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts
View File

@@ -3,13 +3,163 @@
/dts-v1/;
#include "mt7981b.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include "dt-bindings/pinctrl/mt65xx.h"
/ {
compatible = "openwrt,one", "mediatek,mt7981b";
model = "OpenWrt One";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@40000000 {
reg = <0 0x40000000 0 0x40000000>;
device_type = "memory";
};
pwm-leds {
compatible = "pwm-leds";
led-0 {
color = <LED_COLOR_ID_WHITE>;
default-brightness = <0>;
function = LED_FUNCTION_STATUS;
max-brightness = <255>;
pwms = <&pwm 0 10000>;
};
led-1 {
color = <LED_COLOR_ID_GREEN>;
default-brightness = <0>;
function = LED_FUNCTION_STATUS;
max-brightness = <255>;
pwms = <&pwm 1 10000>;
};
};
gpio-leds {
compatible = "gpio-leds";
led-0 {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_STATUS;
gpios = <&pio 9 GPIO_ACTIVE_HIGH>;
};
led-1 {
color = <LED_COLOR_ID_AMBER>;
function = LED_FUNCTION_LAN;
gpios = <&pio 34 GPIO_ACTIVE_LOW>;
linux,default-trigger = "netdev";
};
led-2 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
gpios = <&pio 35 GPIO_ACTIVE_LOW>;
linux,default-trigger = "netdev";
};
};
};
&pio {
pwm_pins: pwm-pins {
mux {
function = "pwm";
groups = "pwm0_0", "pwm1_1";
};
};
spi2_flash_pins: spi2-pins {
mux {
function = "spi";
groups = "spi2";
};
conf-pu {
bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
drive-strength = <8>;
pins = "SPI2_CS", "SPI2_WP";
};
conf-pd {
bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
drive-strength = <8>;
pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
};
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm_pins>;
status = "okay";
};
&spi2 {
pinctrl-names = "default";
pinctrl-0 = <&spi2_flash_pins>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
#address-cells = <1>;
#size-cells = <1>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
reg = <0x00000 0x40000>;
label = "bl2-nor";
};
partition@40000 {
reg = <0x40000 0xc0000>;
label = "factory";
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
wifi_factory_calibration: eeprom@0 {
reg = <0x0 0x1000>;
};
wan_factory_mac: macaddr@24 {
reg = <0x24 0x6>;
compatible = "mac-base";
#nvmem-cell-cells = <1>;
};
};
};
partition@100000 {
reg = <0x100000 0x80000>;
label = "fip-nor";
};
partition@180000 {
reg = <0x180000 0xc80000>;
label = "recovery";
};
};
};
};
&uart0 {
status = "okay";
};

35
arch/arm64/boot/dts/mediatek/mt7981b.dtsi
View File

@@ -41,6 +41,18 @@
method = "smc";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
secmon_reserved: secmon@43000000 {
reg = <0 0x43000000 0 0x30000>;
no-map;
};
};
soc {
compatible = "simple-bus";
ranges;
@@ -82,7 +94,7 @@
#clock-cells = <1>;
};
pwm@10048000 {
pwm: pwm@10048000 {
compatible = "mediatek,mt7981-pwm";
reg = <0 0x10048000 0 0x1000>;
clocks = <&infracfg CLK_INFRA_PWM_STA>,
@@ -94,7 +106,7 @@
#pwm-cells = <2>;
};
serial@11002000 {
uart0: serial@11002000 {
compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x100>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
@@ -102,10 +114,12 @@
clocks = <&infracfg CLK_INFRA_UART0_SEL>,
<&infracfg CLK_INFRA_UART0_CK>;
clock-names = "baud", "bus";
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "disabled";
};
serial@11003000 {
uart1: serial@11003000 {
compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x100>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
@@ -116,7 +130,7 @@
status = "disabled";
};
serial@11004000 {
uart2: serial@11004000 {
compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x100>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
@@ -142,7 +156,7 @@
status = "disabled";
};
spi@11009000 {
spi2: spi@11009000 {
compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm";
reg = <0 0x11009000 0 0x1000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
@@ -229,6 +243,13 @@
gpio-controller;
#gpio-cells = <2>;
#interrupt-cells = <2>;
uart0_pins: uart0-pins {
mux {
function = "uart";
groups = "uart0";
};
};
};
efuse@11f20000 {
@@ -237,6 +258,10 @@
#address-cells = <1>;
#size-cells = <1>;
soc-uuid@140 {
reg = <0x140 0x10>;
};
thermal_calibration: thermal-calib@274 {
reg = <0x274 0xc>;
};

2
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
View File

@@ -42,7 +42,7 @@
compatible = "pwm-fan";
#cooling-cells = <2>;
/* cooling level (0, 1, 2) - pwm inverted */
cooling-levels = <255 96 0>;
cooling-levels = <255 40 0>;
pwms = <&pwm 0 10000>;
status = "okay";
};

4
arch/arm64/boot/dts/mediatek/mt7986a.dtsi
View File

@@ -450,6 +450,10 @@
#address-cells = <1>;
#size-cells = <1>;
soc-uuid@140 {
reg = <0x140 0x8>;
};
thermal_calibration: calib@274 {
reg = <0x274 0xc>;
};

1
arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts
View File

@@ -19,4 +19,5 @@
&int_2p5g_phy {
pinctrl-0 = <&i2p5gbe_led0_pins>;
pinctrl-names = "i2p5gbe-led";
status = "okay";
};

16
arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-4e.dts Normal file
View File

@@ -0,0 +1,16 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2025 MediaTek Inc.
* Author: Frank Wunderlich <frank-w@public-files.de>
*/
/dts-v1/;
#include "mt7988a-bananapi-bpi-r4-pro.dtsi"
/ {
model = "Bananapi BPI-R4";
compatible = "bananapi,bpi-r4-pro-4e",
"bananapi,bpi-r4-pro",
"mediatek,mt7988a";
};

16
arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-8x.dts Normal file
View File

@@ -0,0 +1,16 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2025 MediaTek Inc.
* Author: Frank Wunderlich <frank-w@public-files.de>
*/
/dts-v1/;
#include "mt7988a-bananapi-bpi-r4-pro.dtsi"
/ {
model = "Bananapi BPI-R4";
compatible = "bananapi,bpi-r4-pro-8x",
"bananapi,bpi-r4-pro",
"mediatek,mt7988a";
};

20
arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn15.dtso Normal file
View File

@@ -0,0 +1,20 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2025 MediaTek Inc.
* Author: Frank Wunderlich <frank-w@public-files.de>
*/
/* This enables key-b slot CN15 on pcie2(11280000 1L0) on BPI-R4-Pro */
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "bananapi,bpi-r4-pro", "mediatek,mt7988a";
};
&{/soc/pinctrl@1001f000/pcie-2-hog} {
output-low;
};

20
arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn18.dtso Normal file
View File

@@ -0,0 +1,20 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2025 MediaTek Inc.
* Author: Frank Wunderlich <frank-w@public-files.de>
*/
/* This enables key-b slot CN18 on pcie3(11290000 1L1) on BPI-R4-Pro */
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "bananapi,bpi-r4-pro", "mediatek,mt7988a";
};
&{/soc/pinctrl@1001f000/pcie-3-hog} {
output-low;
};

33
arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-emmc.dtso Normal file
View File

@@ -0,0 +1,33 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 MediaTek Inc.
* Author: Frank Wunderlich <frank-w@public-files.de>
*/
/dts-v1/;
/plugin/;
/ {
compatible = "bananapi,bpi-r4-pro", "mediatek,mt7988a";
};
&{/soc/mmc@11230000} {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_pins_emmc_51>;
pinctrl-1 = <&mmc0_pins_emmc_51>;
bus-width = <8>;
max-frequency = <200000000>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
hs400-ds-delay = <0x12814>;
vqmmc-supply = <&reg_1p8v>;
vmmc-supply = <&reg_3p3v>;
non-removable;
no-sd;
no-sdio;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
};

31
arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-sd.dtso Normal file
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@@ -0,0 +1,31 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2023 MediaTek Inc.
* Author: Frank Wunderlich <frank-w@public-files.de>
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "bananapi,bpi-r4-pro", "mediatek,mt7988a";
};
&{/soc/mmc@11230000} {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_pins_sdcard>;
pinctrl-1 = <&mmc0_pins_sdcard>;
cd-gpios = <&pio 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
max-frequency = <48000000>;
cap-sd-highspeed;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_3p3v>;
no-mmc;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
};

534
arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi Normal file
View File

@@ -0,0 +1,534 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2025 MediaTek Inc.
* Author: Sam.Shih <sam.shih@mediatek.com>
* Author: Frank Wunderlich <frank-w@public-files.de>
*/
/dts-v1/;
#include "mt7988a.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
/ {
aliases {
ethernet0 = &gmac0;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
/* PCA9548 (0-0070) provides 4 i2c channels */
i2c3 = &imux0;
i2c4 = &imux1_sfp1;
i2c5 = &imux2_sfp2;
i2c6 = &imux3_wifi;
};
chosen {
stdout-path = &serial0;
};
fan: pwm-fan {
compatible = "pwm-fan";
/* cooling level (0, 1, 2, 3) : (0% duty, 30% duty, 50% duty, 100% duty) */
cooling-levels = <0 80 128 255>;
pinctrl-0 = <&pwm0_pins>;
pinctrl-names = "default";
pwms = <&pwm 0 50000>;
#cooling-cells = <2>;
};
gpio-keys {
compatible = "gpio-keys";
button-reset {
label = "reset";
gpios = <&pio 13 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
button-wps {
label = "WPS";
gpios = <&pio 14 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
gpio-leds {
compatible = "gpio-leds";
led_red: sys-led-red {
color = <LED_COLOR_ID_RED>;
gpios = <&pca9555 15 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
led_blue: sys-led-blue {
color = <LED_COLOR_ID_BLUE>;
gpios = <&pca9555 14 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
};
reg_1p8v: regulator-dvdd1v8 {
compatible = "regulator-fixed";
regulator-name = "DVDD1V8_SOC";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3v3vd {
compatible = "regulator-fixed";
regulator-name = "3V3VD";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
/* SFP1 cage (LAN) */
sfp1: sfp1 {
compatible = "sff,sfp";
i2c-bus = <&imux1_sfp1>;
los-gpios = <&pio 70 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&pio 69 GPIO_ACTIVE_LOW>;
tx-disable-gpios = <&pio 21 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <3000>;
};
/* SFP2 cage (WAN) */
sfp2: sfp2 {
compatible = "sff,sfp";
i2c-bus = <&imux2_sfp2>;
los-gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&pio 1 GPIO_ACTIVE_LOW>;
tx-disable-gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <3000>;
};
};
&cci {
proc-supply = <&rt5190_buck3>;
};
&cpu0 {
proc-supply = <&rt5190_buck3>;
};
&cpu1 {
proc-supply = <&rt5190_buck3>;
};
&cpu2 {
proc-supply = <&rt5190_buck3>;
};
&cpu3 {
proc-supply = <&rt5190_buck3>;
};
&cpu_thermal {
trips {
cpu_trip_hot: hot {
temperature = <120000>;
hysteresis = <2000>;
type = "hot";
};
cpu_trip_active_high: active-high {
temperature = <115000>;
hysteresis = <2000>;
type = "active";
};
cpu_trip_active_med: active-med {
temperature = <85000>;
hysteresis = <2000>;
type = "active";
};
cpu_trip_active_low: active-low {
temperature = <40000>;
hysteresis = <2000>;
type = "active";
};
};
cooling-maps {
map-cpu-active-high {
/* active: set fan to cooling level 2 */
cooling-device = <&fan 3 3>;
trip = <&cpu_trip_active_high>;
};
map-cpu-active-med {
/* active: set fan to cooling level 1 */
cooling-device = <&fan 2 2>;
trip = <&cpu_trip_active_med>;
};
map-cpu-active-low {
/* active: set fan to cooling level 0 */
cooling-device = <&fan 1 1>;
trip = <&cpu_trip_active_low>;
};
};
};
&eth {
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
status = "okay";
};
&fan {
pinctrl-0 = <&pwm0_pins>;
pinctrl-names = "default";
pwms = <&pwm 0 50000>;
status = "okay";
};
&gmac0 {
status = "okay";
};
&gsw_phy0 {
pinctrl-0 = <&gbe0_led0_pins>;
pinctrl-names = "gbe-led";
};
&gsw_phy0_led0 {
color = <LED_COLOR_ID_YELLOW>;
status = "okay";
};
&gsw_port0 {
label = "mgmt";
};
/* R4Pro has only port 0 connected, so disable the others */
&gsw_phy1 {
status = "disabled";
};
&gsw_port1 {
status = "disabled";
};
&gsw_phy2 {
status = "disabled";
};
&gsw_port2 {
status = "disabled";
};
&gsw_phy3 {
status = "disabled";
};
&gsw_port3 {
status = "disabled";
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
rt5190a_64: rt5190a@64 {
compatible = "richtek,rt5190a";
reg = <0x64>;
vin2-supply = <&rt5190_buck1>;
vin3-supply = <&rt5190_buck1>;
vin4-supply = <&rt5190_buck1>;
regulators {
rt5190_buck1: buck1 {
regulator-name = "rt5190a-buck1";
regulator-min-microvolt = <5090000>;
regulator-max-microvolt = <5090000>;
regulator-allowed-modes =
<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
regulator-boot-on;
regulator-always-on;
};
buck2 {
regulator-name = "vcore";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
regulator-always-on;
};
rt5190_buck3: buck3 {
regulator-name = "vproc";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
regulator-always-on;
};
buck4 {
regulator-name = "rt5190a-buck4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-allowed-modes =
<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
regulator-boot-on;
regulator-always-on;
};
ldo {
regulator-name = "rt5190a-ldo";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
};
&i2c2 {
pinctrl-0 = <&i2c2_1_pins>;
pinctrl-names = "default";
status = "okay";
pca9545: i2c-mux@70 {
compatible = "nxp,pca9545";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
imux0: i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
pca9555: i2c-gpio-expander@20 {
compatible = "nxp,pca9555";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
eeprom@57 {
compatible = "atmel,24c02";
reg = <0x57>;
address-width = <8>;
pagesize = <8>;
size = <256>;
};
};
imux1_sfp1: i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
imux2_sfp2: i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
imux3_wifi: i2c@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
/* mPCIe SIM2 (11300000) */
&pcie0 {
status = "okay";
};
/* mPCIe (11310000 near leds) SIM3 */
&pcie1 {
status = "okay";
};
/* M.2 (11280000) 1L0 key-m SSD1 CN13 / key-b SIM1 CN15 */
&pcie2 {
status = "okay";
};
/* M.2 (11290000) 1L1 key-m SSD2 CN14 / key-b SIM2 CN18 */
&pcie3 {
status = "okay";
};
&pio {
gbe0_led0_pins: gbe0-led0-pins {
mux {
function = "led";
groups = "gbe0_led0";
};
};
i2c0_pins: i2c0-g0-pins {
mux {
function = "i2c";
groups = "i2c0_1";
};
};
i2c1_pins: i2c1-g0-pins {
mux {
function = "i2c";
groups = "i2c1_0";
};
};
i2c2_1_pins: i2c2-g1-pins {
mux {
function = "i2c";
groups = "i2c2_1";
};
};
mdio0_pins: mdio0-pins {
mux {
function = "eth";
groups = "mdc_mdio0";
};
conf {
pins = "SMI_0_MDC", "SMI_0_MDIO";
drive-strength = <8>;
};
};
mmc0_pins_emmc_51: mmc0-emmc-51-pins {
mux {
function = "flash";
groups = "emmc_51";
};
};
mmc0_pins_sdcard: mmc0-sdcard-pins {
mux {
function = "flash";
groups = "sdcard";
};
};
/* 1L0 0=key-b (CN15), 1=key-m (CN13) */
pcie-2-hog {
gpio-hog;
gpios = <79 GPIO_ACTIVE_HIGH>;
output-high;
};
/* 1L1 0=key-b (CN18), 1=key-m (CN14) */
pcie-3-hog {
gpio-hog;
gpios = <63 GPIO_ACTIVE_HIGH>;
output-high;
};
pwm0_pins: pwm0-pins {
mux {
groups = "pwm0";
function = "pwm";
};
};
spi0_flash_pins: spi0-flash-pins {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
};
};
&pwm {
status = "okay";
};
&serial0 {
status = "okay";
};
&spi0 {
pinctrl-0 = <&spi0_flash_pins>;
pinctrl-names = "default";
status = "okay";
spi_nand: nand@0 {
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <52000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
};
};
&spi_nand {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
reg = <0x0 0x200000>;
label = "bl2";
};
partition@200000 {
compatible = "linux,ubi";
reg = <0x200000 0xfe00000>;
label = "ubi";
};
};
};
/* back USB */
&ssusb0 {
/* Use U2P only instead of both U3P/U2P due to U3P serdes shared with pcie2 */
phys = <&xphyu2port0 PHY_TYPE_USB2>;
mediatek,u3p-dis-msk = <1>;
status = "okay";
};
/* front USB */
&ssusb1 {
status = "okay";
};
&switch {
dsa,member = <1 0>;
status = "okay";
};
&tphy {
status = "okay";
};
&watchdog {
status = "okay";
};
&xsphy {
status = "okay";
};

7
arch/arm64/boot/dts/mediatek/mt7988a.dtsi
View File

@@ -418,7 +418,7 @@
nvmem-cell-names = "lvts-calib-data-1";
};
usb@11190000 {
ssusb0: usb@11190000 {
compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci";
reg = <0 0x11190000 0 0x2e00>,
<0 0x11193e00 0 0x0100>;
@@ -714,6 +714,10 @@
#address-cells = <1>;
#size-cells = <1>;
soc-uuid@140 {
reg = <0x140 0x10>;
};
lvts_calibration: calib@918 {
reg = <0x918 0x28>;
};
@@ -995,6 +999,7 @@
int_2p5g_phy: ethernet-phy@15 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <15>;
status = "disabled";
};
};
};

4
arch/arm64/boot/dts/mediatek/mt8183.dtsi
View File

@@ -1445,11 +1445,11 @@
};
};
audiosys: audio-controller@11220000 {
audiosys: clock-controller@11220000 {
compatible = "mediatek,mt8183-audiosys", "syscon";
reg = <0 0x11220000 0 0x1000>;
#clock-cells = <1>;
afe: mt8183-afe-pcm {
afe: audio-controller {
compatible = "mediatek,mt8183-audio";
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
resets = <&watchdog MT8183_TOPRGU_AUDIO_SW_RST>;

612
arch/arm64/boot/dts/mediatek/mt8196-gce.h Normal file
View File

@@ -0,0 +1,612 @@
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
/*
* Copyright (c) 2025 MediaTek Inc.
*
*/
#ifndef __DTS_GCE_MT8196_H
#define __DTS_GCE_MT8196_H
/* GCE Thread Priority
* The GCE core has multiple GCE threads, each of which can independently
* execute its own sequence of instructions.
* However, the GCE threads on the same core cannot run in parallel.
* Different GCE threads can determine thread priority based on the scenario,
* thereby serving different user needs.
*
* Low priority thread is executed when no high priority thread is active.
* Same priority thread is scheduled by round robin.
*/
#define CMDQ_THR_PRIO_LOWEST 0
#define CMDQ_THR_PRIO_1 1
#define CMDQ_THR_PRIO_2 2
#define CMDQ_THR_PRIO_3 3
#define CMDQ_THR_PRIO_4 4
#define CMDQ_THR_PRIO_5 5
#define CMDQ_THR_PRIO_6 6
#define CMDQ_THR_PRIO_HIGHEST 7
/*
* GCE0 Hardware Event IDs
* Different SoCs will have varying numbers of hardware event signals,
* which are sent from the corresponding hardware to the GCE.
* Each hardware event signal corresponds to an event ID in the GCE.
* The CMDQ driver can use the following event ID definitions to allow
* the client driver to use wait and clear APIs provided by CMDQ, enabling
* the GCE to execute operations in the instructions for that event ID.
*
* The event IDs of GCE0 are mainly used by display hardware.
*/
/* CMDQ_EVENT_DISP0_STREAM_SOF0 ~ 15: 0 ~ 15 */
#define CMDQ_EVENT_DISP0_STREAM_SOF(n) (0 + (n))
/* CMDQ_EVENT_DISP0_FRAME_DONE_SEL0 ~ 15: 16 ~ 31 */
#define CMDQ_EVENT_DISP0_FRAME_DONE_SEL(n) (16 + (n))
#define CMDQ_EVENT_DISP0_DISP_WDMA0_TARGET_LINE_END_ENG_EVENT 32
#define CMDQ_EVENT_DISP0_DISP_WDMA0_SW_RST_DONE_ENG_EVENT 33
#define CMDQ_EVENT_DISP0_DISP_POSTMASK1_RST_DONE_ENG_EVENT 34
#define CMDQ_EVENT_DISP0_DISP_POSTMASK0_RST_DONE_ENG_EVENT 35
#define CMDQ_EVENT_DISP0_DISP_MUTEX0_TIMEOUT_ENG_EVENT 36
/* CMDQ_EVENT_DISP0_DISP_MUTEX0_REG_UPDATE_ENG_EVENT0 ~ 15: 37 ~ 52 */
#define CMDQ_EVENT_DISP0_DISP_MUTEX0_REG_UPDATE_ENG_EVENT(n) (37 + (n))
#define CMDQ_EVENT_DISP0_DISP_MUTEX0_GET_RELEASE_ENG_EVENT 53
#define CMDQ_EVENT_DISP0_DISP_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 54
/* CMDQ_EVENT_DISP1_STREAM_SOF0 ~ 15: 55 ~ 70 */
#define CMDQ_EVENT_DISP1_STREAM_SOF(n) (55 + (n))
/* CMDQ_EVENT_DISP1_FRAME_DONE_SEL0 ~ 15: 71 ~ 86 */
#define CMDQ_EVENT_DISP1_FRAME_DONE_SEL(n) (71 + (n))
/* CMDQ_EVENT_DISP1_STREAM_DONE_ENG_EVENT0 ~ 15: 87 ~ 102 */
#define CMDQ_EVENT_DISP1_STREAM_DONE_ENG_EVENT(n) (87 + (n))
/* CMDQ_EVENT_DISP1_REG_UPDATE_DONE_ENG_EVENT0 ~ 15: 103 ~ 118 */
#define CMDQ_EVENT_DISP1_REG_UPDATE_DONE_ENG_EVENT(n) (103 + (n))
#define CMDQ_EVENT_DISP1_OCIP_SUBSYS_SRAM_ISOINT_ENG_EVENT 119
#define CMDQ_EVENT_DISP1_DISP_WDMA4_TARGET_LINE_END_ENG_EVENT 120
#define CMDQ_EVENT_DISP1_DISP_WDMA4_SW_RST_DONE_ENG_EVENT 121
#define CMDQ_EVENT_DISP1_DISP_WDMA3_TARGET_LINE_END_ENG_EVENT 122
#define CMDQ_EVENT_DISP1_DISP_WDMA3_SW_RST_DONE_ENG_EVENT 123
#define CMDQ_EVENT_DISP1_DISP_WDMA2_TARGET_LINE_END_ENG_EVENT 124
#define CMDQ_EVENT_DISP1_DISP_WDMA2_SW_RST_DONE_ENG_EVENT 125
#define CMDQ_EVENT_DISP1_DISP_WDMA1_TARGET_LINE_END_ENG_EVENT 126
#define CMDQ_EVENT_DISP1_DISP_WDMA1_SW_RST_DONE_ENG_EVENT 127
#define CMDQ_EVENT_DISP1_DISP_MUTEX0_TIMEOUT_ENG_EVENT 128
#define CMDQ_EVENT_DISP1_DISP_MUTEX0_GET_RLZ_ENG_EVENT 129
#define CMDQ_EVENT_DISP1_DISP_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 130
#define CMDQ_EVENT_DISP1_DISP_GDMA0_SW_RST_DONE_ENG_EVENT 131
#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VSYNC_START_ENG_EVENT 132
#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VSYNC_END_ENG_EVENT 133
#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VRR_VFP_LAST_SAFE_BLANK_ENG_EVENT 134
#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VFP_START_ENG_EVENT 135
#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VFP_LAST_LINE_ENG_EVENT 136
#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_VDE_END_ENG_EVENT 137
#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_TRIGGER_LOOP_CLR_ENG_EVENT 138
#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_TARGET_LINE1_ENG_EVENT 139
#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_INT_TG_TARGET_LINE0_ENG_EVENT 140
#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_EXT_TG_VSYNC_START_ENG_EVENT 141
#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_EXT_TG_VSYNC_END_ENG_EVENT 142
#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_EXT_TG_VDE_START_ENG_EVENT 143
#define CMDQ_EVENT_DISP1_DISP_DVO0_DVO_EXT_TG_VDE_END_ENG_EVENT 144
/* CMDQ_EVENT_DISP1_DISP_DSI2_ENG_EVENT0 ~ 10: 145 ~ 155 */
#define CMDQ_EVENT_DISP1_DISP_DSI2_ENG_EVENT(n) (145 + (n))
/* CMDQ_EVENT_DISP1_DISP_DSI1_ENG_EVENT0 ~ 21: 156 ~ 177 */
#define CMDQ_EVENT_DISP1_DISP_DSI1_ENG_EVENT(n) (156 + (n))
/* CMDQ_EVENT_DISP1_DISP_DSI0_ENG_EVENT0 ~ 10: 178 ~ 188 */
#define CMDQ_EVENT_DISP1_DISP_DSI0_ENG_EVENT(n) (178 + (n))
#define CMDQ_EVENT_DISP1_DISP_DP_INTF1_VSYNC_START_ENG_EVENT 189
#define CMDQ_EVENT_DISP1_DISP_DP_INTF1_VSYNC_END_ENG_EVENT 190
#define CMDQ_EVENT_DISP1_DISP_DP_INTF1_VDE_START_ENG_EVENT 191
#define CMDQ_EVENT_DISP1_DISP_DP_INTF1_VDE_END_ENG_EVENT 192
#define CMDQ_EVENT_DISP1_DISP_DP_INTF1_TARGET_LINE_ENG_EVENT 193
#define CMDQ_EVENT_DISP1_DISP_DP_INTF0_VSYNC_START_ENG_EVENT 194
#define CMDQ_EVENT_DISP1_DISP_DP_INTF0_VSYNC_END_ENG_EVENT 195
#define CMDQ_EVENT_DISP1_DISP_DP_INTF0_VDE_START_ENG_EVENT 196
#define CMDQ_EVENT_DISP1_DISP_DP_INTF0_VDE_END_ENG_EVENT 197
#define CMDQ_EVENT_DISP1_DISP_DP_INTF0_TARGET_LINE_ENG_EVENT 198
/* CMDQ_EVENT_DISP1_BUF_UNDERRUN_ENG_EVENT0 ~ 10: 199 ~ 209 */
#define CMDQ_EVENT_DISP1_BUF_UNDERRUN_ENG_EVENT(n) (199 + (n))
/* CMDQ_EVENT_MML0_STREAM_SOF0 ~ 15: 210 ~ 225 */
#define CMDQ_EVENT_MML0_STREAM_SOF(n) (210 + (n))
/* CMDQ_EVENT_MML0_FRAME_DONE_SEL0 ~ 15: 226 ~ 241 */
#define CMDQ_EVENT_MML0_FRAME_DONE_SEL(n) (226 + (n))
/* CMDQ_EVENT_MML0_REG_UPDATE_DONE_ENG_EVENT0 ~ 15: 242 ~ 257 */
#define CMDQ_EVENT_MML0_REG_UPDATE_DONE_ENG_EVENT(n) (242 + (n))
#define CMDQ_EVENT_MML0_MDP_WROT2_SW_RST_DONE_ENG_EVENT 258
#define CMDQ_EVENT_MML0_MDP_WROT1_SW_RST_DONE_ENG_EVENT 259
#define CMDQ_EVENT_MML0_MDP_WROT0_SW_RST_DONE_ENG_EVENT 260
#define CMDQ_EVENT_MML0_MDP_RROT0_SW_RST_DONE_ENG_EVENT 261
#define CMDQ_EVENT_MML0_MDP_RDMA2_SW_RST_DONE_ENG_EVENT 262
#define CMDQ_EVENT_MML0_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 263
#define CMDQ_EVENT_MML0_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 264
#define CMDQ_EVENT_MML0_MDP_MERGE0_SW_RST_DONE_ENG_EVENT 265
#define CMDQ_EVENT_MML0_DISP_MUTEX0_TIMEOUT_ENG_EVENT 266
#define CMDQ_EVENT_MML0_DISP_MUTEX0_GET_RLZ_ENG_EVENT 267
/* CMDQ_EVENT_MML1_STREAM_SOF0 ~ 15: 268 ~ 283 */
#define CMDQ_EVENT_MML1_STREAM_SOF(n) (268 + (n))
/* CMDQ_EVENT_MML1_FRAME_DONE_SEL0 ~ 15: 284 ~ 299 */
#define CMDQ_EVENT_MML1_FRAME_DONE_SEL(n) (284 + (n))
/* CMDQ_EVENT_MML1_REG_UPDATE_DONE_ENG_EVENT0 ~ 15: 300 ~ 315 */
#define CMDQ_EVENT_MML1_REG_UPDATE_DONE_ENG_EVENT(n) (300 + (n))
#define CMDQ_EVENT_MML1_MDP_WROT2_SW_RST_DONE_ENG_EVENT 316
#define CMDQ_EVENT_MML1_MDP_WROT1_SW_RST_DONE_ENG_EVENT 317
#define CMDQ_EVENT_MML1_MDP_WROT0_SW_RST_DONE_ENG_EVENT 318
#define CMDQ_EVENT_MML1_MDP_RROT0_SW_RST_DONE_ENG_EVENT 319
#define CMDQ_EVENT_MML1_MDP_RDMA2_SW_RST_DONE_ENG_EVENT 320
#define CMDQ_EVENT_MML1_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 321
#define CMDQ_EVENT_MML1_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 322
#define CMDQ_EVENT_MML1_MDP_MERGE0_SW_RST_DONE_ENG_EVENT 323
#define CMDQ_EVENT_MML1_DISP_MUTEX0_TIMEOUT_ENG_EVENT 324
#define CMDQ_EVENT_MML1_DISP_MUTEX0_GET_RLZ_ENG_EVENT 325
/* CMDQ_EVENT_OVL0_STREAM_SOF0 ~ 15: 326 ~ 341 */
#define CMDQ_EVENT_OVL0_STREAM_SOF(n) (326 + (n))
/* CMDQ_EVENT_OVL0_FRAME_DONE_SEL0 ~ 15: 342 ~ 357 */
#define CMDQ_EVENT_OVL0_FRAME_DONE_SEL(n) (342 + (n))
#define CMDQ_EVENT_OVL0_OVL_UFBC_WDMA0_TARGET_LINE_END_ENG_EVENT 358
#define CMDQ_EVENT_OVL0_OVL_MUTEX0_TIMEOUT_ENG_EVENT 359
/* CMDQ_EVENT_OVL0_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT0 ~ 15: 360 ~ 375 */
#define CMDQ_EVENT_OVL0_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT(n) (360 + (n))
#define CMDQ_EVENT_OVL0_OVL_MUTEX0_GET_RELEASE_ENG_EVENT 376
#define CMDQ_EVENT_OVL0_OVL_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 377
#define CMDQ_EVENT_OVL0_OVL_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 378
#define CMDQ_EVENT_OVL0_OVL_EXDMA9_FRAME_RESET_DONE_ENG_EVENT 379
#define CMDQ_EVENT_OVL0_OVL_EXDMA8_FRAME_RESET_DONE_ENG_EVENT 380
#define CMDQ_EVENT_OVL0_OVL_EXDMA7_FRAME_RESET_DONE_ENG_EVENT 381
#define CMDQ_EVENT_OVL0_OVL_EXDMA6_FRAME_RESET_DONE_ENG_EVENT 382
#define CMDQ_EVENT_OVL0_OVL_EXDMA5_FRAME_RESET_DONE_ENG_EVENT 383
#define CMDQ_EVENT_OVL0_OVL_EXDMA4_FRAME_RESET_DONE_ENG_EVENT 384
#define CMDQ_EVENT_OVL0_OVL_EXDMA3_FRAME_RESET_DONE_ENG_EVENT 385
#define CMDQ_EVENT_OVL0_OVL_EXDMA2_FRAME_RESET_DONE_ENG_EVENT 386
#define CMDQ_EVENT_OVL0_OVL_EXDMA1_FRAME_RESET_DONE_ENG_EVENT 387
#define CMDQ_EVENT_OVL0_OVL_EXDMA0_FRAME_RESET_DONE_ENG_EVENT 388
#define CMDQ_EVENT_OVL0_OVL_DISP_WDMA1_TARGET_LINE_END_ENG_EVENT 389
#define CMDQ_EVENT_OVL0_OVL_DISP_WDMA1_SW_RST_DONE_END_ENG_EVENT 390
#define CMDQ_EVENT_OVL0_OVL_DISP_WDMA0_TARGET_LINE_END_ENG_EVENT 391
#define CMDQ_EVENT_OVL0_OVL_DISP_WDMA0_SW_RST_DONE_END_ENG_EVENT 392
#define CMDQ_EVENT_OVL0_OVL_BWM0_FRAME_RESET_DONE_ENG_EVENT 393
/* CMDQ_EVENT_OVL1_STREAM_SOF0 ~ 15: 394 ~ 409 */
#define CMDQ_EVENT_OVL1_STREAM_SOF(n) (394 + (n))
/* CMDQ_EVENT_OVL1_FRAME_DONE_SEL0 ~ 15: 410 ~ 425 */
#define CMDQ_EVENT_OVL1_FRAME_DONE_SEL(n) (410 + (n))
#define CMDQ_EVENT_OVL1_OVL_UFBC_WDMA0_TARGET_LINE_END_ENG_EVENT 426
#define CMDQ_EVENT_OVL1_OVL_MUTEX0_TIMEOUT_ENG_EVENT 427
/* CMDQ_EVENT_OVL1_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT0 ~ 15: 428 ~ 443 */
#define CMDQ_EVENT_OVL1_OVL_MUTEX0_REG_UPDATE_DONE_ENG_EVENT(n) (428 + (n))
#define CMDQ_EVENT_OVL1_OVL_MUTEX0_GET_RELEASE_ENG_EVENT 444
#define CMDQ_EVENT_OVL1_OVL_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 445
#define CMDQ_EVENT_OVL1_OVL_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 446
#define CMDQ_EVENT_OVL1_OVL_EXDMA9_FRAME_RESET_DONE_ENG_EVENT 447
#define CMDQ_EVENT_OVL1_OVL_EXDMA8_FRAME_RESET_DONE_ENG_EVENT 448
#define CMDQ_EVENT_OVL1_OVL_EXDMA7_FRAME_RESET_DONE_ENG_EVENT 449
#define CMDQ_EVENT_OVL1_OVL_EXDMA6_FRAME_RESET_DONE_ENG_EVENT 450
#define CMDQ_EVENT_OVL1_OVL_EXDMA5_FRAME_RESET_DONE_ENG_EVENT 451
#define CMDQ_EVENT_OVL1_OVL_EXDMA4_FRAME_RESET_DONE_ENG_EVENT 452
#define CMDQ_EVENT_OVL1_OVL_EXDMA3_FRAME_RESET_DONE_ENG_EVENT 453
#define CMDQ_EVENT_OVL1_OVL_EXDMA2_FRAME_RESET_DONE_ENG_EVENT 454
#define CMDQ_EVENT_OVL1_OVL_EXDMA1_FRAME_RESET_DONE_ENG_EVENT 455
#define CMDQ_EVENT_OVL1_OVL_EXDMA0_FRAME_RESET_DONE_ENG_EVENT 456
#define CMDQ_EVENT_OVL1_OVL_DISP_WDMA1_TARGET_LINE_END_ENG_EVENT 457
#define CMDQ_EVENT_OVL1_OVL_DISP_WDMA1_SW_RST_DONE_END_ENG_EVENT 458
#define CMDQ_EVENT_OVL1_OVL_DISP_WDMA0_TARGET_LINE_END_ENG_EVENT 459
#define CMDQ_EVENT_OVL1_OVL_DISP_WDMA0_SW_RST_DONE_END_ENG_EVENT 460
#define CMDQ_EVENT_OVL1_OVL_BWM0_FRAME_RESET_DONE_ENG_EVENT 461
#define CMDQ_EVENT_DPC_DT_DONE0 462
#define CMDQ_EVENT_DPC_DT_DONE1 463
#define CMDQ_EVENT_DPC_DT_DONE2_0_MERGE 464
#define CMDQ_EVENT_DPC_DT_DONE2_1_MERGE 465
#define CMDQ_EVENT_DPC_DT_DONE2_2_MERGE 466
#define CMDQ_EVENT_DPC_DT_DONE2_3_MERGE 467
#define CMDQ_EVENT_DPC_DT_DONE3 468
#define CMDQ_EVENT_DPC_DT_DONE4_MERGE 469
#define CMDQ_EVENT_DPC_DT_DONE5 470
#define CMDQ_EVENT_DPC_DT_DONE6_0_MERGE 471
#define CMDQ_EVENT_DPC_DT_DONE6_1_MERGE 472
#define CMDQ_EVENT_DPC_DT_DONE6_2_MERGE 473
#define CMDQ_EVENT_DPC_DT_DONE6_3_MERGE 474
#define CMDQ_EVENT_DPC_DT_DONE7 475
#define CMDQ_EVENT_DPC_DT_DONE32_MERGE 476
#define CMDQ_EVENT_DPC_DT_DONE33 477
#define CMDQ_EVENT_DPC_DT_DONE34_0 478
#define CMDQ_EVENT_DPC_DT_DONE35 479
#define CMDQ_EVENT_DPC_DISP_SSYS_DT_ERR_ON_BEFORE_OFF 480
#define CMDQ_EVENT_DPC_DISP_SSYS_DT_ERR_PRETE_BEFORE_ON 481
#define CMDQ_EVENT_DPC_DISP_DVFS_DT_ERR_ON_BEFORE_OFF 482
#define CMDQ_EVENT_DPC_DISP_DVFS_DT_ERR_PRETE_BEFORE_ON 483
#define CMDQ_EVENT_DPC_DISP_SB_DT_ERR_ON_BEFORE_OFF 484
#define CMDQ_EVENT_DPC_DISP_SB_DT_ERR_PRETE_BEFORE_ON 485
#define CMDQ_EVENT_DPC_DISP_SW_CONFIG_WHEN_MTCMOS_OFF 486
#define CMDQ_EVENT_DPC_MML_SSYS_DT_ERR_ON_BEFORE_OFF 487
#define CMDQ_EVENT_DPC_MML_SSYS_DT_ERR_PRETE_BEFORE_ON 488
#define CMDQ_EVENT_DPC_MML_DVFS_DT_ERR_ON_BEFORE_OFF 489
#define CMDQ_EVENT_DPC_MML_DVFS_DT_ERR_PRETE_BEFORE_ON 490
#define CMDQ_EVENT_DPC_MML_SB_DT_ERR_ON_BEFORE_OFF 491
#define CMDQ_EVENT_DPC_MML_SB_DT_ERR_PRETE_BEFORE_ON 492
#define CMDQ_EVENT_DPC_MML_SW_CONFIG_WHEN_MTCMOS_OFF 493
/* CMDQ_EVENT_DPTX_DPTX_EVENT0 ~ 3: 494 ~ 497 */
#define CMDQ_EVENT_DPTX_DPTX_EVENT(n) (494 + (n))
/* CMDQ_EVENT_EDPTX_EDPTX_EVENT0 ~ 1: 498 ~ 499 */
#define CMDQ_EVENT_EDPTX_EDPTX_EVENT(n) (498 + (n))
#define CMDQ_EVENT_DSI0_TE_I_DSI0_TE_I 898
#define CMDQ_EVENT_DSI1_TE_I_DSI1_TE_I 899
#define CMDQ_EVENT_DSI2_TE_I_DSI2_TE_I 900
/* CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK0 ~ 23: 901 ~ 924 */
#define CMDQ_EVENT_POWEREVENT_GCE_EVENT_SUBSYS_PWR_ACK(n) (901 + (n))
/* CMDQ_EVENT_GCE_EVENT_DPTX_GCE_EVENT_DPTX0 ~ 1: 925 ~ 926 */
#define CMDQ_EVENT_GCE_EVENT_DPTX_GCE_EVENT_DPTX(n) (925 + (n))
/* CMDQ_EVENT_GCE_EVENT_DPTX_P1_GCE_EVENT_DPTX_P10 ~ 1: 927 ~ 928 */
#define CMDQ_EVENT_GCE_EVENT_DPTX_P1_GCE_EVENT_DPTX_P1(n) (927 + (n))
/* CMDQ_EVENT_GCE_EVENT_EDPTX_GCE_EVENT_EDPTX0 ~ 1: 929 ~ 930 */
#define CMDQ_EVENT_GCE_EVENT_EDPTX_GCE_EVENT_EDPTX(n) (929 + (n))
#define CMDQ_EVENT_DSI3_TE_I_DSI3_TE_I 931
#define CMDQ_EVENT_SPI0_FINISH_EVENT_DSI4_TE_I 932
#define CMDQ_EVENT_SPI0_EVENT_EVENT_DSI5_TE_I 933
/*
* GCE1 Hardware Event IDs
* Different SoCs will have varying numbers of hardware event signals,
* which are sent from the corresponding hardware to the GCE.
* Each hardware event signal corresponds to an event ID in the GCE.
* The CMDQ driver can use the following event ID definitions to allow
* the client driver to use wait and clear APIs provided by CMDQ, enabling
* the GCE to execute operations in the instructions for that event ID.
*
* The event IDs of GCE1 are mainly used by non-display hardware.
*/
#define CMDQ_EVENT_VENC3_VENC_RESERVED 0
#define CMDQ_EVENT_VENC3_VENC_FRAME_DONE 1
#define CMDQ_EVENT_VENC3_VENC_PAUSE_DONE 2
#define CMDQ_EVENT_VENC3_JPGENC_DONE 3
#define CMDQ_EVENT_VENC3_VENC_MB_DONE 4
#define CMDQ_EVENT_VENC3_VENC_128BYTE_DONE 5
#define CMDQ_EVENT_VENC3_JPGDEC_DONE 6
#define CMDQ_EVENT_VENC3_JPGDEC_C1_DONE 7
#define CMDQ_EVENT_VENC3_JPGDEC_INSUFF_DONE 8
#define CMDQ_EVENT_VENC3_JPGDEC_C1_INSUFF_DONE 9
#define CMDQ_EVENT_VENC3_WP_2ND_STAGE_DONE 10
#define CMDQ_EVENT_VENC3_WP_3RD_STAGE_DONE 11
#define CMDQ_EVENT_VENC3_PPS_HEADER_DONE 12
#define CMDQ_EVENT_VENC3_SPS_HEADER_DONE 13
#define CMDQ_EVENT_VENC3_VPS_HEADER_DONE 14
#define CMDQ_EVENT_VENC3_VENC_SLICE_DONE 15
#define CMDQ_EVENT_VENC3_VENC_SOC_SLICE_DONE 16
#define CMDQ_EVENT_VENC3_VENC_SOC_FRAME_DONE 17
#define CMDQ_EVENT_VENC2_VENC_FRAME_DONE 33
#define CMDQ_EVENT_VENC2_VENC_PAUSE_DONE 34
#define CMDQ_EVENT_VENC2_JPGENC_DONE 35
#define CMDQ_EVENT_VENC2_VENC_MB_DONE 36
#define CMDQ_EVENT_VENC2_VENC_128BYTE_DONE 37
#define CMDQ_EVENT_VENC2_JPGDEC_DONE 38
#define CMDQ_EVENT_VENC2_JPGDEC_C1_DONE 39
#define CMDQ_EVENT_VENC2_JPGDEC_INSUFF_DONE 40
#define CMDQ_EVENT_VENC2_JPGDEC_C1_INSUFF_DONE 41
#define CMDQ_EVENT_VENC2_WP_2ND_STAGE_DONE 42
#define CMDQ_EVENT_VENC2_WP_3RD_STAGE_DONE 43
#define CMDQ_EVENT_VENC2_PPS_HEADER_DONE 44
#define CMDQ_EVENT_VENC2_SPS_HEADER_DONE 45
#define CMDQ_EVENT_VENC2_VPS_HEADER_DONE 46
#define CMDQ_EVENT_VENC2_VENC_SLICE_DONE 47
#define CMDQ_EVENT_VENC2_VENC_SOC_SLICE_DONE 48
#define CMDQ_EVENT_VENC2_VENC_SOC_FRAME_DONE 49
#define CMDQ_EVENT_VENC1_VENC_FRAME_DONE 65
#define CMDQ_EVENT_VENC1_VENC_PAUSE_DONE 66
#define CMDQ_EVENT_VENC1_JPGENC_DONE 67
#define CMDQ_EVENT_VENC1_VENC_MB_DONE 68
#define CMDQ_EVENT_VENC1_VENC_128BYTE_DONE 69
#define CMDQ_EVENT_VENC1_JPGDEC_DONE 70
#define CMDQ_EVENT_VENC1_JPGDEC_C1_DONE 71
#define CMDQ_EVENT_VENC1_JPGDEC_INSUFF_DONE 72
#define CMDQ_EVENT_VENC1_JPGDEC_C1_INSUFF_DONE 73
#define CMDQ_EVENT_VENC1_WP_2ND_STAGE_DONE 74
#define CMDQ_EVENT_VENC1_WP_3RD_STAGE_DONE 75
#define CMDQ_EVENT_VENC1_PPS_HEADER_DONE 76
#define CMDQ_EVENT_VENC1_SPS_HEADER_DONE 77
#define CMDQ_EVENT_VENC1_VPS_HEADER_DONE 78
#define CMDQ_EVENT_VENC1_VENC_SLICE_DONE 79
#define CMDQ_EVENT_VENC1_VENC_SOC_SLICE_DONE 80
#define CMDQ_EVENT_VENC1_VENC_SOC_FRAME_DONE 81
#define CMDQ_EVENT_VDEC1_VDEC_LINE_CNT_INT 192
#define CMDQ_EVENT_VDEC1_VDEC_INT 193
#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_2 194
#define CMDQ_EVENT_VDEC1_VDEC_DEC_ERR 195
#define CMDQ_EVENT_VDEC1_VDEC_BUSY_OVERFLOW 196
#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_5 197
#define CMDQ_EVENT_VDEC1_VDEC_INI_FETCH_RDY 198
#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_7 199
#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_8 200
#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_9 201
#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_10 202
#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_11 203
#define CMDQ_EVENT_VDEC1_VDEC_GCE_CNT_OP_THR 207
#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_32 224
#define CMDQ_EVENT_VDEC1_VDEC_LAT_INT 225
#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_34 226
#define CMDQ_EVENT_VDEC1_VDEC_LAT_DEC_ERR 227
#define CMDQ_EVENT_VDEC1_VDEC_LAT_BUSY_OVERFLOW 228
#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_37 229
#define CMDQ_EVENT_VDEC1_VDEC_LAT_INI_FETCH_RDY 230
#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_39 231
#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_40 232
#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_41 233
#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_42 234
#define CMDQ_EVENT_VDEC1_VDEC1_EVENT_43 235
#define CMDQ_EVENT_VDEC1_VDEC_LAT_GCE_CNT_OP_THR 239
#define CMDQ_EVENT_IMG_IMG_EVENT_0 256
/* CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_0 ~ 5: 257 ~ 262 */
#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0(n) (257 + (n))
#define CMDQ_EVENT_IMG_TRAW0_DMA_ERR_EVENT 263
#define CMDQ_EVENT_IMG_TRAW0_DUMMY_0 264
/* CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_0 ~ 5: 265 ~ 270 */
#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0(n) (265 + (n))
#define CMDQ_EVENT_IMG_TRAW1_DMA_ERR_EVENT 271
#define CMDQ_EVENT_IMG_ADL_TILE_DONE_EVENT 272
#define CMDQ_EVENT_IMG_ADLWR0_TILE_DONE_EVENT 273
#define CMDQ_EVENT_IMG_ADLWR1_TILE_DONE_EVENT 274
#define CMDQ_EVENT_IMG_IMGSYS_IPE_ME_DONE 275
#define CMDQ_EVENT_IMG_IMGSYS_IPE_MMG_DONE 276
/* CMDQ_EVENT_IMG_QOF_ACK_EVENT0 ~ 19: 277 ~ 296 */
#define CMDQ_EVENT_IMG_QOF_ACK_EVENT(n) (277 + (n))
/* CMDQ_EVENT_IMG_QOF_ON_EVENT0 ~ 4: 297 ~ 301 */
#define CMDQ_EVENT_IMG_QOF_ON_EVENT(n) (297 + (n))
/* CMDQ_EVENT_IMG_QOF_OFF_EVENT0 ~ 4: 302 ~ 306 */
#define CMDQ_EVENT_IMG_QOF_OFF_EVENT(n) (302 + (n))
/* CMDQ_EVENT_IMG_QOF_SAVE_EVENT0 ~ 4: 307 ~ 311 */
#define CMDQ_EVENT_IMG_QOF_SAVE_EVENT(n) (307 + (n))
/* CMDQ_EVENT_IMG_QOF_RESTORE_EVENT0 ~ 4: 312 ~ 316 */
#define CMDQ_EVENT_IMG_QOF_RESTORE_EVENT(n) (312 + (n))
/* CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P20~5: 317 ~ 322 */
#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2(n) (317 + (n))
#define CMDQ_EVENT_IMG_DIP_DMA_ERR_EVENT 323
#define CMDQ_EVENT_IMG_DIP_NR_DMA_ERR_EVENT 324
#define CMDQ_EVENT_IMG_DIP_DUMMY_0 325
#define CMDQ_EVENT_IMG_WPE_EIS_GCE_FRAME_DONE 326
#define CMDQ_EVENT_IMG_WPE_EIS_DONE_SYNC_OUT 327
/* CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P20 ~ 5: 328 ~ 333 */
#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_P2(n) (328 + (n))
/* CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P20 ~ 5: 334 ~ 339 */
#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2(n) (334 + (n))
#define CMDQ_EVENT_IMG_PQA_DMA_ERR_EVENT 340
/* CMDQ_EVENT_IMG_WPE0_DUMMY0~2: 341 ~ 343 */
#define CMDQ_EVENT_IMG_WPE0_DUMMY(n) (341 + (n))
#define CMDQ_EVENT_IMG_OMC_TNR_GCE_FRAME_DONE 344
#define CMDQ_EVENT_IMG_OMC_TNR_DONE_SYNC_OUT 345
/* CMDQ_EVENT_IMG_OMC_TNR_CQ_THR_DONE_P20 ~ 5: 346 ~ 351 */
#define CMDQ_EVENT_IMG_OMC_TNR_CQ_THR_DONE_P2(n) (346 + (n))
/* CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P20 ~ 5: 352 ~ 357 */
#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2(n) (352 + (n))
#define CMDQ_EVENT_IMG_PQB_DMA_ERR_EVENT 358
/* CMDQ_EVENT_IMG_WPE1_DUMMY0 ~ 2: 359 ~ 361 */
#define CMDQ_EVENT_IMG_WPE1_DUMMY(n) (359 + (n))
#define CMDQ_EVENT_IMG_WPE_LITE_GCE_FRAME_DONE 362
#define CMDQ_EVENT_IMG_WPE_LITE_DONE_SYNC_OUT 363
/* CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P20 ~ 5: 364 ~ 369 */
#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_P2(n) (364 + (n))
#define CMDQ_EVENT_IMG_OMC_LITE_GCE_FRAME_DONE 370
#define CMDQ_EVENT_IMG_OMC_LITE_DONE_SYNC_OUT 371
/* CMDQ_EVENT_IMG_OMC_LITE_CQ_THR_DONE_P20 ~ 5: 372 ~ 377 */
#define CMDQ_EVENT_IMG_OMC_LITE_CQ_THR_DONE_P2(n) (372 + (n))
/* CMDQ_EVENT_IMG_WPE2_DUMMY0 ~ 2: 378 ~ 380 */
#define CMDQ_EVENT_IMG_WPE2_DUMMY(n) (378 + (n))
#define CMDQ_EVENT_IMG_IMGSYS_IPE_FDVT0_DONE 381
#define CMDQ_EVENT_IMG_IMG_EVENT_126 382
#define CMDQ_EVENT_IMG_IMG_EVENT_127 383
#define CMDQ_EVENT_CAM_CAM_EVENT_0 384
#define CMDQ_EVENT_CAM_CAM_SUBA_SW_PASS1_DONE 385
#define CMDQ_EVENT_CAM_CAM_SUBB_SW_PASS1_DONE 386
#define CMDQ_EVENT_CAM_CAM_SUBC_SW_PASS1_DONE 387
#define CMDQ_EVENT_CAM_CAM_SUBA_TFMR_PASS1_DONE 388
#define CMDQ_EVENT_CAM_CAM_SUBB_TFMR_PASS1_DONE 389
#define CMDQ_EVENT_CAM_CAM_SUBC_TFMR_PASS1_DONE 390
/* CMDQ_EVENT_CAM_CAMSV_A_SW_PASS1_DONE0 ~ 3: 391 ~ 394 */
#define CMDQ_EVENT_CAM_CAMSV_A_SW_PASS1_DONE(n) (391 + (n))
/* CMDQ_EVENT_CAM_CAMSV_B_SW_PASS1_DONE0 ~ 3: 395 ~ 398 */
#define CMDQ_EVENT_CAM_CAMSV_B_SW_PASS1_DONE(n) (395 + (n))
/* CMDQ_EVENT_CAM_CAMSV_C_SW_PASS1_DONE0 ~ 3: 399 + 402 */
#define CMDQ_EVENT_CAM_CAMSV_C_SW_PASS1_DONE(n) (399 + (n))
/* CMDQ_EVENT_CAM_CAMSV_D_SW_PASS1_DONE0 ~ 3: 403 ~ 406 */
#define CMDQ_EVENT_CAM_CAMSV_D_SW_PASS1_DONE(n) (403 + (n))
/* CMDQ_EVENT_CAM_CAMSV_E_SW_PASS1_DONE0 ~ 3: 407 ~ 409 */
#define CMDQ_EVENT_CAM_CAMSV_E_SW_PASS1_DONE(n) (407 + (n))
/* CMDQ_EVENT_CAM_CAMSV_F_SW_PASS1_DONE0 ~ 3: 411 ~ 413 */
#define CMDQ_EVENT_CAM_CAMSV_F_SW_PASS1_DONE(n) (411 + (n))
#define CMDQ_EVENT_CAM_MRAW0_SW_PASS1_DONE 415
#define CMDQ_EVENT_CAM_MRAW1_SW_PASS1_DONE 416
#define CMDQ_EVENT_CAM_MRAW2_SW_PASS1_DONE 417
#define CMDQ_EVENT_CAM_MRAW3_SW_PASS1_DONE 418
#define CMDQ_EVENT_CAM_UISP_SW_PASS1_DONE 419
#define CMDQ_EVENT_CAM_TG_MRAW0_OUT_SOF 420
#define CMDQ_EVENT_CAM_TG_MRAW1_OUT_SOF 421
#define CMDQ_EVENT_CAM_TG_MRAW2_OUT_SOF 422
#define CMDQ_EVENT_CAM_TG_MRAW3_OUT_SOF 423
#define CMDQ_EVENT_CAM_PDA0_IRQO_EVENT_DONE_D1 424
#define CMDQ_EVENT_CAM_PDA1_IRQO_EVENT_DONE_D1 425
#define CMDQ_EVENT_CAM_DPE_DVP_CMQ_EVENT 426
#define CMDQ_EVENT_CAM_DPE_DVS_CMQ_EVENT 427
#define CMDQ_EVENT_CAM_DPE_DVFG_CMQ_EVENT 428
#define CMDQ_EVENT_CAM_CAM_EVENT_45 429
#define CMDQ_EVENT_CAM_CAM_EVENT_46 430
#define CMDQ_EVENT_CAM_CAM_EVENT_47 431
#define CMDQ_EVENT_CAM_CAM_EVENT_48 432
/* CMDQ_EVENT_CAM_CAM_SUBA_TG_INT1 ~ 4: 433 ~ 436 */
#define CMDQ_EVENT_CAM_CAM_SUBA_TG_INT(n) (433 + (n) - 1)
/* CMDQ_EVENT_CAM_CAM_SUBB_TG_INT1 ~ 4: 437 ~ 440 */
#define CMDQ_EVENT_CAM_CAM_SUBB_TG_INT(n) (437 + (n) - 1)
/* CMDQ_EVENT_CAM_CAM_SUBC_TG_INT1 ~ 4: 441 ~ 444 */
#define CMDQ_EVENT_CAM_CAM_SUBC_TG_INT(n) (441 + (n) - 1)
#define CMDQ_EVENT_CAM_RAW_O_SOF_SUBA 445
#define CMDQ_EVENT_CAM_RAW_O_SOF_SUBB 446
#define CMDQ_EVENT_CAM_RAW_O_SOF_SUBC 447
#define CMDQ_EVENT_CAM_TFMR_RAW_O_SOF_SUBA 448
#define CMDQ_EVENT_CAM_TFMR_RAW_O_SOF_SUBB 449
#define CMDQ_EVENT_CAM_TFMR_RAW_O_SOF_SUBC 450
#define CMDQ_EVENT_CAM_RAW_SEL_SOF_UISP 451
#define CMDQ_EVENT_CAM_CAM_SUBA_RING_BUFFER_OVERFLOW_INT_IN 452
#define CMDQ_EVENT_CAM_CAM_SUBB_RING_BUFFER_OVERFLOW_INT_IN 453
#define CMDQ_EVENT_CAM_CAM_SUBC_RING_BUFFER_OVERFLOW_INT_IN 454
#define CMDQ_EVENT_CAM_CAM_EVENT_71 455
#define CMDQ_EVENT_CAM_ADL_WR_FRAME_DONE 456
#define CMDQ_EVENT_CAM_ADL_RD_FRAME_DONE 457
#define CMDQ_EVENT_CAM_QOF_RAWA_POWER_ON_EVENT 458
#define CMDQ_EVENT_CAM_QOF_RAWB_POWER_ON_EVENT 459
#define CMDQ_EVENT_CAM_QOF_RAWC_POWER_ON_EVENT 460
#define CMDQ_EVENT_CAM_QOF_RAWA_POWER_OFF_EVENT 461
#define CMDQ_EVENT_CAM_QOF_RAWB_POWER_OFF_EVENT 462
#define CMDQ_EVENT_CAM_QOF_RAWC_POWER_OFF_EVENT 463
#define CMDQ_EVENT_CAM_QOF_RAWA_SAVE_EVENT 464
#define CMDQ_EVENT_CAM_QOF_RAWB_SAVE_EVENT 465
#define CMDQ_EVENT_CAM_QOF_RAWC_SAVE_EVENT 466
#define CMDQ_EVENT_CAM_QOF_RAWA_RESTORE_EVENT 467
#define CMDQ_EVENT_CAM_QOF_RAWB_RESTORE_EVENT 468
#define CMDQ_EVENT_CAM_QOF_RAWC_RESTORE_EVENT 469
/* CMDQ_EVENT_CAM_QOF_CAM_EVENT0 ~ 11: 470 ~ 481 */
#define CMDQ_EVENT_CAM_QOF_CAM_EVENT(n) (470 + (n))
/* CMDQ_EVENT_CAM_SENINF_CFG_DONE_EVENT0 ~ 11: 482 ~ 495 */
#define CMDQ_EVENT_CAM_SENINF_CFG_DONE_EVENT(n) (482 + (n))
#define CMDQ_EVENT_CAM_CCU0_TO_GCE_NON_SEC_IRQ 496
#define CMDQ_EVENT_CAM_CCU0_TO_GCE_SEC_IRQ 497
#define CMDQ_EVENT_CAM_CCU0_TO_GCE_VM_IRQ 498
#define CMDQ_EVENT_CAM_CCU0_TO_GCE_EXCH_VM_IRQ 499
#define CMDQ_EVENT_CAM_CCU1_TO_GCE_NON_SEC_IRQ 500
#define CMDQ_EVENT_CAM_CCU1_TO_GCE_SEC_IRQ 501
#define CMDQ_EVENT_CAM_CCU1_TO_GCE_VM_IRQ 502
#define CMDQ_EVENT_CAM_CCU1_TO_GCE_EXCH_VM_IRQ 503
/* CMDQ_EVENT_CAM_I2C_CH2_EVENT0 ~ 4: 504 ~ 509 */
#define CMDQ_EVENT_CAM_I2C_CH2_EVENT(n) (504 + (n))
#define CMDQ_EVENT_CAM_CAM_EVENT_125 509
#define CMDQ_EVENT_CAM_CAM_EVENT_126 510
#define CMDQ_EVENT_CAM_CAM_EVENT_127 511
#define CMDQ_EVENT_SMI_EVENT_MMINFRA_SMI_MMSRAM_COMM_SMIASSER 898
#define CMDQ_EVENT_SMI_EVENT_MMINFRA_SMI_MDP_COMM_SMIASSER 899
#define CMDQ_EVENT_SMI_EVENT_MMINFRA_SMI_DISP_COMM_SMIASSER 900
/*
* GCE Software Tokens
* Apart from the event IDs that are already bound to hardware event signals,
* the remaining event IDs can be used as software tokens.
* This allows the client driver to name and operate them independently,
* and their usage is the same as that of hardware events.
*/
/* Begin of GCE0 software token */
/* Config thread notify trigger thread */
#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY 640
/* Trigger thread notify config thread */
#define CMDQ_SYNC_TOKEN_STREAM_EOF 641
/* Block Trigger thread until the ESD check finishes */
#define CMDQ_SYNC_TOKEN_ESD_EOF 642
#define CMDQ_SYNC_TOKEN_STREAM_BLOCK 643
/* Check CABC setup finish */
#define CMDQ_SYNC_TOKEN_CABC_EOF 644
/* VFP period token for Msync */
#define CMDQ_SYNC_TOKEN_VFP_PERIOD 645
/* Software sync token for dual display */
#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY_1 694
#define CMDQ_SYNC_TOKEN_STREAM_EOF_1 695
#define CMDQ_SYNC_TOKEN_ESD_EOF_1 696
#define CMDQ_SYNC_TOKEN_STREAM_BLOCK_1 697
#define CMDQ_SYNC_TOKEN_CABC_EOF_1 698
/*
* GPR access tokens (for HW register backup)
* There are 15 32-bit GPR, form 3 GPR as a set
* (64-bit for address, 32-bit for value)
*
* CMDQ_SYNC_TOKEN_GPR_SET0 ~ 4: 700 ~ 704
*/
#define CMDQ_SYNC_TOKEN_GPR_SET(n) (700 + (n))
#define CMDQ_SYNC_TOKEN_TE_0 705
#define CMDQ_SYNC_TOKEN_PREFETCH_TE_0 706
#define CMDQ_SYNC_TOKEN_VIDLE_POWER_ON 707
#define CMDQ_SYNC_TOKEN_CHECK_TRIGGER_MERGE 708
/* Resource lock event to control resource in GCE thread */
#define CMDQ_SYNC_RESOURCE_WROT0 710
#define CMDQ_SYNC_RESOURCE_WROT1 711
/* Hardware TRACE software token */
#define CMDQ_SYNC_TOKEN_HW_TRACE_WAIT 712
#define CMDQ_SYNC_TOKEN_HW_TRACE_LOCK 713
/* Software sync token for dual display */
#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY_3 714
#define CMDQ_SYNC_TOKEN_STREAM_EOF_3 715
#define CMDQ_SYNC_TOKEN_ESD_EOF_3 716
#define CMDQ_SYNC_TOKEN_STREAM_BLOCK_3 717
#define CMDQ_SYNC_TOKEN_CABC_EOF_3 718
/* End of GCE0 software token */
/* Begin of GCE1 software token */
/* CMDQ_SYNC_TOKEN_IMGSYS_POOL0 ~ 300: 512 ~ 812 */
#define CMDQ_SYNC_TOKEN_IMGSYS_POOL(n) (512 + (n))
/* ISP software token */
#define CMDQ_SYNC_TOKEN_IMGSYS_WPE_EIS 813
#define CMDQ_SYNC_TOKEN_IMGSYS_OMC_TNR 814
#define CMDQ_SYNC_TOKEN_IMGSYS_WPE_LITE 815
#define CMDQ_SYNC_TOKEN_IMGSYS_TRAW 816
#define CMDQ_SYNC_TOKEN_IMGSYS_LTRAW 817
#define CMDQ_SYNC_TOKEN_IMGSYS_XTRAW 818
#define CMDQ_SYNC_TOKEN_IMGSYS_DIP 819
#define CMDQ_SYNC_TOKEN_IMGSYS_PQDIP_A 820
#define CMDQ_SYNC_TOKEN_IMGSYS_PQDIP_B 821
#define CMDQ_SYNC_TOKEN_IPESYS_ME 822
#define CMDQ_SYNC_TOKEN_APUSYS_APU 823
#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_TRAW 824
#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_LTRAW 825
#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_XTRAW 826
#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_DIP 827
#define CMDQ_SYNC_TOKEN_IMGSYS_OMC_LITE 828
/* IMG software token for QoS */
#define CMDQ_SYNC_TOKEN_IMGSYS_QOS_LOCK 829
/* IMG software token for Qof */
#define CMDQ_SYNC_TOKEN_DIP_POWER_CTRL 830
#define CMDQ_SYNC_TOKEN_DIP_TRIG_PWR_ON 831
#define CMDQ_SYNC_TOKEN_DIP_PWR_ON 832
#define CMDQ_SYNC_TOKEN_DIP_TRIG_PWR_OFF 833
#define CMDQ_SYNC_TOKEN_DIP_PWR_OFF 834
#define CMDQ_SYNC_TOKEN_DIP_PWR_HAND_SHAKE 835
#define CMDQ_SYNC_TOKEN_TRAW_POWER_CTRL 836
#define CMDQ_SYNC_TOKEN_TRAW_TRIG_PWR_ON 837
#define CMDQ_SYNC_TOKEN_TRAW_PWR_ON 838
#define CMDQ_SYNC_TOKEN_TRAW_TRIG_PWR_OFF 839
#define CMDQ_SYNC_TOKEN_TRAW_PWR_OFF 840
#define CMDQ_SYNC_TOKEN_TRAW_PWR_HAND_SHAKE 841
/* End of GCE1 software token */
/* Begin of common software token */
/*
* Notify normal CMDQ there are some secure task done
* MUST NOT CHANGE, this token sync with secure world
*/
#define CMDQ_SYNC_SECURE_THR_EOF 940
/* CMDQ use software token */
#define CMDQ_SYNC_TOKEN_USER_0 941
#define CMDQ_SYNC_TOKEN_USER_1 942
#define CMDQ_SYNC_TOKEN_POLL_MONITOR 943
#define CMDQ_SYNC_TOKEN_TPR_LOCK 942
/* TZMP software token */
#define CMDQ_SYNC_TOKEN_TZMP_DISP_WAIT 943
#define CMDQ_SYNC_TOKEN_TZMP_DISP_SET 944
#define CMDQ_SYNC_TOKEN_TZMP_ISP_WAIT 945
#define CMDQ_SYNC_TOKEN_TZMP_ISP_SET 946
#define CMDQ_SYNC_TOKEN_TZMP_AIE_WAIT 947
#define CMDQ_SYNC_TOKEN_TZMP_AIE_SET 948
#define CMDQ_SYNC_TOKEN_TZMP_ADL_WAIT 949
#define CMDQ_SYNC_TOKEN_TZMP_ADL_SET 950
/* PREBUILT software token */
#define CMDQ_SYNC_TOKEN_PREBUILT_MDP_LOCK 951
#define CMDQ_SYNC_TOKEN_PREBUILT_MML_LOCK 952
#define CMDQ_SYNC_TOKEN_PREBUILT_VFMT_LOCK 953
#define CMDQ_SYNC_TOKEN_PREBUILT_DISP_LOCK 954
#define CMDQ_SYNC_TOKEN_DISP_VA_START 955
#define CMDQ_SYNC_TOKEN_DISP_VA_END 956
/*
* Event for GPR timer, used in sleep and poll with timeout
*
* CMDQ_TOKEN_GPR_TIMER_R0~15: 994 ~ 1009
*/
#define CMDQ_TOKEN_GPR_TIMER_R(n) (994 + (n))
/* End of common software token */
#endif

9
arch/arm64/boot/dts/mediatek/mt8365-evk.dts
View File

@@ -284,6 +284,11 @@
};
};
&gpu {
mali-supply = <&mt6357_vcore_reg>;
status = "okay";
};
&i2c0 {
clock-frequency = <100000>;
pinctrl-0 = <&i2c0_pins>;
@@ -353,6 +358,10 @@
};
};
&mfg {
domain-supply = <&mt6357_vsram_others_reg>;
};
&mmc0 {
assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;

43
arch/arm64/boot/dts/mediatek/mt8365.dtsi
View File

@@ -267,6 +267,26 @@
clock-output-names = "clk26m";
};
gpu_opp_table: opp-table-gpu {
compatible = "operating-points-v2";
opp-shared;
opp-450000000 {
opp-hz = /bits/ 64 <450000000>;
opp-microvolt = <650000>;
};
opp-560000000 {
opp-hz = /bits/ 64 <560000000>;
opp-microvolt = <700000>;
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <800000>;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -292,6 +312,27 @@
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
mfgcfg: syscon@13000000 {
compatible = "mediatek,mt8365-mfgcfg", "syscon";
reg = <0 0x13000000 0 0x1000>;
#clock-cells = <1>;
};
gpu: gpu@13040000 {
compatible = "mediatek,mt8365-mali", "arm,mali-bifrost";
reg = <0 0x13040000 0 0x4000>;
clocks = <&mfgcfg CLK_MFG_BG3D>;
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 201 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "job", "mmu", "gpu", "event";
operating-points-v2 = <&gpu_opp_table>;
power-domains = <&spm MT8365_POWER_DOMAIN_MFG>;
status = "disabled";
};
topckgen: syscon@10000000 {
compatible = "mediatek,mt8365-topckgen", "syscon";
reg = <0 0x10000000 0 0x1000>;
@@ -398,7 +439,7 @@
mediatek,infracfg = <&infracfg>;
};
power-domain@MT8365_POWER_DOMAIN_MFG {
mfg: power-domain@MT8365_POWER_DOMAIN_MFG {
reg = <MT8365_POWER_DOMAIN_MFG>;
clocks = <&topckgen CLK_TOP_MFG_SEL>;
clock-names = "mfg";

20
arch/arm64/boot/dts/mediatek/mt8370-grinn-genio-510-sbc.dts Normal file
View File

@@ -0,0 +1,20 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2025 Grinn sp. z o.o.
* Author: Bartosz Bilas <bartosz.bilas@grinn-global.com>
*/
/dts-v1/;
#include "mt8370.dtsi"
#include "mt8390-grinn-genio-som.dtsi"
#include "mt8390-grinn-genio-sbc.dtsi"
/ {
model = "Grinn GenioSBC-510";
compatible = "grinn,genio-510-sbc", "mediatek,mt8370", "mediatek,mt8188";
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 1 0x00000000>;
};
};

20
arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-700-sbc.dts Normal file
View File

@@ -0,0 +1,20 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2025 Grinn sp. z o.o.
* Author: Mateusz Koza <mateusz.koza@grinn-global.com>
*/
/dts-v1/;
#include "mt8188.dtsi"
#include "mt8390-grinn-genio-som.dtsi"
#include "mt8390-grinn-genio-sbc.dtsi"
/ {
model = "Grinn GenioSBC-700";
compatible = "grinn,genio-700-sbc", "mediatek,mt8390", "mediatek,mt8188";
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 1 0x00000000>;
};
};

538
arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-sbc.dtsi Normal file
View File

@@ -0,0 +1,538 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2025 Grinn sp. z o.o.
* Author: Mateusz Koza <mateusz.koza@grinn-global.com>
*/
#include <dt-bindings/gpio/gpio.h>
/ {
chassis-type = "embedded";
aliases {
ethernet0 = &eth;
i2c0 = &i2c0;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c5 = &i2c5;
i2c6 = &i2c6;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:921600n8";
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/*
* 12 MiB reserved for OP-TEE (BL32)
* +-----------------------+ 0x43e0_0000
* | SHMEM 2MiB |
* +-----------------------+ 0x43c0_0000
* | | TA_RAM 8MiB |
* + TZDRAM +--------------+ 0x4340_0000
* | | TEE_RAM 2MiB |
* +-----------------------+ 0x4320_0000
*/
optee_reserved: optee@43200000 {
no-map;
reg = <0 0x43200000 0 0x00c00000>;
};
scp_mem: memory@50000000 {
compatible = "shared-dma-pool";
reg = <0 0x50000000 0 0x2900000>;
no-map;
};
/* 2 MiB reserved for ARM Trusted Firmware (BL31) */
bl31_secmon_reserved: memory@54600000 {
no-map;
reg = <0 0x54600000 0x0 0x200000>;
};
apu_mem: memory@55000000 {
compatible = "shared-dma-pool";
reg = <0 0x55000000 0 0x1400000>; /* 20 MB */
};
vpu_mem: memory@57000000 {
compatible = "shared-dma-pool";
reg = <0 0x57000000 0 0x1400000>; /* 20 MB */
};
adsp_mem: memory@60000000 {
compatible = "shared-dma-pool";
reg = <0 0x60000000 0 0xf00000>;
no-map;
};
afe_dma_mem: memory@60f00000 {
compatible = "shared-dma-pool";
reg = <0 0x60f00000 0 0x100000>;
no-map;
};
adsp_dma_mem: memory@61000000 {
compatible = "shared-dma-pool";
reg = <0 0x61000000 0 0x100000>;
no-map;
};
};
reg_sbc_vsys: regulator-vsys {
compatible = "regulator-fixed";
regulator-name = "vsys";
regulator-always-on;
regulator-boot-on;
};
reg_fixed_5v: regulator-0 {
compatible = "regulator-fixed";
regulator-name = "fixed-5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
vin-supply = <&reg_sbc_vsys>;
};
reg_fixed_4v2: regulator-1 {
compatible = "regulator-fixed";
regulator-name = "fixed-4v2";
regulator-min-microvolt = <4200000>;
regulator-max-microvolt = <4200000>;
enable-active-high;
regulator-always-on;
vin-supply = <&reg_sbc_vsys>;
};
reg_fixed_3v3: regulator-2 {
compatible = "regulator-fixed";
regulator-name = "fixed-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
regulator-always-on;
vin-supply = <&reg_sbc_vsys>;
};
};
&pio {
gpio-line-names =
/* 0 - 4 */ "RPI_GPIO0", "RPI_GPIO1", "", "", "RPI_GPIO4",
/* 5 - 9 */ "", "RPI_GPIO6", "", "", "RPI_GPIO9",
/* 10 - 14 */ "RPI_GPIO10", "RPI_GPIO11", "", "", "",
/* 15 - 19 */ "", "", "", "", "",
/* 20 - 24 */ "", "RPI_GPIO21", "", "RPI_GPIO23", "",
/* 25 - 29 */ "", "", "", "", "",
/* 30 - 34 */ "RPI_GPIO30", "", "", "", "",
/* 35 - 39 */ "RPI_GPIO35", "RPI_GPIO36", "", "", "",
/* 40 - 44 */ "", "", "", "", "",
/* 45 - 49 */ "", "", "", "", "",
/* 50 - 54 */ "", "", "", "", "",
/* 55 - 59 */ "RPI_GPIO55", "RPI_GPIO56", "", "", "RPI_GPIO59",
/* 60 - 64 */ "RPI_GPIO60", "", "", "", "",
/* 65 - 69 */ "", "", "", "", "RPI_GPIO69",
/* 70 - 74 */ "", "", "RPI_GPIO72", "RPI_GPIO73", "RPI_GPIO74",
/* 75 - 79 */ "", "", "", "", "RPI_GPIO79",
/* 80 - 84 */ "RPI_GPIO80", "RPI_GPIO81", "RPI_GPIO82", "", "",
/* 85 - 89 */ "", "", "", "", "",
/* 90 - 94 */ "", "", "", "", "",
/* 95 - 99 */ "", "", "", "", "",
/*100 - 104 */ "", "", "", "", "",
/*105 - 109 */ "", "", "", "", "",
/*110 - 114 */ "", "", "", "", "",
/*115 - 119 */ "", "", "", "", "",
/*120 - 124 */ "", "RPI_GPIO121", "RPI_GPIO122", "RPI_GPIO123", "RPI_GPIO124";
i2c0_pins: i2c0-pins {
pins {
pinmux = <PINMUX_GPIO56__FUNC_B1_SDA0>,
<PINMUX_GPIO55__FUNC_B1_SCL0>;
bias-pull-up = <MTK_PULL_SET_RSEL_011>;
drive-strength-microamp = <1000>;
};
};
i2c2_pins: i2c2-pins {
pins {
pinmux = <PINMUX_GPIO60__FUNC_B1_SDA2>,
<PINMUX_GPIO59__FUNC_B1_SCL2>;
bias-pull-up = <MTK_PULL_SET_RSEL_011>;
drive-strength-microamp = <1000>;
};
};
i2c3_pins: i2c3-pins {
pins {
pinmux = <PINMUX_GPIO62__FUNC_B1_SDA3>,
<PINMUX_GPIO61__FUNC_B1_SCL3>;
bias-pull-up = <MTK_PULL_SET_RSEL_011>;
drive-strength-microamp = <1000>;
};
};
i2c5_pins: i2c5-pins {
pins {
pinmux = <PINMUX_GPIO66__FUNC_B1_SDA5>,
<PINMUX_GPIO65__FUNC_B1_SCL5>;
bias-pull-up = <MTK_PULL_SET_RSEL_011>;
drive-strength-microamp = <1000>;
};
};
i2c6_pins: i2c6-pins {
pins {
pinmux = <PINMUX_GPIO68__FUNC_B1_SDA6>,
<PINMUX_GPIO67__FUNC_B1_SCL6>;
bias-pull-up = <MTK_PULL_SET_RSEL_011>;
drive-strength-microamp = <1000>;
};
};
uart0_pins: uart0-pins {
pins {
pinmux = <PINMUX_GPIO31__FUNC_O_UTXD0>,
<PINMUX_GPIO32__FUNC_I1_URXD0>;
bias-pull-up;
};
};
uart1_pins: uart1-pins {
pins {
pinmux = <PINMUX_GPIO86__FUNC_O_UTXD1>,
<PINMUX_GPIO87__FUNC_I1_URXD1>;
bias-pull-up;
};
};
uart2_pins: uart2-pins {
pins {
pinmux = <PINMUX_GPIO35__FUNC_O_UTXD2>,
<PINMUX_GPIO36__FUNC_I1_URXD2>;
bias-pull-up;
};
};
pcie_pins_default: pcie-default {
mux {
pinmux = <PINMUX_GPIO47__FUNC_I1_WAKEN>,
<PINMUX_GPIO48__FUNC_O_PERSTN>,
<PINMUX_GPIO49__FUNC_B1_CLKREQN>;
bias-pull-up;
};
};
eth_default_pins: eth-default-pins {
pins-cc {
pinmux = <PINMUX_GPIO139__FUNC_B0_GBE_TXC>,
<PINMUX_GPIO140__FUNC_I0_GBE_RXC>,
<PINMUX_GPIO141__FUNC_I0_GBE_RXDV>,
<PINMUX_GPIO142__FUNC_O_GBE_TXEN>;
drive-strength = <8>;
};
pins-mdio {
pinmux = <PINMUX_GPIO143__FUNC_O_GBE_MDC>,
<PINMUX_GPIO144__FUNC_B1_GBE_MDIO>;
drive-strength = <8>;
input-enable;
};
pins-power {
pinmux = <PINMUX_GPIO145__FUNC_B_GPIO145>,
<PINMUX_GPIO146__FUNC_B_GPIO146>;
output-high;
};
pins-rxd {
pinmux = <PINMUX_GPIO135__FUNC_I0_GBE_RXD3>,
<PINMUX_GPIO136__FUNC_I0_GBE_RXD2>,
<PINMUX_GPIO137__FUNC_I0_GBE_RXD1>,
<PINMUX_GPIO138__FUNC_I0_GBE_RXD0>;
drive-strength = <8>;
};
pins-txd {
pinmux = <PINMUX_GPIO131__FUNC_O_GBE_TXD3>,
<PINMUX_GPIO132__FUNC_O_GBE_TXD2>,
<PINMUX_GPIO133__FUNC_O_GBE_TXD1>,
<PINMUX_GPIO134__FUNC_O_GBE_TXD0>;
drive-strength = <8>;
};
};
eth_sleep_pins: eth-sleep-pins {
pins-cc {
pinmux = <PINMUX_GPIO139__FUNC_B_GPIO139>,
<PINMUX_GPIO140__FUNC_B_GPIO140>,
<PINMUX_GPIO141__FUNC_B_GPIO141>,
<PINMUX_GPIO142__FUNC_B_GPIO142>;
};
pins-mdio {
pinmux = <PINMUX_GPIO143__FUNC_B_GPIO143>,
<PINMUX_GPIO144__FUNC_B_GPIO144>;
input-disable;
bias-disable;
};
pins-rxd {
pinmux = <PINMUX_GPIO135__FUNC_B_GPIO135>,
<PINMUX_GPIO136__FUNC_B_GPIO136>,
<PINMUX_GPIO137__FUNC_B_GPIO137>,
<PINMUX_GPIO138__FUNC_B_GPIO138>;
};
pins-txd {
pinmux = <PINMUX_GPIO131__FUNC_B_GPIO131>,
<PINMUX_GPIO132__FUNC_B_GPIO132>,
<PINMUX_GPIO133__FUNC_B_GPIO133>,
<PINMUX_GPIO134__FUNC_B_GPIO134>;
};
};
spi2_pins: spi2-pins {
pins-spi {
pinmux = <PINMUX_GPIO79__FUNC_O_SPIM2_CSB>,
<PINMUX_GPIO80__FUNC_O_SPIM2_CLK>,
<PINMUX_GPIO81__FUNC_B0_SPIM2_MOSI>,
<PINMUX_GPIO82__FUNC_B0_SPIM2_MISO>;
bias-disable;
};
};
audio_default_pins: audio-default-pins {
pins-cmd-dat {
pinmux = <PINMUX_GPIO121__FUNC_B0_PCM_CLK>,
<PINMUX_GPIO122__FUNC_B0_PCM_SYNC>,
<PINMUX_GPIO123__FUNC_O_PCM_DO>,
<PINMUX_GPIO124__FUNC_I0_PCM_DI>;
};
};
usb_default_pins: usb-default-pins {
pins-valid {
pinmux = <PINMUX_GPIO85__FUNC_I0_VBUSVALID>;
input-enable;
};
};
};
&eth {
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&eth_default_pins>;
pinctrl-1 = <&eth_sleep_pins>;
mediatek,mac-wol;
mediatek,tx-delay-ps = <30>;
snps,reset-active-low;
snps,reset-delays-us = <0 11000 200000>;
snps,reset-gpio = <&pio 147 GPIO_ACTIVE_LOW>;
status = "okay";
};
&eth_mdio {
ethernet_phy0: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
interrupts-extended = <&pio 148 IRQ_TYPE_LEVEL_LOW>;
eee-broken-1000t;
};
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
clock-frequency = <400000>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
clock-frequency = <400000>;
status = "okay";
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
clock-frequency = <400000>;
status = "okay";
};
&i2c5 {
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins>;
clock-frequency = <400000>;
status = "okay";
};
&i2c6 {
pinctrl-names = "default";
pinctrl-0 = <&i2c6_pins>;
clock-frequency = <400000>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "okay";
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pcie_pins_default>;
status = "okay";
};
&pciephy {
status = "okay";
};
&spi2 {
pinctrl-names = "default";
pinctrl-0 = <&spi2_pins>;
mediatek,pad-select = <0>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
};
&u3phy0 {
status = "okay";
};
&u3phy1 {
status = "okay";
};
&u3phy2 {
status = "okay";
};
&xhci1 {
#address-cells = <1>;
#size-cells = <0>;
vusb33-supply = <&mt6359_vusb_ldo_reg>;
status = "okay";
hub_2_0: hub@1 {
compatible = "usb451,8027";
reg = <1>;
peer-hub = <&hub_3_0>;
reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
vdd-supply = <&reg_fixed_3v3>;
};
hub_3_0: hub@2 {
compatible = "usb451,8025";
reg = <2>;
peer-hub = <&hub_2_0>;
reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
vdd-supply = <&reg_fixed_3v3>;
};
};
&xhci2 {
#address-cells = <1>;
#size-cells = <0>;
vusb33-supply = <&mt6359_vusb_ldo_reg>;
status = "okay";
hub@1 {
compatible = "microchip,usb2513bi";
reg = <1>;
vdd-supply = <&reg_fixed_3v3>;
};
};
&ssusb0 {
dr_mode = "peripheral";
pinctrl-names = "default";
pinctrl-0 = <&usb_default_pins>;
vusb33-supply = <&mt6359_vusb_ldo_reg>;
status = "okay";
};
&ssusb1 {
dr_mode = "host";
maximum-speed = "super-speed";
vusb33-supply = <&mt6359_vusb_ldo_reg>;
status = "okay";
};
&ssusb2 {
dr_mode = "host";
maximum-speed = "high-speed";
vusb33-supply = <&mt6359_vusb_ldo_reg>;
status = "okay";
};
&scp_cluster {
status = "okay";
};
&scp_c0 {
memory-region = <&scp_mem>;
status = "okay";
};
&gpu {
mali-supply = <&mt6359_vproc2_buck_reg>;
status = "okay";
};
&adsp {
memory-region = <&adsp_dma_mem>, <&adsp_mem>;
status = "okay";
};
&afe {
memory-region = <&afe_dma_mem>;
status = "okay";
};
&sound {
compatible = "mediatek,mt8390-mt6359-evk", "mediatek,mt8188-mt6359-evb";
model = "mt8390-evk";
pinctrl-names = "default";
pinctrl-0 = <&audio_default_pins>;
audio-routing =
"Headphone", "Headphone L",
"Headphone", "Headphone R",
"AP DMIC", "AUDGLB",
"AP DMIC", "MIC_BIAS_0",
"AP DMIC", "MIC_BIAS_2",
"DMIC_INPUT", "AP DMIC";
mediatek,adsp = <&adsp>;
status = "okay";
};

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2025 Grinn sp. z o.o.
* Author: Mateusz Koza <mateusz.koza@grinn-global.com>
*/
#include "mt6359.dtsi"
#include <dt-bindings/input/input.h>
/ {
aliases {
i2c1 = &i2c1;
mmc0 = &mmc0;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
status = "okay";
};
&mfg0 {
domain-supply = <&mt6359_vproc2_buck_reg>;
};
&mfg1 {
domain-supply = <&mt6359_vsram_others_ldo_reg>;
};
&mmc0 {
status = "okay";
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_default_pins>;
pinctrl-1 = <&mmc0_uhs_pins>;
bus-width = <8>;
max-frequency = <200000000>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
supports-cqe;
cap-mmc-hw-reset;
no-sdio;
no-sd;
hs400-ds-delay = <0x1481b>;
vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
vqmmc-supply = <&mt6359_vufs_ldo_reg>;
non-removable;
};
&mt6359_vbbck_ldo_reg {
regulator-always-on;
};
&mt6359_vcn18_ldo_reg {
regulator-name = "vcn18_pmu";
regulator-always-on;
};
&mt6359_vcn33_2_bt_ldo_reg {
regulator-name = "vcn33_2_pmu";
regulator-always-on;
};
&mt6359_vcore_buck_reg {
regulator-name = "dvdd_proc_l";
regulator-always-on;
};
&mt6359_vgpu11_buck_reg {
regulator-name = "dvdd_core";
regulator-always-on;
};
&mt6359_vpa_buck_reg {
regulator-name = "vpa_pmu";
regulator-max-microvolt = <3100000>;
};
&mt6359_vproc2_buck_reg {
/* The name "vgpu" is required by mtk-regulator-coupler */
regulator-name = "vgpu";
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <800000>;
regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>;
regulator-coupled-max-spread = <6250>;
};
&mt6359_vpu_buck_reg {
regulator-name = "dvdd_adsp";
regulator-always-on;
};
&mt6359_vrf12_ldo_reg {
regulator-name = "va12_abb2_pmu";
regulator-always-on;
};
&mt6359_vsim1_ldo_reg {
regulator-name = "vsim1_pmu";
regulator-enable-ramp-delay = <480>;
};
&mt6359_vsram_others_ldo_reg {
/* The name "vsram_gpu" is required by mtk-regulator-coupler */
regulator-name = "vsram_gpu";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <800000>;
regulator-coupled-with = <&mt6359_vproc2_buck_reg>;
regulator-coupled-max-spread = <6250>;
};
&mt6359_vufs_ldo_reg {
regulator-name = "vufs18_pmu";
regulator-always-on;
};
&pio {
i2c1_pins: i2c1-pins {
pins {
pinmux = <PINMUX_GPIO58__FUNC_B1_SDA1>,
<PINMUX_GPIO57__FUNC_B1_SCL1>;
bias-pull-up = <MTK_PULL_SET_RSEL_011>;
drive-strength-microamp = <1000>;
};
};
mmc0_default_pins: mmc0-default-pins {
pins-clk {
pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>;
drive-strength = <6>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins-cmd-dat {
pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>,
<PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>,
<PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>,
<PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>,
<PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>,
<PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>,
<PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>,
<PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>,
<PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>;
input-enable;
drive-strength = <6>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-rst {
pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>;
drive-strength = <6>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
mmc0_uhs_pins: mmc0-uhs-pins {
pins-clk {
pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>;
drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins-cmd-dat {
pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>,
<PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>,
<PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>,
<PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>,
<PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>,
<PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>,
<PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>,
<PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>,
<PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>;
input-enable;
drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-ds {
pinmux = <PINMUX_GPIO162__FUNC_B0_MSDC0_DSL>;
drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins-rst {
pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>;
drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
};
&pmic {
interrupt-parent = <&pio>;
interrupts = <222 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
keys {
compatible = "mediatek,mt6359-keys";
mediatek,long-press-mode = <1>;
power-off-time-sec = <0>;
power-key {
linux,keycodes = <KEY_POWER>;
wakeup-source;
};
};
};

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2025 MediaTek Inc.
* Author: Ramax Lo <ramax.lo@mediatek.com>
* Macpaul Lin <macpaul.lin@mediatek.com>
*/
/dts-v1/;
#include "mt8395-genio-common.dtsi"
/ {
model = "MediaTek Genio 1200 EVK-P1V2-UFS";
compatible = "mediatek,mt8395-evk-ufs", "mediatek,mt8395",
"mediatek,mt8195";
};
&ufshci {
status = "okay";
vcc-supply = <&mt6359_vemc_1_ldo_reg>;
vccq2-supply = <&mt6359_vufs_ldo_reg>;
};
&ufsphy {
status = "okay";
};
&mmc0 {
status = "disabled";
};

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