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Merge tag 'mtk-dts32-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt

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MediaTek ARM32 Device Tree updates

This performs a cleanup of the MT6582 devicetrees and adds support
for secondary cores bringup on this SoC.

This also introduces basic support for a new machine, the MT6582
Alcatel "yarisxl" Pop C7 (OT-7041D) smartphone, with support for
booting into a initramfs with UART console output.

* tag 'mtk-dts32-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux:
  ARM: dts: mediatek: drop wrong syscon hifsys compatible for MT2701/7623
  ARM: dts: mediatek: add basic support for Alcatel yarisxl board
  dt-bindings: arm: mediatek: Add MT6582 yarisxl
  ARM: dts: mediatek: mt6582: add enable-method property to cpus
  ARM: dts: mediatek: mt6582: add clock-names property to uart nodes
  ARM: dts: mediatek: mt6582: add mt6582 compatible to timer
  ARM: dts: mediatek: mt6582: remove compatible property from root node
  ARM: dts: mediatek: mt6582: sort nodes and properties
  ARM: dts: mediatek: mt6582: move MMIO devices under soc node

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2025-11-21 16:38:23 +01:00
parent ab07edaab6 5416aeee4e
commit c4aee1ad41
6 changed files with 139 additions and 73 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/arm/mediatek.yaml
View File

@@ -38,6 +38,7 @@ properties:
- const: mediatek,mt6580
- items:
- enum:
- alcatel,yarisxl
- prestigio,pmt5008-3g
- const: mediatek,mt6582
- items:

1
arch/arm/boot/dts/mediatek/Makefile
View File

@@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt6572-jty-d101.dtb \
mt6572-lenovo-a369i.dtb \
mt6580-evbp1.dtb \
mt6582-alcatel-yarisxl.dtb \
mt6582-prestigio-pmt5008-3g.dtb \
mt6589-aquaris5.dtb \
mt6589-fairphone-fp1.dtb \

2
arch/arm/boot/dts/mediatek/mt2701.dtsi
View File

@@ -597,7 +597,7 @@
};
hifsys: syscon@1a000000 {
compatible = "mediatek,mt2701-hifsys", "syscon";
compatible = "mediatek,mt2701-hifsys";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;

61
arch/arm/boot/dts/mediatek/mt6582-alcatel-yarisxl.dts Normal file
View File

@@ -0,0 +1,61 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2025 Cristian Cozzolino <cristian_ci@protonmail.com>
*/
/dts-v1/;
#include "mt6582.dtsi"
/ {
model = "Alcatel One Touch Pop C7 (OT-7041D)";
compatible = "alcatel,yarisxl", "mediatek,mt6582";
aliases {
serial0 = &uart0;
};
chosen {
#address-cells = <1>;
#size-cells = <1>;
stdout-path = "serial0:921600n8";
framebuffer: framebuffer@9fa00000 {
compatible = "simple-framebuffer";
memory-region = <&framebuffer_reserved>;
width = <480>;
height = <854>;
stride = <(480 * 4)>;
format = "r5g6b5";
};
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
connsys@9f900000 {
reg = <0x9f900000 0x100000>;
no-map;
};
modem@9e000000 {
reg = <0x9e000000 0x1800000>;
no-map;
};
framebuffer_reserved: framebuffer@9fa00000 {
reg = <0x9fa00000 0x600000>;
no-map;
};
};
};
&uart0 {
status = "okay";
};

144
arch/arm/boot/dts/mediatek/mt6582.dtsi
View File

@@ -9,12 +9,12 @@
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mediatek,mt6582";
interrupt-parent = <&sysirq>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
#address-cells = <1>;
enable-method = "mediatek,mt6589-smp";
cpu@0 {
device_type = "cpu";
@@ -38,91 +38,95 @@
};
};
uart_clk: dummy26m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
system_clk: dummy13m {
compatible = "fixed-clock";
clock-frequency = <13000000>;
#clock-cells = <0>;
clock-frequency = <13000000>;
};
rtc_clk: dummy32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32000>;
#clock-cells = <0>;
};
uart_clk: dummy26m {
compatible = "fixed-clock";
clock-frequency = <26000000>;
#clock-cells = <0>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
timer: timer@11008000 {
compatible = "mediatek,mt6577-timer";
reg = <0x10008000 0x80>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
clocks = <&system_clk>, <&rtc_clk>;
clock-names = "system-clk", "rtc-clk";
};
watchdog: watchdog@10007000 {
compatible = "mediatek,mt6582-wdt", "mediatek,mt6589-wdt";
reg = <0x10007000 0x100>;
};
sysirq: interrupt-controller@10200100 {
compatible = "mediatek,mt6582-sysirq",
"mediatek,mt6577-sysirq";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0x10200100 0x1c>;
};
timer: timer@10008000 {
compatible = "mediatek,mt6582-timer", "mediatek,mt6577-timer";
reg = <0x10008000 0x80>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
clocks = <&system_clk>, <&rtc_clk>;
};
gic: interrupt-controller@10211000 {
compatible = "arm,cortex-a7-gic";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0x10211000 0x1000>,
<0x10212000 0x2000>,
<0x10214000 0x2000>,
<0x10216000 0x2000>;
};
sysirq: interrupt-controller@10200100 {
compatible = "mediatek,mt6582-sysirq", "mediatek,mt6577-sysirq";
reg = <0x10200100 0x1c>;
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <3>;
};
uart0: serial@11002000 {
compatible = "mediatek,mt6582-uart",
"mediatek,mt6577-uart";
reg = <0x11002000 0x400>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
gic: interrupt-controller@10211000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
interrupt-controller;
interrupt-parent = <&gic>;
reg = <0x10211000 0x1000>,
<0x10212000 0x2000>,
<0x10214000 0x2000>,
<0x10216000 0x2000>;
};
uart1: serial@11003000 {
compatible = "mediatek,mt6582-uart",
"mediatek,mt6577-uart";
reg = <0x11003000 0x400>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
uart0: serial@11002000 {
compatible = "mediatek,mt6582-uart", "mediatek,mt6577-uart";
reg = <0x11002000 0x400>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
clock-names = "baud";
status = "disabled";
};
uart2: serial@11004000 {
compatible = "mediatek,mt6582-uart",
"mediatek,mt6577-uart";
reg = <0x11004000 0x400>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
uart1: serial@11003000 {
compatible = "mediatek,mt6582-uart", "mediatek,mt6577-uart";
reg = <0x11003000 0x400>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
clock-names = "baud";
status = "disabled";
};
uart3: serial@11005000 {
compatible = "mediatek,mt6582-uart",
"mediatek,mt6577-uart";
reg = <0x11005000 0x400>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
uart2: serial@11004000 {
compatible = "mediatek,mt6582-uart", "mediatek,mt6577-uart";
reg = <0x11004000 0x400>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
clock-names = "baud";
status = "disabled";
};
watchdog: watchdog@10007000 {
compatible = "mediatek,mt6582-wdt",
"mediatek,mt6589-wdt";
reg = <0x10007000 0x100>;
uart3: serial@11005000 {
compatible = "mediatek,mt6582-uart", "mediatek,mt6577-uart";
reg = <0x11005000 0x400>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
clock-names = "baud";
status = "disabled";
};
};
};

3
arch/arm/boot/dts/mediatek/mt7623.dtsi
View File

@@ -744,8 +744,7 @@
hifsys: syscon@1a000000 {
compatible = "mediatek,mt7623-hifsys",
"mediatek,mt2701-hifsys",
"syscon";
"mediatek,mt2701-hifsys";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;