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riscv: dts: starfive: Add common board dtsi for VisionFive 2 Lite variants

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Add a common board dtsi for use by VisionFive 2 Lite and
VisionFive 2 Lite eMMC.

Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Tested-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Hal Feng
2025-11-25 15:56:02 +08:00
committed by Conor Dooley
parent 84853940a7
commit 2ad6d71a0d
1 changed files with 161 additions and 0 deletions
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161
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2025 StarFive Technology Co., Ltd.
* Copyright (C) 2025 Hal Feng <hal.feng@starfivetech.com>
*/
/dts-v1/;
#include "jh7110-common.dtsi"
/ {
vcc_3v3_pcie: regulator-vcc-3v3-pcie {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&sysgpio 27 GPIO_ACTIVE_HIGH>;
regulator-name = "vcc_3v3_pcie";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&cpu_opp {
/delete-node/ opp-375000000;
/delete-node/ opp-500000000;
/delete-node/ opp-750000000;
/delete-node/ opp-1500000000;
opp-312500000 {
opp-hz = /bits/ 64 <312500000>;
opp-microvolt = <800000>;
};
opp-417000000 {
opp-hz = /bits/ 64 <417000000>;
opp-microvolt = <800000>;
};
opp-625000000 {
opp-hz = /bits/ 64 <625000000>;
opp-microvolt = <800000>;
};
opp-1250000000 {
opp-hz = /bits/ 64 <1250000000>;
opp-microvolt = <1000000>;
};
};
&gmac0 {
starfive,tx-use-rgmii-clk;
assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
status = "okay";
};
&i2c0 {
status = "okay";
};
&mmc1 {
max-frequency = <50000000>;
keep-power-in-suspend;
non-removable;
};
&pcie1 {
vpcie3v3-supply = <&vcc_3v3_pcie>;
status = "okay";
};
&phy0 {
motorcomm,tx-clk-adj-enabled;
motorcomm,tx-clk-100-inverted;
motorcomm,tx-clk-1000-inverted;
motorcomm,rx-clk-drv-microamp = <3970>;
motorcomm,rx-data-drv-microamp = <2910>;
rx-internal-delay-ps = <1500>;
tx-internal-delay-ps = <1500>;
};
&pwm {
status = "okay";
};
&spi0 {
status = "okay";
};
&syscrg {
assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <1250000000>;
};
&sysgpio {
uart1_pins: uart1-0 {
tx-pins {
pinmux = <GPIOMUX(22, GPOUT_SYS_UART1_TX,
GPOEN_ENABLE,
GPI_NONE)>;
bias-disable;
drive-strength = <12>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
rx-pins {
pinmux = <GPIOMUX(23, GPOUT_LOW,
GPOEN_DISABLE,
GPI_SYS_UART1_RX)>;
bias-pull-up;
drive-strength = <2>;
input-enable;
input-schmitt-enable;
slew-rate = <0>;
};
cts-pins {
pinmux = <GPIOMUX(24, GPOUT_LOW,
GPOEN_DISABLE,
GPI_SYS_UART1_CTS)>;
input-enable;
};
rts-pins {
pinmux = <GPIOMUX(25, GPOUT_SYS_UART1_RTS,
GPOEN_ENABLE,
GPI_NONE)>;
input-enable;
};
};
usb0_pins: usb0-0 {
power-pins {
pinmux = <GPIOMUX(26, GPOUT_HIGH,
GPOEN_ENABLE,
GPI_NONE)>;
input-disable;
};
switch-pins {
pinmux = <GPIOMUX(62, GPOUT_LOW,
GPOEN_ENABLE,
GPI_NONE)>;
input-disable;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
&usb0 {
dr_mode = "host";
pinctrl-names = "default";
pinctrl-0 = <&usb0_pins>;
status = "okay";
};
&usb_cdns3 {
phys = <&usbphy0>, <&pciephy0>;
phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy";
};