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riscv: dts: starfive: jh7110-common: Move out some nodes to the board dts
Some node in this file are not used by the upcoming VisionFive 2 Lite board. Move them to the board dts to prepare for adding the new VisionFive 2 Lite device tree. Tested-by: Matthias Brugger <mbrugger@suse.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
@@ -281,14 +281,8 @@
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assigned-clock-rates = <50000000>;
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bus-width = <8>;
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bootph-pre-ram;
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cap-mmc-highspeed;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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cap-mmc-hw-reset;
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins>;
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vmmc-supply = <&vcc_3v3>;
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vqmmc-supply = <&emmc_vdd>;
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status = "okay";
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};
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@@ -298,8 +292,6 @@
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assigned-clock-rates = <50000000>;
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bus-width = <4>;
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bootph-pre-ram;
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cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
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disable-wp;
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cap-sd-highspeed;
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pinctrl-names = "default";
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pinctrl-0 = <&mmc1_pins>;
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@@ -11,6 +11,15 @@
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compatible = "deepcomputing,fml13v01", "starfive,jh7110";
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};
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&mmc0 {
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cap-mmc-highspeed;
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cap-mmc-hw-reset;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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vmmc-supply = <&vcc_3v3>;
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vqmmc-supply = <&emmc_vdd>;
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};
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&mmc0_pins {
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rst-pins {
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pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
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@@ -24,6 +33,11 @@
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};
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};
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&mmc1 {
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cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
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disable-wp;
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};
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&pcie1 {
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perst-gpios = <&sysgpio 21 GPIO_ACTIVE_LOW>;
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phys = <&pciephy1>;
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@@ -22,6 +22,15 @@
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status = "okay";
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};
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&mmc0 {
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cap-mmc-highspeed;
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cap-mmc-hw-reset;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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vmmc-supply = <&vcc_3v3>;
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vqmmc-supply = <&emmc_vdd>;
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};
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&mmc0_pins {
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rst-pins {
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pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
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@@ -35,6 +44,11 @@
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};
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};
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&mmc1 {
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cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
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disable-wp;
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};
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&pcie0 {
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status = "okay";
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};
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@@ -10,3 +10,12 @@
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model = "Milk-V Mars CM";
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compatible = "milkv,marscm-emmc", "starfive,jh7110";
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};
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&mmc0 {
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cap-mmc-highspeed;
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cap-mmc-hw-reset;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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vmmc-supply = <&vcc_3v3>;
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vqmmc-supply = <&emmc_vdd>;
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};
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@@ -14,6 +14,7 @@
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&mmc0 {
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bus-width = <4>;
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cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
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disable-wp;
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};
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&mmc0_pins {
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@@ -44,6 +44,15 @@
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status = "okay";
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};
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&mmc0 {
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cap-mmc-highspeed;
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cap-mmc-hw-reset;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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vmmc-supply = <&vcc_3v3>;
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vqmmc-supply = <&emmc_vdd>;
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};
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&mmc0_pins {
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rst-pins {
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pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
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@@ -57,6 +66,11 @@
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};
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};
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&mmc1 {
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cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
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disable-wp;
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};
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&pcie1 {
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status = "okay";
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};
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@@ -38,6 +38,12 @@
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};
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&mmc0 {
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cap-mmc-highspeed;
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cap-mmc-hw-reset;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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vmmc-supply = <&vcc_3v3>;
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vqmmc-supply = <&emmc_vdd>;
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non-removable;
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};
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@@ -54,6 +60,11 @@
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};
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};
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&mmc1 {
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cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
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disable-wp;
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};
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&pcie0 {
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status = "okay";
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};
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