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Daniel Machon
d41bb5e00e phy: sparx5-serdes: add support for private match data 
In order to reuse the existing Sparx5 SERDES driver for lan969x, we add
support for private match data, with initial fields for the iomap and
imap_size.

Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Link: https://lore.kernel.org/r/20240909-sparx5-lan969x-serdes-driver-v2-1-d695bcb57b84@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-22 00:02:03 +05:30
Rafał Miłecki
0175a673e4 phy: bcm-ns-usb2: drop support for old binding variant 
The old binding was incorrectly designed and ended up being deprecated 3
years ago. Finally it has been dropped so relevant code it not needed
anymore.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Link: https://lore.kernel.org/r/20240913044557.28315-2-zajec5@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-21 23:56:16 +05:30
Rafał Miłecki
c3639d423d dt-bindings: phy: bcm-ns-usb2-phy: drop deprecated variant 
The old binding variant (the one covering whole DMU block) was
deprecated 3 years ago. Linux kernel was warning when using it for
similar amount of time.

There aren't any known Northstar devices with bootloader providing DT to
operating system. Actually OpenWrt seems to be the only project using
this binding and it always appends DTB to kernel. It has switched to the
non-deprecated binding years ago.

Given there is close to zero chance this breaks anyone's setup it should
more than safe to drop this binding variant after 3 years.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240913044557.28315-1-zajec5@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-21 23:56:16 +05:30
Xin Liu
30c280bc8e dt-bindings: phy: Add QMP UFS PHY compatible for QCS8300 
Document the QMP UFS PHY compatible for Qualcomm QCS8300 to support
physical layer functionality for UFS found on the SoC. Use fallback to
indicate the compatibility of the QMP UFS PHY on the QCS8300 with that
on the SA8775P.

Signed-off-by: Xin Liu <quic_liuxin@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
Link: https://lore.kernel.org/r/20241018-qcs8300_ufs_phy_binding-v4-1-261c7c5fb8ff@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-21 23:46:18 +05:30
Dmitry Baryshkov
8e1e94619b dt-bindings: phy: qcom: snps-eusb2: Add SAR2130P compatible 
Document the Synopsys eUSB2 PHY on the SAR2130P platform by using
the SM8550 as fallback.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241017-sar2130p-eusb2-v1-1-1cedd674ec64@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-21 23:37:50 +05:30
Ilya Orazov
26ac85e3ad dt-bindings: phy: ti,tcan104x-can: Document Microchip ATA6561 
Microchip ATA6561 is High-Speed CAN Transceiver with Standby Mode.
It is pin-compatible with TI TCAN1042 and has a compatible programming
model, therefore use ti,tcan1042 as fallback compatible.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Ilya Orazov <ilordash02@gmail.com>
Link: https://lore.kernel.org/r/20240915141831.2809208-2-ilordash02@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-17 20:53:58 +05:30
Lorenzo Bianconi
e56272f2bb phy: airoha: Fix REG_CSR_2L_RX{0,1}_REV0 definitions 
Fix the following register definitions for REG_CSR_2L_RX{0,1}_REV0
registers:
- CSR_2L_PXP_VOS_PNINV
- CSR_2L_PXP_FE_GAIN_NORMAL_MODE
- CSR_2L_PXP_FE_GAIN_TRAIN_MODE

Fixes: d7d2818b93 ("phy: airoha: Add PCIe PHY driver for EN7581 SoC.")
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Link: https://lore.kernel.org/r/20240918-airoha-en7581-phy-fixes-v1-4-8291729a87f8@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-17 20:52:48 +05:30
Lorenzo Bianconi
6fd016c965 phy: airoha: Fix REG_CSR_2L_JCPLL_SDM_HREN config in airoha_pcie_phy_init_ssc_jcpll() 
Fix typo configuring REG_CSR_2L_JCPLL_SDM_HREN register in
airoha_pcie_phy_init_ssc_jcpll routine.

Fixes: d7d2818b93 ("phy: airoha: Add PCIe PHY driver for EN7581 SoC.")
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Link: https://lore.kernel.org/r/20240918-airoha-en7581-phy-fixes-v1-3-8291729a87f8@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-17 20:52:48 +05:30
Lorenzo Bianconi
f9c5d6369d phy: airoha: Fix REG_PCIE_PMA_TX_RESET config in airoha_pcie_phy_init_csr_2l() 
Fix typos configuring REG_PCIE_PMA_TX_RESET register in
airoha_pcie_phy_init_csr_2l routine for lane0 and lane1

Fixes: d7d2818b93 ("phy: airoha: Add PCIe PHY driver for EN7581 SoC.")
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Link: https://lore.kernel.org/r/20240918-airoha-en7581-phy-fixes-v1-2-8291729a87f8@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-17 20:52:48 +05:30
Lorenzo Bianconi
09a19fb754 phy: airoha: Fix REG_CSR_2L_PLL_CMN_RESERVE0 config in airoha_pcie_phy_init_clk_out() 
Fix typo configuring REG_CSR_2L_PLL_CMN_RESERVE0 register in
airoha_pcie_phy_init_clk_out routine.

Fixes: d7d2818b93 ("phy: airoha: Add PCIe PHY driver for EN7581 SoC.")
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Link: https://lore.kernel.org/r/20240918-airoha-en7581-phy-fixes-v1-1-8291729a87f8@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-17 20:52:48 +05:30
Andy Yan
f2dbca1697 phy: phy-rockchip-samsung-hdptx: Don't request RST_PHY/RST_ROPLL/RST_LCPLL 
RST_PHY/RST_ROPLL/RST_LCPLL are used for debug only on rk3588,
and they are not exported on rk3576, no need to request it in
driver.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Link: https://lore.kernel.org/r/20240920093629.7410-1-andyshrk@163.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-17 20:50:22 +05:30
Dmitry Baryshkov
c9be539e11 phy: add NXP PTN3222 eUSB2 to USB2 redriver 
The NXP PTN3222 is the single-port eUSB2 to USB2 redriver that performs
translation between eUSB2 and USB2 signalling schemes. It supports all
three data rates: Low Speed, Full Speed and High Speed.

The reset state enables autonegotiation of the PHY role and of the data
rate, so no additional programming is required.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Konrad Dybcio <konradybcio@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Tested-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Link: https://lore.kernel.org/r/20240830-nxp-ptn3222-v2-2-4c6d8535cf6c@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-17 20:48:27 +05:30
Dmitry Baryshkov
2df490e737 dt-bindings: phy: add NXP PTN3222 eUSB2 to USB2 redriver 
The NXP PTN3222 is the single-port eUSB2 to USB2 redriver that performs
translation between eUSB2 and USB2 signalling schemes. It supports all
three data rates: Low Speed, Full Speed and High Speed.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Link: https://lore.kernel.org/r/20240830-nxp-ptn3222-v2-1-4c6d8535cf6c@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-17 20:48:27 +05:30
Xu Yang
76b4f2a5ce dt-bindings: phy: mxs-usb-phy: add imx8qxp compatible 
Add "fsl,imx8qxp-usbphy" compatible.

Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240926073951.783869-2-xu.yang_2@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-17 20:42:24 +05:30
Heiko Stuebner
de30906910 dt-bindings: phy: rk3228-hdmi-phy: convert to yaml 
Convert the binding to yaml and rename it according to its first
compatible instead of the unspecific rockchip-inno-hdmi naming.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20241007162732.2450168-1-heiko@sntech.de
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-17 20:40:00 +05:30
Uwe Kleine-König
54234e3a69 phy: Switch back to struct platform_driver::remove() 
After commit 0edb555a65 ("platform: Make platform_driver::remove()
return void") .remove() is (again) the right callback to implement for
platform drivers.

Convert all platform drivers below drivers/phy/ to use .remove(), with
the eventual goal to drop struct platform_driver::remove_new(). As
.remove() and .remove_new() have the same prototypes, conversion is done
by just changing the structure member name in the driver initializer.

While touching these files, make indention of the struct initializer
consistent in several files.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
Link: https://lore.kernel.org/r/20241009065307.504930-2-u.kleine-koenig@baylibre.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-17 20:33:03 +05:30
Macpaul Lin
2ac03d0811 dt-bindings: phy: mediatek: tphy: add a property for power-domains 
Include the MediaTek TPHY in a power domain.  Add the 'power-domains'
property in the Device Tree (DT) Schema and set 'maxItems: 1'.

Also, include a reminder in the description of the 'power-domains'
property.

Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241012035016.17667-1-macpaul.lin@mediatek.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-17 20:26:07 +05:30
Soutrik Mukhopadhyay
3f12bf1621 phy: qcom: edp: Add support for eDP PHY on SA8775P 
Add support for eDP PHY v5 found on the Qualcomm SA8775P platform.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Link: https://lore.kernel.org/r/20241004103046.22209-4-quic_mukhopad@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-17 20:16:30 +05:30
Soutrik Mukhopadhyay
913463587d phy: qcom: edp: Introduce aux_cfg array for version specific aux settings 
In order to support different HW versions, introduce aux_cfg array
to move v4 specific aux configuration settings.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Link: https://lore.kernel.org/r/20241004103046.22209-3-quic_mukhopad@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-17 20:16:30 +05:30
Soutrik Mukhopadhyay
7adb3d221a dt-bindings: phy: Add eDP PHY compatible for sa8775p 
Add compatible string for the supported eDP PHY on sa8775p platform.

Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241004103046.22209-2-quic_mukhopad@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-17 20:16:30 +05:30
Frank Wang
a76de028c6 phy: rockchip: usbdp: add rk3576 device match data 
This adds RK3576 device match data support.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Acked-by: Dragan Simic <dsimic@manjaro.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20241014020342.15974-2-frawang.cn@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-17 20:11:05 +05:30
Frank Wang
b3e804ab9a dt-bindings: phy: rockchip-usbdp: add rk3576 
Add compatible for the USBDP phy in the Rockchip RK3576 SoC.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Dragan Simic <dsimic@manjaro.org>
Link: https://lore.kernel.org/r/20241014020342.15974-1-frawang.cn@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-17 20:11:05 +05:30
Adam Ford
7588444551 phy: freescale: fsl-samsung-hdmi: Remove unnecessary LUT entries 
The lookup table contains entries which use the integer divider
instead of just the fractional divider. Since the set and round
functions check both the integer divider values and the LUT values,
it's no longer necessary to keep the integer divider values in the
lookup table, as can be dynamically calcuated.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Dominique Martinet <dominique.martinet@atmark-techno.com>
Tested-by: Dominique Martinet <dominique.martinet@atmark-techno.com>
Link: https://lore.kernel.org/r/20240914112816.520224-6-aford173@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-17 18:43:36 +05:30
Adam Ford
058ea4a067 phy: freescale: fsl-samsung-hdmi: Use closest divider 
Currently, if the clock values cannot be set to the exact rate,
the round_rate and set_rate functions use the closest value found in
the look-up-table.  In preparation of removing values from the LUT
that can be calculated evenly with the integer calculator, it's
necessary to ensure to check both the look-up-table and the integer
divider clock values to get the closest values to the requested
value.  It does this by measuring the difference between the
requested clock value and the closest value in both integer divider
calucator and the fractional clock look-up-table.

Which ever has the smallest difference between them is returned as
the closest rate.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Dominique Martinet <dominique.martinet@atmark-techno.com>
Tested-by: Dominique Martinet <dominique.martinet@atmark-techno.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Link: https://lore.kernel.org/r/20240914112816.520224-5-aford173@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-17 18:43:36 +05:30
Adam Ford
1951dbb41d phy: freescale: fsl-samsung-hdmi: Support dynamic integer 
There is currently a look-up table for a variety of resolutions.
Since the phy has the ability to dynamically calculate the values
necessary to use the intger divider which should allow more
resolutions without having to update the look-up-table.

If the lookup table cannot find an exact match, fall back to the
dynamic calculator of the integer divider.

Previously, the value of P was hard-coded to 1, this required an
update to the phy_pll_cfg table to add in the extra value into the
table, so if the value of P is calculated to be something else
by the PMS calculator, the calculated_phy_pll_cfg structure
can be used instead without having to keep track of which method
was used.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Dominique Martinet <dominique.martinet@atmark-techno.com>
Tested-by: Dominique Martinet <dominique.martinet@atmark-techno.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Link: https://lore.kernel.org/r/20240914112816.520224-4-aford173@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-17 18:43:36 +05:30
Adam Ford
375ee44adb phy: freescale: fsl-samsung-hdmi: Simplify REG21_PMS_S_MASK lookup 
The value of 'S' is writen to two places, PHY_REG3[7:4] and
PHY_REG21[3:0].  There is a lookup table which contains
the value of PHY_REG3.  Rather than using a switch statement
based on the pixel clock to search for the value of 'S' again,
just shift the contents of PHY_REG3[7:4] >> 4 and place the value
in PHY_REG21[3:0].  Doing this can eliminate an entire function.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Dominique Martinet <dominique.martinet@atmark-techno.com>
Tested-by: Dominique Martinet <dominique.martinet@atmark-techno.com>
Link: https://lore.kernel.org/r/20240914112816.520224-3-aford173@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-17 18:43:35 +05:30
Adam Ford
4a5a9e2577 phy: freescale: fsl-samsung-hdmi: Replace register defines with macro 
There are 47 registers defined as PHY_REG_xx were xx goes from 00 to
47.  Simplify this by replacing them all with a macro which is passed
the register number to return the proper register offset.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Dominique Martinet <dominique.martinet@atmark-techno.com>
Tested-by: Dominique Martinet <dominique.martinet@atmark-techno.com>
Link: https://lore.kernel.org/r/20240914112816.520224-2-aford173@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-17 18:43:35 +05:30
William Wu
3d7de6e870 phy: rockchip: inno-usb2: Add usb2 phys support for rk3576 
The RK3576 SoC has two independent USB2.0 PHYs, and each PHY has
one port. This adds device specific data for it.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20241016073713.14133-4-frawang.cn@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-17 18:29:40 +05:30
Frank Wang
0217f4aef0 dt-bindings: phy: rockchip,inno-usb2phy: add rk3576 
Add compatible for the USB2 phy in the Rockchip RK3576 SoC.

This change also refactor the clocks list as there are new clocks
adding used for the USB MMU in RK3576 SoC.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20241016073713.14133-3-frawang.cn@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-17 18:29:40 +05:30
Frank Wang
86e2ed4e9a phy: rockchip: inno-usb2: convert clock management to bulk 
Since some Rockchip SoCs (e.g RK3576) have more than one clock,
this converts the clock management from single to bulk method to
make the driver more flexible.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20241016073713.14133-1-frawang.cn@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-17 18:29:40 +05:30
Yang Li
e592a65584 phy: stm32: Remove unneeded semicolon 
This patch removes an unneeded semicolon after a switch statement.

./drivers/phy/st/phy-stm32-combophy.c:226:2-3: Unneeded semicolon

Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=11403
Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
Link: https://lore.kernel.org/r/20241017040657.33992-1-yang.lee@linux.alibaba.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-17 18:24:46 +05:30
Qiang Yu
e961ec81a3 phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3 
Currently driver supports only x4 lane based functionality using tx/rx and
tx2/rx2 pair of register sets. To support 8 lane functionality with PCIe3,
PCIe3 related QMP PHY provides additional programming which are available
as txz and rxz based register set. Hence add txz and rxz based registers
usage and programming sequences.

As soon as software programs the txz and rxz based register set, hardware
shall "broadcast" the same settings to the tx/rx pair of registers for all
the 8 lanes, which saves the effort of software programming them one by
one.

There might be some tx and/or rx registers on some lanes need minor tweaks,
program them after programming the txz and rxz reigster set.

In addition, x1e80100 uses QMP PHY ver 6.30 for PCIe Gen4 x8, hence add
two new header files to reflect the new register offsets.

Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konradybcio@kernel.org>
Link: https://lore.kernel.org/r/20241017030412.265000-5-quic_qianyu@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-17 18:21:52 +05:30
Qiang Yu
26fb23ce35 dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x8 
PCIe 3rd instance of X1E80100 supports Gen 4 x8 which needs different
8 lane capable QMP PCIe PHY with hardware revision v6.30. Document Gen
4 x8 PHY as separate module.

Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20241017030412.265000-2-quic_qianyu@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-17 18:21:52 +05:30
Sayali Lokhande
6a612c86c8 dt-bindings: phy: Add QMP UFS PHY comptible for QCS615 
Document the QMP UFS PHY compatible for Qualcomm QCS615 to support physical
layer functionality for UFS found on the SoC. Use fallback to indicate the
compatibility of the QMP UFS PHY on the QCS615 with that on the SM6115.

Signed-off-by: Sayali Lokhande <quic_sayalil@quicinc.com>
Co-developed-by: Xin Liu <quic_liuxin@quicinc.com>
Signed-off-by: Xin Liu <quic_liuxin@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241017042300.872963-2-quic_liuxin@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-17 18:12:38 +05:30
Yijie Yang
03b9d469e0 dt-bindings: phy: describe the Qualcomm SGMII PHY 
Describe the SGMII/SerDes PHY present on the qcs8300 platforms. Since
qcs8300 shares the same SerDes as sa8775p, so it fallback to the
compatible.

Signed-off-by: Yijie Yang <quic_yijiyang@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241017-schema-v2-2-2320f68dc126@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-17 18:07:30 +05:30
Andrew Kreimer
11dad94b50 phy: sun4i-usb: Fix a typo 
Fix a typo in comments: wether -> whether.

Signed-off-by: Andrew Kreimer <algonell@gmail.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Link: https://lore.kernel.org/r/20241010091355.8271-1-algonell@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-11 14:37:29 +05:30
Krishna Kurapati
5ee213bdbc phy: qcom: qmp: Add qmp configuration for QCS8300 
Add qmp configuration for QCS8300. It is similar to SA8775P and
SC8280XP except for some Lane configuration settings specific to
QCS8300.

Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241009195348.2649368-5-quic_kriskura@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-11 14:27:30 +05:30
Krishna Kurapati
c2b174209b dt-bindings: phy: qcom,sc8280xp-qmp-usb3-uni: Add QCS8300 compatible 
Update dt-bindings to add QCS8300 to QMP Uni Phy list.

Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20241009195348.2649368-4-quic_kriskura@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-11 14:27:29 +05:30
Krishna Kurapati
c5a3519eae dt-bindings: phy: qcom,usb-snps-femto-v2: Add bindings for QCS8300 
Update dt-bindings to add QCS8300 to USB2 SNPS Femto Phy list.

Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20241009195348.2649368-3-quic_kriskura@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-11 14:27:29 +05:30
Krishna Kurapati
3624fa00ae dt-bindings: usb: qcom,dwc3: Add QCS8300 to USB DWC3 bindings 
Update dt-bindings to add QCS8300 to USB DWC3 controller list.
The second controller of QCS8300 is High speed only capable and
doesn't have ss_phy_irq.

Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20241009195348.2649368-2-quic_kriskura@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-11 14:27:29 +05:30
Siddharth Vadapalli
9e544d46a2 phy: ti: gmii-sel: Enable USXGMII mode for J7200 
TI's J7200 SoC supports USXGMII mode with the CPSW5G instance's MAC Port1.
Add USXGMII mode to the extra_modes member of J7200's SoC data.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20241010144845.2555983-1-s-vadapalli@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-11 13:59:44 +05:30
Siddharth Vadapalli
bbcc9e2bde dt-bindings: phy: cadence-sierra: Allow PHY types QSGMII and SGMII 
The Sierra SERDES can be configured for QSGMII and SGMII protocols. Hence,
update the bindings to treat "PHY_TYPE_QSGMII" and "PHY_TYPE_SGMII" as
valid values for the "cdns,phy-type" property.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240930095145.3004053-1-s-vadapalli@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-07 12:18:55 +05:30
Christian Bruel
b6a713b92e MAINTAINERS: add entry for ST STM32MP25 COMBOPHY driver 
Add myself as STM32MP25 COMBOPHY maintainer

Signed-off-by: Christian Bruel <christian.bruel@foss.st.com>
Link: https://lore.kernel.org/r/20240930170847.948779-4-christian.bruel@foss.st.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-07 12:17:07 +05:30
Christian Bruel
47e1bb6b4b phy: stm32: Add support for STM32MP25 COMBOPHY. 
Addition of the COMBOPHY driver found on STM32MP25 platforms

This single lane PHY is shared (exclusive) between the USB3 and PCIE
controllers.
Supports 5Gbit/s for PCIE gen2 or 2.5Gbit/s for PCIE gen1.

Supports wakeup-source capability to wakeup system using remote-wakeup
capable USB device

Signed-off-by: Christian Bruel <christian.bruel@foss.st.com>
Link: https://lore.kernel.org/r/20240930170847.948779-3-christian.bruel@foss.st.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-07 12:17:07 +05:30
Christian Bruel
8c7e955fac dt-bindings: phy: Add STM32MP25 COMBOPHY bindings 
Document the bindings for STM32 COMBOPHY interface, used to support
the PCIe and USB3 stm32mp25 drivers.
Following entries can be used to tune caracterisation parameters
 - st,output-micro-ohms and st,output-vswing-microvolt bindings entries
to tune the impedance and voltage swing using discrete simulation results
 - st,rx-equalizer register to set the internal rx equalizer filter value.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Christian Bruel <christian.bruel@foss.st.com>
Link: https://lore.kernel.org/r/20240930170847.948779-2-christian.bruel@foss.st.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-07 12:17:07 +05:30
Josua Mayer
d6c496f05e phy: mvebu-cp110-utmi: support swapping d+/d- lanes by dts property 
CP11x UTMI PHY supports swapping D+/D- signals via digital control
register 1.

Add support for the "swap-dx-lanes" device-tree property, which lists
the port-ids that should swap D+ and D-.
The property is evaluated in probe and applied before power-on
during mvebu_cp110_utmi_port_setup.

Signed-off-by: Josua Mayer <josua@solid-run.com>
Link: https://lore.kernel.org/r/20241002-mvebu-utmi-phy-v4-1-83783dc89b9d@solid-run.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-07 12:00:19 +05:30
Dragan Simic
4045252085 phy: phy-rockchip-inno-usb2: Use dev_err_probe() in the probe path 
Improve error handling in the probe path by using function dev_err_probe()
instead of function dev_err(), where appropriate.

Signed-off-by: Dragan Simic <dsimic@manjaro.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/d4ccd9fc278fb46ea868406bf77811ee507f0e4e.1725524803.git.dsimic@manjaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-07 11:53:16 +05:30
Dragan Simic
595ad7a336 phy: phy-rockchip-inno-usb2: Handle failed extcon allocation better 
Return the actual error code upon failure to allocate extcon device, instead
of hardcoding -ENOMEM.  Use dev_err_probe() to also log appropriate messages,
which is fine because the containing function is used in the probe path.

Helped-by: Heiko Stubner <heiko@sntech.de>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Dragan Simic <dsimic@manjaro.org>
Link: https://lore.kernel.org/r/cc4995aa3e569be6bc23ca126b41fba82d50eeee.1725524802.git.dsimic@manjaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-07 11:53:16 +05:30
Dragan Simic
449d2a523a phy: phy-rockchip-inno-usb2: Perform trivial code cleanups 
Perform a few trivial code cleanups, e.g. to obey the reverse Christmas tree
rule, to avoid use of "{ ... }" code blocks where they aren't really needed,
or to avoid line wrapping by using the 100-column width better.

No intended functional changes are introduced by these code cleanups.

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Dragan Simic <dsimic@manjaro.org>
Link: https://lore.kernel.org/r/adce7309f6fd9e1191c53bab552a8531d1a71216.1725524802.git.dsimic@manjaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-07 11:53:16 +05:30
Sam Edwards
d3712b35f3 phy: usb: update Broadcom driver table to use designated initializers 
The Broadcom USB PHY driver contains a lookup table
(`reg_bits_map_tables`) to resolve register bitmaps unique to certain
versions of the USB PHY as found in various Broadcom chip families.
Historically, this table was just kept carefully in sync with the
"selector" enum every time the latter changed to ensure consistency.
However, a recent commit [1] introduced two new enumerators but did not
adjust the array for BCM4908, thus breaking the xHCI controller (and
boot process) on this platform and revealing the fragility of this
approach.

Since these arrays are a little sparse (many elements are zero) and the
position of the array elements is significant only insofar as they agree
with the enumerators, designated initializers are a better fit than
positional initializers here. Convert this table accordingly.

[1] 4536fe9640 ("phy: usb: suppress OC condition for 7439b2")

Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Reviewed-by: Justin Chen <justin.chen@broadcom.com>
Link: https://lore.kernel.org/r/20241004034131.1363813-3-CFSworks@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2024-10-07 11:45:34 +05:30