Renesas DTS updates for v6.6
- Add Clocked Serial Interface (CSI) support for the RZ/V2M SoC,
- Add PMIC, RTC, and PWM support for the RZ/G2L, RZ/G2LC, and RZ/V2L
SMARC EVK development boards,
- Add PWM (MTU3a) support for the RZ/G2UL and RZ/Five SoCs,
- Add External interrupt (INTC-EX) support for the R-Car S4-8 SoC,
- Add LED support for the Spider development board,
- Miscellaneous fixes and improvements.
* tag 'renesas-dts-for-v6.6-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: dts: renesas: spider-cpu: Add GP LEDs
arm64: dts: renesas: r8a779f0: Add INTC-EX node
arm64: dts: renesas: rzg2ul-smarc: Add support for enabling MTU3
arm64: dts: renesas: r9a07g043: Add MTU3a node
ARM dts: renesas: armadillo800eva: Switch to enable-gpios
arm64: dts: renesas: rzg2lc-smarc-som: Enable PMIC and built-in RTC
arm64: dts: renesas: rzg2lc-smarc-som: Add PHY interrupt support for ETH0
riscv: dts: renesas: Clean up dtbs_check W=1 warning due to empty phy node
arm64: dts: renesas: rzg2lc-smarc: Add support for enabling MTU3
arm64: dts: renesas: rzg2l-smarc: Add support for enabling MTU3
arm64: dts: renesas: Add missing space before {
ARM: dts: renesas: Add missing space before {
arm64: dts: renesas: Minor whitespace cleanup around '='
arm64: dts: renesas: rzg2l-smarc-som: Enable PMIC and built-in RTC
arm64: dts: renesas: r9a09g011: Add CSI nodes
arm64: dts: renesas: rzg2l: Fix txdv-skew-psec typos
arm64: dts: renesas: rzg2l: Update overfow/underflow IRQ names for MTU3 channels
Link: https://lore.kernel.org/r/cover.1690545144.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
arm64: tegra: Device tree changes for v6.6-rc1
The majority of this is fixes all over the place for DT schema
validation warnings. However, there are also cleanups for some things in
DT and audio support is added on IGX Orin. Jetson Orin NX and Nano also
gain a new thermal trip point to help keep the device cool at moderate
loads.
* tag 'tegra-for-6.6-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (22 commits)
arm64: tegra: Add blank lines for better readability
arm64: tegra: Remove {clock,reset}-names from VIC powergate
arm64: tegra: Drop incorrect maxim,disable-etr on Smaug
arm64: tegra: Add SPI device tree nodes for Tegra234
arm64: tegra: Enable UARTA and UARTE for Orin Nano
arm64: tegra: Add UARTE device tree node on Tegra234
arm64: tegra: Adapt to LP855X bindings changes
arm64: tegra: Add PCIe and DP 3.3V supplies
arm64: tegra: Add missing reset-names for Tegra HS UART
arm64: tegra: Remove current-speed for SBSA UART
arm64: tegra: smaug: Remove reg-shift for high-speed UART
arm64: tegra: Remove dmas and dma-names for debug UART
arm64: tegra: Add 35°C trip point for Jetson Orin NX/Nano
arm64: tegra: Remove duplicate PCI nodes
arm64: tegra: Sort PCI nodes correctly on Orin
arm64: tegra: Add audio support for IGX Orin
arm64: tegra: Update CPU OPP tables
arm64: tegra: Fix HSUART for Smaug
arm64: tegra: Fix HSUART for Jetson AGX Orin
arm64: tegra: Add missing alias for NVIDIA IGX Orin
...
Link: https://lore.kernel.org/r/20230728094129.3587109-4-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
ARM: tegra: Device tree changes for v6.6-rc1
This contains various fixes for DT schema validation and the Pegatron
Chagall and Nexus 7 get specific compatible strings for the panels that
they use.
* tag 'tegra-for-6.6-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: Provide specific compatible string for Nexus 7 panel
ARM: tegra: Use Hannstar HSD101PWW2 on Pegatron Chagall
ARM: tegra: Reuse I2C3 for NVEC
ARM: tegra: Add missing reset-names for Tegra HS UART
ARM: tegra: Remove reset-names for UART devices
ARM: tegra: Remove dmas and dma-names for debug UART
Link: https://lore.kernel.org/r/20230728094129.3587109-3-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
dt-bindings: Changes for v6.6-rc1
A number of Tegra-specific bindings are converted to json-schema and the
reserved-memory and BPMP bindings get support for Tegra264.
* tag 'tegra-for-6.6-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
dt-bindings: firmware: Add support for tegra186-bpmp DRAM MRQ GSCs
dt-bindings: reserved-memory: Add support for DRAM MRQ GSCs
dt-bindings: thermal: tegra: Convert to json-schema
dt-bindings: arm: tegra: nvec: Convert to json-schema
dt-bindings: clock: tegra: Document Tegra132 compatible
dt-bindings: cpu: Document NVIDIA Tegra186 CCPLEX cluster
dt-bindings: serial: tegra-hsuart: Convert to json-schema
dt-bindings: arm: tegra: ahb: Convert to json-schema
dt-bindings: arm: tegra: flowctrl: Convert to json-schema
Link: https://lore.kernel.org/r/20230728094129.3587109-2-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Without this change the KSZ9477 Evaluation board's Linux (v6.5-rc1) shows
following device warning:
'ksz-switch spi1.0: Port 5 interpreting RGMII delay settings based on "phy-mode" property, please update device tree to specify "rx-internal-delay-ps" and "tx-internal-delay-ps"'
This is not critical, as KSZ driver by itself assigns default value of
tx delay to 2000 ps (as 'rgmii-txid' is set as PHY mode).
However, to avoid extra warnings in logs - the missing 'tx-internal-delay-ps'
has been specified with the default value of 2000 ps.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Link: https://lore.kernel.org/r/20230727080656.3828397-1-lukma@denx.de
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Without this change the KSZ9477-EVB board hangs just after passing
execution flow from u-boot to Linux kernel.
This code has been copied from at91-sama5d3_xplained.dts.
Test setup: Linux 6.5-rc1
Config: arch/arm/configs/sama5_defconfig
Toolchain: gcc-linaro-7.3.1-2018.05-x86_64_arm-linux-gnueabi
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Link: https://lore.kernel.org/r/20230712152111.3756211-1-lukma@denx.de
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
panel-lvds alone is not a valid compatible string and we always need a
specific compatible string as well. Nexus 7 can come with one of (at
least) two panels, so pick one of them as the specific compatible
string.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The LVDS bindings require a specific compatible string in addition to
the generic "panel-lvds". Add the HannStar HSD101PWW2 which is used on
a similar device (ASUS TF201) and seems to work fine with slightly
modified timings in DT.
Suggested-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Instead of duplicating the I2C3 node and adding NVEC specific
properties, reuse the I2C3 node, extend it with NVEC specific properties
and drop properties that are not needed by NVEC. This results in a DTB
that is a bit cleaner and avoids accidentally using I2C3 and NVEC which
would have them fight over the same hardware resources.
Signed-off-by: Thierry Reding <treding@nvidia.com>
According to the device tree bindings, the powergate definition nodes
don't contain clock-names and reset-names properties, so remove them.
Signed-off-by: Thierry Reding <treding@nvidia.com>
There is no "maxim,disable-etr" property (but there is
maxim,enable-etr), neither in the bindings nor in the Linux driver:
tegra210-smaug.dtb: regulator@1c: Unevaluated properties are not allowed ('maxim,disable-etr' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Create the device tree nodes for the SPI1, SPI2 and SPI3 controllers
found on Tegra234.
Signed-off-by: Gautham Srinivasan <gauthams@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Activate UARTA and UARTE functionalities for Orin Nano.
- UARTA is accessible via the 40-pin header with pin 8 and 10 (TX/RX)
- UARTE utilizes the M2.E connector
Signed-off-by: Gautham Srinivasan <gauthams@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit adds the device tree node for UARTE on Tegra234.
Signed-off-by: Gautham Srinivasan <gauthams@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add the 3.3V supplies for PCIe C1 controller and Display Port controller
for the NVIDIA IGX Orin platform.
Signed-off-by: Shubhi Garg <shgarg@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The device tree bindings for the Tegra high-speed UART require the
reset-names property, so add it whenever the compatible string for the
serial port is overwritten.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The debug UART doesn't support DMA and the DT bindings prohibit the use
of the dmas and dma-names properties for it, so remove them.
Signed-off-by: Thierry Reding <treding@nvidia.com>
It turns out that these devices can get quite hot to the touch with the
standard cooling configuration, so add another trip point at 35°C along
with a cooling map to help keep the system reasonably cool at very low
system load.
Reviewed-by: Yi-Wei Wang <yiweiw@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The PCI nodes for Jetson Orin NX are already defined at the carrier
board level, so the duplicates can be dropped at the platform level.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add audio support for the NVIDIA IGX Orin development kit having P3701
module with P3740 carrier board.
Move the common device-tree nodes to a new file tegra234-p3701.dtsi and
use this for Jetson AGX Orin and NVIDIA IGX Orin platforms
Signed-off-by: Mohan Kumar <mkumard@nvidia.com>
[treding@nvidia.com: properly sort nodes]
Signed-off-by: Thierry Reding <treding@nvidia.com>
Convert the Tegra thermal bindings from the free-form text format to
json-schema.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Convert the NVIDIA embedded controller bindings from the free-form text
format to json-schema.
Acked-by: Marc Dietrich <marvin24@gmx.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The Tegra132 clock and reset controller is largely compatible with the
version found on Tegra124 but it does have slight differences in what
clocks it exposes, so a separate compatible string is needed.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
dtbs_check w/ W=1 complains:
Warning (unit_address_vs_reg): /soc/ethernet@11c20000/ethernet-phy@7: node has a unit name, but no reg or ranges property
Warning (avoid_unnecessary_addr_size): /soc/ethernet@11c20000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
The ethernet@11c20000 node is guarded by an `#if (!SW_ET0_EN_N)` in
rzg2ul-smarc-som.dtsi, where the phy child node is added. In
rzfive-smarc-som.dtsi, the ethernet node is marked disabled & the
interrupt properties are deleted from the phy child node. As a result,
the produced dts looks like:
ethernet@11c20000 {
compatible = "renesas,r9a07g043-gbeth",
"renesas,rzg2l-gbeth";
/* snip */
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ethernet-phy@7 {
};
};
Adding a corresponding `#if (!SW_ET0_EN_N)` around the node in
rzfive-smarc-som.dtsi avoids the complaint, as the empty child node is
not added:
ethernet@11c20000 {
compatible = "renesas,r9a07g043-gbeth",
"renesas,rzg2l-gbeth";
/* snip */
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230712-squealer-walmart-9587342ddec1@wendy
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add support for PMOD_MTU3 macro to enable MTU3 node on RZ/{G2,V2}L SMARC
EVK.
The MTU3a PWM pins are muxed with spi1 pins and counter external input
phase clock pins are muxed with scif2 pins. Disable these IPs when
PMOD_MTU3 macro is enabled.
Apart from this, the counter Z phase clock signal is muxed with the
SDHI1 cd signal. So disable SDHI1 IP, when the counter Z phase signal
is enabled.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230706153047.368993-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
