mirror of
https://github.com/torvalds/linux.git
synced 2025-12-07 20:06:24 +00:00
net: stmmac: socfpga: Add hardware supported cross-timestamp
Cross timestamping is supported on Agilex5 platform with Synchronized
Multidrop Timestamp Gathering(SMTG) IP. The hardware cross-timestamp
result is made available the applications through the ioctl call
PTP_SYS_OFFSET_PRECISE, which inturn calls stmmac_getcrosststamp().
Device time is stored in the MAC Auxiliary register. The 64-bit System
time (ARM_ARCH_COUNTER) is stored in SMTG IP. SMTG IP is an MDIO device
with 0xC - 0xF MDIO register space holds 64-bit system time.
This commit is similar to following commit for Intel platforms:
Commit 341f67e424 ("net: stmmac: Add hardware supported cross-timestamp")
Signed-off-by: Rohan G Thomas <rohan.g.thomas@altera.com>
Link: https://patch.msgid.link/20251101-agilex5_ext-v2-4-a6b51b4dca4d@altera.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Rohan G Thomas
committed by
Jakub Kicinski
Jakub Kicinski
parent
e28988aef7
commit
fd8c4f6454
@@ -5,6 +5,7 @@
|
||||
*/
|
||||
|
||||
#include <linux/mfd/altera-sysmgr.h>
|
||||
#include <linux/clocksource_ids.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_net.h>
|
||||
@@ -15,8 +16,10 @@
|
||||
#include <linux/reset.h>
|
||||
#include <linux/stmmac.h>
|
||||
|
||||
#include "dwxgmac2.h"
|
||||
#include "stmmac.h"
|
||||
#include "stmmac_platform.h"
|
||||
#include "stmmac_ptp.h"
|
||||
|
||||
#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
|
||||
#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
|
||||
@@ -41,6 +44,13 @@
|
||||
#define SGMII_ADAPTER_ENABLE 0x0000
|
||||
#define SGMII_ADAPTER_DISABLE 0x0001
|
||||
|
||||
#define SMTG_MDIO_ADDR 0x15
|
||||
#define SMTG_TSC_WORD0 0xC
|
||||
#define SMTG_TSC_WORD1 0xD
|
||||
#define SMTG_TSC_WORD2 0xE
|
||||
#define SMTG_TSC_WORD3 0xF
|
||||
#define SMTG_TSC_SHIFT 16
|
||||
|
||||
struct socfpga_dwmac;
|
||||
struct socfpga_dwmac_ops {
|
||||
int (*set_phy_mode)(struct socfpga_dwmac *dwmac_priv);
|
||||
@@ -269,6 +279,112 @@ static int socfpga_set_phy_mode_common(int phymode, u32 *val)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void get_smtgtime(struct mii_bus *mii, int smtg_addr, u64 *smtg_time)
|
||||
{
|
||||
u64 ns;
|
||||
|
||||
ns = mdiobus_read(mii, smtg_addr, SMTG_TSC_WORD3);
|
||||
ns <<= SMTG_TSC_SHIFT;
|
||||
ns |= mdiobus_read(mii, smtg_addr, SMTG_TSC_WORD2);
|
||||
ns <<= SMTG_TSC_SHIFT;
|
||||
ns |= mdiobus_read(mii, smtg_addr, SMTG_TSC_WORD1);
|
||||
ns <<= SMTG_TSC_SHIFT;
|
||||
ns |= mdiobus_read(mii, smtg_addr, SMTG_TSC_WORD0);
|
||||
|
||||
*smtg_time = ns;
|
||||
}
|
||||
|
||||
static int smtg_crosststamp(ktime_t *device, struct system_counterval_t *system,
|
||||
void *ctx)
|
||||
{
|
||||
struct stmmac_priv *priv = (struct stmmac_priv *)ctx;
|
||||
u32 num_snapshot, gpio_value, acr_value;
|
||||
void __iomem *ptpaddr = priv->ptpaddr;
|
||||
void __iomem *ioaddr = priv->hw->pcsr;
|
||||
unsigned long flags;
|
||||
u64 smtg_time = 0;
|
||||
u64 ptp_time = 0;
|
||||
int i, ret;
|
||||
u32 v;
|
||||
|
||||
/* Both internal crosstimestamping and external triggered event
|
||||
* timestamping cannot be run concurrently.
|
||||
*/
|
||||
if (priv->plat->flags & STMMAC_FLAG_EXT_SNAPSHOT_EN)
|
||||
return -EBUSY;
|
||||
|
||||
mutex_lock(&priv->aux_ts_lock);
|
||||
/* Enable Internal snapshot trigger */
|
||||
acr_value = readl(ptpaddr + PTP_ACR);
|
||||
acr_value &= ~PTP_ACR_MASK;
|
||||
switch (priv->plat->int_snapshot_num) {
|
||||
case AUX_SNAPSHOT0:
|
||||
acr_value |= PTP_ACR_ATSEN0;
|
||||
break;
|
||||
case AUX_SNAPSHOT1:
|
||||
acr_value |= PTP_ACR_ATSEN1;
|
||||
break;
|
||||
case AUX_SNAPSHOT2:
|
||||
acr_value |= PTP_ACR_ATSEN2;
|
||||
break;
|
||||
case AUX_SNAPSHOT3:
|
||||
acr_value |= PTP_ACR_ATSEN3;
|
||||
break;
|
||||
default:
|
||||
mutex_unlock(&priv->aux_ts_lock);
|
||||
return -EINVAL;
|
||||
}
|
||||
writel(acr_value, ptpaddr + PTP_ACR);
|
||||
|
||||
/* Clear FIFO */
|
||||
acr_value = readl(ptpaddr + PTP_ACR);
|
||||
acr_value |= PTP_ACR_ATSFC;
|
||||
writel(acr_value, ptpaddr + PTP_ACR);
|
||||
/* Release the mutex */
|
||||
mutex_unlock(&priv->aux_ts_lock);
|
||||
|
||||
/* Trigger Internal snapshot signal. Create a rising edge by just toggle
|
||||
* the GPO0 to low and back to high.
|
||||
*/
|
||||
gpio_value = readl(ioaddr + XGMAC_GPIO_STATUS);
|
||||
gpio_value &= ~XGMAC_GPIO_GPO0;
|
||||
writel(gpio_value, ioaddr + XGMAC_GPIO_STATUS);
|
||||
gpio_value |= XGMAC_GPIO_GPO0;
|
||||
writel(gpio_value, ioaddr + XGMAC_GPIO_STATUS);
|
||||
|
||||
/* Poll for time sync operation done */
|
||||
ret = readl_poll_timeout(priv->ioaddr + XGMAC_INT_STATUS, v,
|
||||
(v & XGMAC_INT_TSIS), 100, 10000);
|
||||
if (ret) {
|
||||
netdev_err(priv->dev, "%s: Wait for time sync operation timeout\n",
|
||||
__func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
*system = (struct system_counterval_t) {
|
||||
.cycles = 0,
|
||||
.cs_id = CSID_ARM_ARCH_COUNTER,
|
||||
.use_nsecs = false,
|
||||
};
|
||||
|
||||
num_snapshot = (readl(ioaddr + XGMAC_TIMESTAMP_STATUS) &
|
||||
XGMAC_TIMESTAMP_ATSNS_MASK) >>
|
||||
XGMAC_TIMESTAMP_ATSNS_SHIFT;
|
||||
|
||||
/* Repeat until the timestamps are from the FIFO last segment */
|
||||
for (i = 0; i < num_snapshot; i++) {
|
||||
read_lock_irqsave(&priv->ptp_lock, flags);
|
||||
stmmac_get_ptptime(priv, ptpaddr, &ptp_time);
|
||||
*device = ns_to_ktime(ptp_time);
|
||||
read_unlock_irqrestore(&priv->ptp_lock, flags);
|
||||
}
|
||||
|
||||
get_smtgtime(priv->mii, SMTG_MDIO_ADDR, &smtg_time);
|
||||
system->cycles = smtg_time;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int socfpga_gen5_set_phy_mode(struct socfpga_dwmac *dwmac)
|
||||
{
|
||||
struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr;
|
||||
@@ -473,6 +589,10 @@ static void socfpga_agilex5_setup_plat_dat(struct socfpga_dwmac *dwmac)
|
||||
/* Tx Queues 0 - 5 doesn't support TBS on Agilex5 */
|
||||
break;
|
||||
}
|
||||
|
||||
/* Hw supported cross-timestamp */
|
||||
plat_dat->int_snapshot_num = AUX_SNAPSHOT0;
|
||||
plat_dat->crosststamp = smtg_crosststamp;
|
||||
}
|
||||
|
||||
static int socfpga_dwmac_probe(struct platform_device *pdev)
|
||||
|
||||
@@ -79,6 +79,7 @@
|
||||
#define XGMAC_PSRQ(x) GENMASK((x) * 8 + 7, (x) * 8)
|
||||
#define XGMAC_PSRQ_SHIFT(x) ((x) * 8)
|
||||
#define XGMAC_INT_STATUS 0x000000b0
|
||||
#define XGMAC_INT_TSIS BIT(12)
|
||||
#define XGMAC_LPIIS BIT(5)
|
||||
#define XGMAC_PMTIS BIT(4)
|
||||
#define XGMAC_INT_EN 0x000000b4
|
||||
@@ -173,6 +174,8 @@
|
||||
#define XGMAC_MDIO_ADDR 0x00000200
|
||||
#define XGMAC_MDIO_DATA 0x00000204
|
||||
#define XGMAC_MDIO_C22P 0x00000220
|
||||
#define XGMAC_GPIO_STATUS 0x0000027c
|
||||
#define XGMAC_GPIO_GPO0 BIT(16)
|
||||
#define XGMAC_ADDRx_HIGH(x) (0x00000300 + (x) * 0x8)
|
||||
#define XGMAC_ADDR_MAX 32
|
||||
#define XGMAC_AE BIT(31)
|
||||
@@ -220,6 +223,8 @@
|
||||
#define XGMAC_OB BIT(0)
|
||||
#define XGMAC_RSS_DATA 0x00000c8c
|
||||
#define XGMAC_TIMESTAMP_STATUS 0x00000d20
|
||||
#define XGMAC_TIMESTAMP_ATSNS_MASK GENMASK(29, 25)
|
||||
#define XGMAC_TIMESTAMP_ATSNS_SHIFT 25
|
||||
#define XGMAC_TXTSC BIT(15)
|
||||
#define XGMAC_TXTIMESTAMP_NSEC 0x00000d30
|
||||
#define XGMAC_TXTSSTSLO GENMASK(30, 0)
|
||||
|
||||
Reference in New Issue
Block a user