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drm/i915/irq: use a dedicated IMR cache for gen 5-7

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There are three groups of platforms using i915->irq_mask independently:
gen 2-4, VLV/CHV, and gen 5-7.

The gen 5-7 usage is primarily limited to display. Move its irq_mask
usage to struct intel_display as ilk_de_imr_mask for gen 5-7.

ilk_de_imr_mask could be put inside a union with with vlv_imr_mask and
de_irq_mask[], but keep them separate to avoid accidental aliasing of
the values.

With this, we can also drop the irq_mask member from struct xe_device.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://lore.kernel.org/r/adf60e74b890d52dd20ab4673111ae2063d33b49.1758198300.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula
2025-09-18 15:25:45 +03:00
parent 96b8ccbe7f
commit f2c6777dd9
4 changed files with 12 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/drm/i915/display/intel_display_core.h
View File

@@ -480,6 +480,11 @@ struct intel_display {
* bitfield.
*/
u32 vlv_imr_mask;
/*
* Cached value of gen 5-7 DE IMR to avoid reads in updating the
* bitfield.
*/
u32 ilk_de_imr_mask;
u32 de_irq_mask[I915_MAX_PIPES];
u32 pipestat_irq_mask[I915_MAX_PIPES];
} irq;

14
drivers/gpu/drm/i915/display/intel_display_irq.c
View File

@@ -140,14 +140,14 @@ void ilk_update_display_irq(struct intel_display *display,
lockdep_assert_held(&display->irq.lock);
drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask);
new_val = dev_priv->irq_mask;
new_val = display->irq.ilk_de_imr_mask;
new_val &= ~interrupt_mask;
new_val |= (~enabled_irq_mask & interrupt_mask);
if (new_val != dev_priv->irq_mask &&
if (new_val != display->irq.ilk_de_imr_mask &&
!drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv))) {
dev_priv->irq_mask = new_val;
intel_de_write(display, DEIMR, dev_priv->irq_mask);
display->irq.ilk_de_imr_mask = new_val;
intel_de_write(display, DEIMR, display->irq.ilk_de_imr_mask);
intel_de_posting_read(display, DEIMR);
}
}
@@ -2180,8 +2180,6 @@ out:
void ilk_de_irq_postinstall(struct intel_display *display)
{
struct drm_i915_private *i915 = to_i915(display->drm);
u32 display_mask, extra_mask;
if (DISPLAY_VER(display) >= 7) {
@@ -2213,11 +2211,11 @@ void ilk_de_irq_postinstall(struct intel_display *display)
if (display->platform.ironlake && display->platform.mobile)
extra_mask |= DE_PCU_EVENT;
i915->irq_mask = ~display_mask;
display->irq.ilk_de_imr_mask = ~display_mask;
ibx_irq_postinstall(display);
intel_display_irq_regs_init(display, DE_IRQ_REGS, i915->irq_mask,
intel_display_irq_regs_init(display, DE_IRQ_REGS, display->irq.ilk_de_imr_mask,
display_mask | extra_mask);
}

2
drivers/gpu/drm/i915/i915_irq.c
View File

@@ -659,7 +659,7 @@ static void ilk_irq_reset(struct drm_i915_private *dev_priv)
struct intel_uncore *uncore = &dev_priv->uncore;
gen2_irq_reset(uncore, DE_IRQ_REGS);
dev_priv->irq_mask = ~0u;
display->irq.ilk_de_imr_mask = ~0u;
if (GRAPHICS_VER(dev_priv) == 7)
intel_uncore_write(uncore, GEN7_ERR_INT, 0xffffffff);

3
drivers/gpu/drm/xe/xe_device_types.h
View File

@@ -611,9 +611,6 @@ struct xe_device {
/* To shut up runtime pm macros.. */
struct xe_runtime_pm {} runtime_pm;
/* only to allow build, not used functionally */
u32 irq_mask;
struct intel_uncore {
spinlock_t lock;
} uncore;