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net: stmmac: add support for controlling PCS interrupts

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Add support to the PCS instance for controlling the PCS interrupts
depending on whether the PCS is used.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/E1vBrtp-0000000BMYs-3bhI@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Russell King (Oracle)
2025-10-23 10:46:25 +01:00
committed by Jakub Kicinski
parent 442a8c68f0
commit eed68edac5
6 changed files with 34 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
View File

@@ -38,11 +38,10 @@
#define GMAC_INT_DISABLE_PCSAN BIT(2)
#define GMAC_INT_DISABLE_PMT BIT(3)
#define GMAC_INT_DISABLE_TIMESTAMP BIT(9)
#define GMAC_INT_DISABLE_PCS (GMAC_INT_DISABLE_PCSLINK | \
GMAC_INT_DISABLE_PCSAN)
#define GMAC_INT_DEFAULT_MASK (GMAC_INT_DISABLE_RGMII | \
GMAC_INT_DISABLE_TIMESTAMP | \
GMAC_INT_DISABLE_PCS)
GMAC_INT_DISABLE_PCSLINK | \
GMAC_INT_DISABLE_PCSAN | \
GMAC_INT_DISABLE_TIMESTAMP)
/* PMT Control and Status */
#define GMAC_PMT 0x0000002c

11
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
View File

@@ -27,7 +27,9 @@ static int dwmac1000_pcs_init(struct stmmac_priv *priv)
if (!priv->dma_cap.pcs)
return 0;
return stmmac_integrated_pcs_init(priv, GMAC_PCS_BASE);
return stmmac_integrated_pcs_init(priv, GMAC_PCS_BASE,
GMAC_INT_DISABLE_PCSLINK |
GMAC_INT_DISABLE_PCSAN);
}
static void dwmac1000_core_init(struct mac_device_info *hw,
@@ -48,12 +50,7 @@ static void dwmac1000_core_init(struct mac_device_info *hw,
writel(value | GMAC_CORE_INIT, ioaddr + GMAC_CONTROL);
/* Mask GMAC interrupts */
value = GMAC_INT_DEFAULT_MASK;
if (hw->pcs)
value &= ~GMAC_INT_DISABLE_PCS;
writel(value, ioaddr + GMAC_INT_MASK);
writel(GMAC_INT_DEFAULT_MASK, ioaddr + GMAC_INT_MASK);
#ifdef STMMAC_VLAN_TAG_USED
/* Tag detection without filtering */

2
drivers/net/ethernet/stmicro/stmmac/dwmac4.h
View File

@@ -106,8 +106,6 @@
#define GMAC_INT_LPI_EN BIT(5)
#define GMAC_INT_TSIE BIT(12)
#define GMAC_PCS_IRQ_DEFAULT (GMAC_INT_PCS_LINK | GMAC_INT_PCS_ANE)
#define GMAC_INT_DEFAULT_ENABLE (GMAC_INT_PMT_EN | GMAC_INT_LPI_EN | \
GMAC_INT_TSIE)

10
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
View File

@@ -27,7 +27,8 @@ static int dwmac4_pcs_init(struct stmmac_priv *priv)
if (!priv->dma_cap.pcs)
return 0;
return stmmac_integrated_pcs_init(priv, GMAC_PCS_BASE);
return stmmac_integrated_pcs_init(priv, GMAC_PCS_BASE,
GMAC_INT_PCS_LINK | GMAC_INT_PCS_ANE);
}
static void dwmac4_core_init(struct mac_device_info *hw,
@@ -46,12 +47,7 @@ static void dwmac4_core_init(struct mac_device_info *hw,
writel((clk_rate / 1000000) - 1, ioaddr + GMAC4_MAC_ONEUS_TIC_COUNTER);
/* Enable GMAC interrupts */
value = GMAC_INT_DEFAULT_ENABLE;
if (hw->pcs)
value |= GMAC_PCS_IRQ_DEFAULT;
writel(value, ioaddr + GMAC_INT_EN);
writel(GMAC_INT_DEFAULT_ENABLE, ioaddr + GMAC_INT_EN);
if (GMAC_INT_DEFAULT_ENABLE & GMAC_INT_TSIE)
init_waitqueue_head(&priv->tstamp_busy_wait);

22
drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
View File

@@ -2,6 +2,22 @@
#include "stmmac.h"
#include "stmmac_pcs.h"
static int dwmac_integrated_pcs_enable(struct phylink_pcs *pcs)
{
struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
stmmac_mac_irq_modify(spcs->priv, 0, spcs->int_mask);
return 0;
}
static void dwmac_integrated_pcs_disable(struct phylink_pcs *pcs)
{
struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
stmmac_mac_irq_modify(spcs->priv, spcs->int_mask, 0);
}
static void dwmac_integrated_pcs_get_state(struct phylink_pcs *pcs,
unsigned int neg_mode,
struct phylink_link_state *state)
@@ -23,11 +39,14 @@ static int dwmac_integrated_pcs_config(struct phylink_pcs *pcs,
}
static const struct phylink_pcs_ops dwmac_integrated_pcs_ops = {
.pcs_enable = dwmac_integrated_pcs_enable,
.pcs_disable = dwmac_integrated_pcs_disable,
.pcs_get_state = dwmac_integrated_pcs_get_state,
.pcs_config = dwmac_integrated_pcs_config,
};
int stmmac_integrated_pcs_init(struct stmmac_priv *priv, unsigned int offset)
int stmmac_integrated_pcs_init(struct stmmac_priv *priv, unsigned int offset,
u32 int_mask)
{
struct stmmac_pcs *spcs;
@@ -37,6 +56,7 @@ int stmmac_integrated_pcs_init(struct stmmac_priv *priv, unsigned int offset)
spcs->priv = priv;
spcs->base = priv->ioaddr + offset;
spcs->int_mask = int_mask;
spcs->pcs.ops = &dwmac_integrated_pcs_ops;
__set_bit(PHY_INTERFACE_MODE_SGMII, spcs->pcs.supported_interfaces);

4
drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
View File

@@ -52,6 +52,7 @@ struct stmmac_priv;
struct stmmac_pcs {
struct stmmac_priv *priv;
void __iomem *base;
u32 int_mask;
struct phylink_pcs pcs;
};
@@ -61,7 +62,8 @@ phylink_pcs_to_stmmac_pcs(struct phylink_pcs *pcs)
return container_of(pcs, struct stmmac_pcs, pcs);
}
int stmmac_integrated_pcs_init(struct stmmac_priv *priv, unsigned int offset);
int stmmac_integrated_pcs_init(struct stmmac_priv *priv, unsigned int offset,
u32 int_mask);
/**
* dwmac_pcs_isr - TBI, RTBI, or SGMII PHY ISR