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x86/cpu/topology: Make primary thread mask available with SMP=n
cpu_primary_thread_mask is only defined when CONFIG_SMP=y. However, even
in UP kernels there is always exactly one CPU, which can reasonably be
treated as the primary thread.
Historically, topology_is_primary_thread() always returned true with
CONFIG_SMP=n. A recent commit:
4b455f5994 ("cpu/SMT: Provide a default topology_is_primary_thread()")
replaced it with a generic implementation with the note:
"When disabling SMT, the primary thread of the SMT will remain
enabled/active. Architectures that have a special primary thread (e.g.
x86) need to override this function. ..."
For consistency and clarity, make the primary thread mask available
regardless of SMP, similar to cpu_possible_mask and cpu_present_mask.
Move __cpu_primary_thread_mask into common code to prevent build issues.
Let cpu_mark_primary_thread() configure the mask even for UP kernels,
alongside other masks. Then, topology_is_primary_thread() can
consistently reference it.
Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Link: https://lore.kernel.org/r/20250320234104.8288-1-chang.seok.bae@intel.com
This commit is contained in:
committed by
Borislav Petkov (AMD)
parent
3a86608788
commit
ed44a5625f
@@ -218,6 +218,12 @@ static inline unsigned int topology_amd_nodes_per_pkg(void)
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return __amd_nodes_per_pkg;
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}
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#else /* CONFIG_SMP */
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static inline int topology_phys_to_logical_pkg(unsigned int pkg) { return 0; }
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static inline int topology_max_smt_threads(void) { return 1; }
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static inline unsigned int topology_amd_nodes_per_pkg(void) { return 1; }
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#endif /* !CONFIG_SMP */
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extern struct cpumask __cpu_primary_thread_mask;
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#define cpu_primary_thread_mask ((const struct cpumask *)&__cpu_primary_thread_mask)
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@@ -241,12 +247,6 @@ static inline bool topology_is_core_online(unsigned int cpu)
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}
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#define topology_is_core_online topology_is_core_online
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#else /* CONFIG_SMP */
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static inline int topology_phys_to_logical_pkg(unsigned int pkg) { return 0; }
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static inline int topology_max_smt_threads(void) { return 1; }
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static inline unsigned int topology_amd_nodes_per_pkg(void) { return 1; }
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#endif /* !CONFIG_SMP */
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static inline void arch_fix_phys_package_id(int num, u32 slot)
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{
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}
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@@ -75,15 +75,11 @@ bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
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return phys_id == (u64)cpuid_to_apicid[cpu];
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}
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#ifdef CONFIG_SMP
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static void cpu_mark_primary_thread(unsigned int cpu, unsigned int apicid)
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{
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if (!(apicid & (__max_threads_per_core - 1)))
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cpumask_set_cpu(cpu, &__cpu_primary_thread_mask);
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}
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#else
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static inline void cpu_mark_primary_thread(unsigned int cpu, unsigned int apicid) { }
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#endif
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/*
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* Convert the APIC ID to a domain level ID by masking out the low bits
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@@ -16,6 +16,9 @@ EXPORT_SYMBOL_GPL(x86_topo_system);
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unsigned int __amd_nodes_per_pkg __ro_after_init;
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EXPORT_SYMBOL_GPL(__amd_nodes_per_pkg);
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/* CPUs which are the primary SMT threads */
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struct cpumask __cpu_primary_thread_mask __read_mostly;
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void topology_set_dom(struct topo_scan *tscan, enum x86_topology_domains dom,
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unsigned int shift, unsigned int ncpus)
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{
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@@ -103,9 +103,6 @@ EXPORT_PER_CPU_SYMBOL(cpu_core_map);
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DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map);
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EXPORT_PER_CPU_SYMBOL(cpu_die_map);
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/* CPUs which are the primary SMT threads */
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struct cpumask __cpu_primary_thread_mask __read_mostly;
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/* Representing CPUs for which sibling maps can be computed */
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static cpumask_var_t cpu_sibling_setup_mask;
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