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https://github.com/torvalds/linux.git
synced 2025-12-07 20:06:24 +00:00
net: txgbe: support RSC offload
Support to enable and disable RSC for txgbe devices. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> Link: https://patch.msgid.link/20251023014538.12644-4-jiawenwu@trustnetic.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
@@ -51,6 +51,11 @@ static const struct wx_stats wx_gstrings_fdir_stats[] = {
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WX_STAT("fdir_miss", stats.fdirmiss),
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};
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static const struct wx_stats wx_gstrings_rsc_stats[] = {
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WX_STAT("rsc_aggregated", rsc_count),
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WX_STAT("rsc_flushed", rsc_flush),
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};
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/* drivers allocates num_tx_queues and num_rx_queues symmetrically so
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* we set the num_rx_queues to evaluate to num_tx_queues. This is
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* used because we do not have a good way to get the max number of
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@@ -64,16 +69,21 @@ static const struct wx_stats wx_gstrings_fdir_stats[] = {
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(sizeof(struct wx_queue_stats) / sizeof(u64)))
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#define WX_GLOBAL_STATS_LEN ARRAY_SIZE(wx_gstrings_stats)
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#define WX_FDIR_STATS_LEN ARRAY_SIZE(wx_gstrings_fdir_stats)
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#define WX_RSC_STATS_LEN ARRAY_SIZE(wx_gstrings_rsc_stats)
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#define WX_STATS_LEN (WX_GLOBAL_STATS_LEN + WX_QUEUE_STATS_LEN)
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int wx_get_sset_count(struct net_device *netdev, int sset)
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{
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struct wx *wx = netdev_priv(netdev);
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int len = WX_STATS_LEN;
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switch (sset) {
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case ETH_SS_STATS:
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return (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags)) ?
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WX_STATS_LEN + WX_FDIR_STATS_LEN : WX_STATS_LEN;
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if (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags))
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len += WX_FDIR_STATS_LEN;
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if (test_bit(WX_FLAG_RSC_CAPABLE, wx->flags))
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len += WX_RSC_STATS_LEN;
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return len;
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default:
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return -EOPNOTSUPP;
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}
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@@ -94,6 +104,10 @@ void wx_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
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for (i = 0; i < WX_FDIR_STATS_LEN; i++)
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ethtool_puts(&p, wx_gstrings_fdir_stats[i].stat_string);
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}
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if (test_bit(WX_FLAG_RSC_CAPABLE, wx->flags)) {
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for (i = 0; i < WX_RSC_STATS_LEN; i++)
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ethtool_puts(&p, wx_gstrings_rsc_stats[i].stat_string);
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}
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for (i = 0; i < netdev->num_tx_queues; i++) {
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ethtool_sprintf(&p, "tx_queue_%u_packets", i);
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ethtool_sprintf(&p, "tx_queue_%u_bytes", i);
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@@ -131,6 +145,13 @@ void wx_get_ethtool_stats(struct net_device *netdev,
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}
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}
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if (test_bit(WX_FLAG_RSC_CAPABLE, wx->flags)) {
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for (k = 0; k < WX_RSC_STATS_LEN; k++) {
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p = (char *)wx + wx_gstrings_rsc_stats[k].stat_offset;
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data[i++] = *(u64 *)p;
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}
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}
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for (j = 0; j < netdev->num_tx_queues; j++) {
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ring = wx->tx_ring[j];
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if (!ring) {
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@@ -322,6 +343,40 @@ int wx_get_coalesce(struct net_device *netdev,
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}
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EXPORT_SYMBOL(wx_get_coalesce);
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static void wx_update_rsc(struct wx *wx)
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{
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struct net_device *netdev = wx->netdev;
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bool need_reset = false;
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/* nothing to do if LRO or RSC are not enabled */
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if (!test_bit(WX_FLAG_RSC_CAPABLE, wx->flags) ||
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!(netdev->features & NETIF_F_LRO))
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return;
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/* check the feature flag value and enable RSC if necessary */
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if (wx->rx_itr_setting == 1 ||
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wx->rx_itr_setting > WX_MIN_RSC_ITR) {
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if (!test_bit(WX_FLAG_RSC_ENABLED, wx->flags)) {
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set_bit(WX_FLAG_RSC_ENABLED, wx->flags);
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dev_info(&wx->pdev->dev,
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"rx-usecs value high enough to re-enable RSC\n");
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need_reset = true;
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}
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/* if interrupt rate is too high then disable RSC */
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} else if (test_bit(WX_FLAG_RSC_ENABLED, wx->flags)) {
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clear_bit(WX_FLAG_RSC_ENABLED, wx->flags);
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dev_info(&wx->pdev->dev,
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"rx-usecs set too low, disabling RSC\n");
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need_reset = true;
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}
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/* reset the device to apply the new RSC setting */
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if (need_reset && wx->do_reset)
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wx->do_reset(netdev);
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}
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int wx_set_coalesce(struct net_device *netdev,
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struct ethtool_coalesce *ec,
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struct kernel_ethtool_coalesce *kernel_coal,
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@@ -414,6 +469,8 @@ int wx_set_coalesce(struct net_device *netdev,
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wx_write_eitr(q_vector);
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}
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wx_update_rsc(wx);
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return 0;
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}
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EXPORT_SYMBOL(wx_set_coalesce);
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@@ -1779,7 +1779,9 @@ EXPORT_SYMBOL(wx_set_rx_mode);
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static void wx_set_rx_buffer_len(struct wx *wx)
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{
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struct net_device *netdev = wx->netdev;
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struct wx_ring *rx_ring;
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u32 mhadd, max_frame;
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int i;
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max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
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/* adjust max frame to be at least the size of a standard frame */
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@@ -1789,6 +1791,19 @@ static void wx_set_rx_buffer_len(struct wx *wx)
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mhadd = rd32(wx, WX_PSR_MAX_SZ);
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if (max_frame != mhadd)
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wr32(wx, WX_PSR_MAX_SZ, max_frame);
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/*
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* Setup the HW Rx Head and Tail Descriptor Pointers and
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* the Base and Length of the Rx Descriptor Ring
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*/
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for (i = 0; i < wx->num_rx_queues; i++) {
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rx_ring = wx->rx_ring[i];
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rx_ring->rx_buf_len = WX_RXBUFFER_2K;
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#if (PAGE_SIZE < 8192)
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if (test_bit(WX_FLAG_RSC_ENABLED, wx->flags))
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rx_ring->rx_buf_len = WX_RXBUFFER_3K;
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#endif
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}
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}
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/**
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@@ -1865,11 +1880,27 @@ static void wx_configure_srrctl(struct wx *wx,
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srrctl |= WX_RXBUFFER_256 << WX_PX_RR_CFG_BHDRSIZE_SHIFT;
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/* configure the packet buffer length */
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srrctl |= WX_RX_BUFSZ >> WX_PX_RR_CFG_BSIZEPKT_SHIFT;
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srrctl |= rx_ring->rx_buf_len >> WX_PX_RR_CFG_BSIZEPKT_SHIFT;
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wr32(wx, WX_PX_RR_CFG(reg_idx), srrctl);
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}
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static void wx_configure_rscctl(struct wx *wx,
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struct wx_ring *ring)
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{
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u8 reg_idx = ring->reg_idx;
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u32 rscctrl;
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if (!test_bit(WX_FLAG_RSC_ENABLED, wx->flags))
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return;
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rscctrl = rd32(wx, WX_PX_RR_CFG(reg_idx));
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rscctrl |= WX_PX_RR_CFG_RSC;
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rscctrl |= WX_PX_RR_CFG_MAX_RSCBUF_16;
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wr32(wx, WX_PX_RR_CFG(reg_idx), rscctrl);
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}
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static void wx_configure_tx_ring(struct wx *wx,
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struct wx_ring *ring)
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{
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@@ -1956,6 +1987,7 @@ static void wx_configure_rx_ring(struct wx *wx,
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ring->tail = wx->hw_addr + WX_PX_RR_WP(reg_idx);
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wx_configure_srrctl(wx, ring);
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wx_configure_rscctl(wx, ring);
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/* initialize rx_buffer_info */
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memset(ring->rx_buffer_info, 0,
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@@ -2194,7 +2226,9 @@ void wx_configure_rx(struct wx *wx)
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/* RSC Setup */
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psrctl = rd32(wx, WX_PSR_CTL);
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psrctl |= WX_PSR_CTL_RSC_ACK; /* Disable RSC for ACK packets */
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psrctl |= WX_PSR_CTL_RSC_DIS;
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psrctl &= ~WX_PSR_CTL_RSC_DIS;
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if (!test_bit(WX_FLAG_RSC_ENABLED, wx->flags))
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psrctl |= WX_PSR_CTL_RSC_DIS;
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wr32(wx, WX_PSR_CTL, psrctl);
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}
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@@ -2824,6 +2858,18 @@ void wx_update_stats(struct wx *wx)
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wx->hw_csum_rx_error = hw_csum_rx_error;
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wx->hw_csum_rx_good = hw_csum_rx_good;
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if (test_bit(WX_FLAG_RSC_ENABLED, wx->flags)) {
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u64 rsc_count = 0;
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u64 rsc_flush = 0;
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for (i = 0; i < wx->num_rx_queues; i++) {
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rsc_count += wx->rx_ring[i]->rx_stats.rsc_count;
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rsc_flush += wx->rx_ring[i]->rx_stats.rsc_flush;
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}
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wx->rsc_count = rsc_count;
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wx->rsc_flush = rsc_flush;
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}
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for (i = 0; i < wx->num_tx_queues; i++) {
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struct wx_ring *tx_ring = wx->tx_ring[i];
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@@ -235,7 +235,7 @@ static struct sk_buff *wx_build_skb(struct wx_ring *rx_ring,
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{
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unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
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#if (PAGE_SIZE < 8192)
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unsigned int truesize = WX_RX_BUFSZ;
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unsigned int truesize = wx_rx_pg_size(rx_ring) / 2;
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#else
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unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
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#endif
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@@ -341,7 +341,7 @@ void wx_alloc_rx_buffers(struct wx_ring *rx_ring, u16 cleaned_count)
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/* sync the buffer for use by the device */
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dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
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bi->page_offset,
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WX_RX_BUFSZ,
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rx_ring->rx_buf_len,
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DMA_FROM_DEVICE);
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rx_desc->read.pkt_addr =
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@@ -404,6 +404,7 @@ static bool wx_is_non_eop(struct wx_ring *rx_ring,
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union wx_rx_desc *rx_desc,
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struct sk_buff *skb)
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{
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struct wx *wx = rx_ring->q_vector->wx;
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u32 ntc = rx_ring->next_to_clean + 1;
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/* fetch, update, and store next to clean */
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@@ -412,6 +413,24 @@ static bool wx_is_non_eop(struct wx_ring *rx_ring,
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prefetch(WX_RX_DESC(rx_ring, ntc));
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/* update RSC append count if present */
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if (test_bit(WX_FLAG_RSC_ENABLED, wx->flags)) {
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__le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
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cpu_to_le32(WX_RXD_RSCCNT_MASK);
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if (unlikely(rsc_enabled)) {
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u32 rsc_cnt = le32_to_cpu(rsc_enabled);
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rsc_cnt >>= WX_RXD_RSCCNT_SHIFT;
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WX_CB(skb)->append_cnt += rsc_cnt - 1;
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/* update ntc based on RSC value */
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ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
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ntc &= WX_RXD_NEXTP_MASK;
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ntc >>= WX_RXD_NEXTP_SHIFT;
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}
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}
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/* if we are the last buffer then there is nothing else to do */
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if (likely(wx_test_staterr(rx_desc, WX_RXD_STAT_EOP)))
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return false;
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@@ -582,6 +601,33 @@ static void wx_rx_vlan(struct wx_ring *ring, union wx_rx_desc *rx_desc,
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}
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}
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static void wx_set_rsc_gso_size(struct wx_ring *ring,
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struct sk_buff *skb)
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{
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u16 hdr_len = skb_headlen(skb);
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/* set gso_size to avoid messing up TCP MSS */
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skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
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WX_CB(skb)->append_cnt);
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skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
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}
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static void wx_update_rsc_stats(struct wx_ring *rx_ring,
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struct sk_buff *skb)
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{
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/* if append_cnt is 0 then frame is not RSC */
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if (!WX_CB(skb)->append_cnt)
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return;
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rx_ring->rx_stats.rsc_count += WX_CB(skb)->append_cnt;
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rx_ring->rx_stats.rsc_flush++;
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wx_set_rsc_gso_size(rx_ring, skb);
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/* gso_size is computed using append_cnt so always clear it last */
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WX_CB(skb)->append_cnt = 0;
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}
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/**
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* wx_process_skb_fields - Populate skb header fields from Rx descriptor
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* @rx_ring: rx descriptor ring packet is being transacted on
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@@ -598,6 +644,9 @@ static void wx_process_skb_fields(struct wx_ring *rx_ring,
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{
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struct wx *wx = netdev_priv(rx_ring->netdev);
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if (test_bit(WX_FLAG_RSC_CAPABLE, wx->flags))
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wx_update_rsc_stats(rx_ring, skb);
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wx_rx_hash(rx_ring, rx_desc, skb);
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wx_rx_checksum(rx_ring, rx_desc, skb);
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@@ -2549,7 +2598,7 @@ static void wx_clean_rx_ring(struct wx_ring *rx_ring)
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dma_sync_single_range_for_cpu(rx_ring->dev,
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rx_buffer->dma,
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rx_buffer->page_offset,
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WX_RX_BUFSZ,
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rx_ring->rx_buf_len,
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DMA_FROM_DEVICE);
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/* free resources associated with mapping */
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@@ -2760,13 +2809,14 @@ static int wx_alloc_page_pool(struct wx_ring *rx_ring)
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struct page_pool_params pp_params = {
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.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
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.order = 0,
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.pool_size = rx_ring->count,
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.order = wx_rx_pg_order(rx_ring),
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.pool_size = rx_ring->count * rx_ring->rx_buf_len /
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wx_rx_pg_size(rx_ring),
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.nid = dev_to_node(rx_ring->dev),
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.dev = rx_ring->dev,
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.dma_dir = DMA_FROM_DEVICE,
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.offset = 0,
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.max_len = PAGE_SIZE,
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.max_len = wx_rx_pg_size(rx_ring),
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};
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rx_ring->page_pool = page_pool_create(&pp_params);
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@@ -3075,8 +3125,25 @@ int wx_set_features(struct net_device *netdev, netdev_features_t features)
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else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_FILTER))
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wx_set_rx_mode(netdev);
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if (test_bit(WX_FLAG_RSC_CAPABLE, wx->flags)) {
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if (!(features & NETIF_F_LRO)) {
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if (test_bit(WX_FLAG_RSC_ENABLED, wx->flags))
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need_reset = true;
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clear_bit(WX_FLAG_RSC_ENABLED, wx->flags);
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} else if (!(test_bit(WX_FLAG_RSC_ENABLED, wx->flags))) {
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if (wx->rx_itr_setting == 1 ||
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wx->rx_itr_setting > WX_MIN_RSC_ITR) {
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set_bit(WX_FLAG_RSC_ENABLED, wx->flags);
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need_reset = true;
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} else if (changed & NETIF_F_LRO) {
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dev_info(&wx->pdev->dev,
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"rx-usecs set too low, disable RSC\n");
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}
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}
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}
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if (!(test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags)))
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return 0;
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goto out;
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/* Check if Flow Director n-tuple support was enabled or disabled. If
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* the state changed, we need to reset.
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@@ -3102,6 +3169,7 @@ int wx_set_features(struct net_device *netdev, netdev_features_t features)
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break;
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}
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out:
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if (need_reset && wx->do_reset)
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wx->do_reset(netdev);
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@@ -3151,6 +3219,14 @@ netdev_features_t wx_fix_features(struct net_device *netdev,
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}
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}
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/* If Rx checksum is disabled, then RSC/LRO should also be disabled */
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if (!(features & NETIF_F_RXCSUM))
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features &= ~NETIF_F_LRO;
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/* Turn off LRO if not RSC capable */
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if (!test_bit(WX_FLAG_RSC_CAPABLE, wx->flags))
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features &= ~NETIF_F_LRO;
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return features;
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}
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EXPORT_SYMBOL(wx_fix_features);
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@@ -122,6 +122,10 @@ static int __wx_enable_sriov(struct wx *wx, u8 num_vfs)
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WX_CFG_PORT_CTL_NUM_VT_MASK,
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value);
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/* Disable RSC when in SR-IOV mode */
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clear_bit(WX_FLAG_RSC_CAPABLE, wx->flags);
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clear_bit(WX_FLAG_RSC_ENABLED, wx->flags);
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return ret;
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}
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@@ -424,6 +424,7 @@ enum WX_MSCA_CMD_value {
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#define WX_7K_ITR 595
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#define WX_12K_ITR 336
|
||||
#define WX_20K_ITR 200
|
||||
#define WX_MIN_RSC_ITR 24
|
||||
#define WX_SP_MAX_EITR 0x00000FF8U
|
||||
#define WX_AML_MAX_EITR 0x00000FFFU
|
||||
#define WX_EM_MAX_EITR 0x00007FFCU
|
||||
@@ -454,7 +455,9 @@ enum WX_MSCA_CMD_value {
|
||||
/* PX_RR_CFG bit definitions */
|
||||
#define WX_PX_RR_CFG_VLAN BIT(31)
|
||||
#define WX_PX_RR_CFG_DROP_EN BIT(30)
|
||||
#define WX_PX_RR_CFG_RSC BIT(29)
|
||||
#define WX_PX_RR_CFG_SPLIT_MODE BIT(26)
|
||||
#define WX_PX_RR_CFG_MAX_RSCBUF_16 FIELD_PREP(GENMASK(24, 23), 3)
|
||||
#define WX_PX_RR_CFG_DESC_MERGE BIT(19)
|
||||
#define WX_PX_RR_CFG_RR_THER_SHIFT 16
|
||||
#define WX_PX_RR_CFG_RR_HDR_SZ GENMASK(15, 12)
|
||||
@@ -551,14 +554,9 @@ enum WX_MSCA_CMD_value {
|
||||
/* Supported Rx Buffer Sizes */
|
||||
#define WX_RXBUFFER_256 256 /* Used for skb receive header */
|
||||
#define WX_RXBUFFER_2K 2048
|
||||
#define WX_RXBUFFER_3K 3072
|
||||
#define WX_MAX_RXBUFFER 16384 /* largest size for single descriptor */
|
||||
|
||||
#if MAX_SKB_FRAGS < 8
|
||||
#define WX_RX_BUFSZ ALIGN(WX_MAX_RXBUFFER / MAX_SKB_FRAGS, 1024)
|
||||
#else
|
||||
#define WX_RX_BUFSZ WX_RXBUFFER_2K
|
||||
#endif
|
||||
|
||||
#define WX_RX_BUFFER_WRITE 16 /* Must be power of 2 */
|
||||
|
||||
#define WX_MAX_DATA_PER_TXD BIT(14)
|
||||
@@ -652,6 +650,12 @@ enum wx_l2_ptypes {
|
||||
|
||||
#define WX_RXD_PKTTYPE(_rxd) \
|
||||
((le32_to_cpu((_rxd)->wb.lower.lo_dword.data) >> 9) & 0xFF)
|
||||
|
||||
#define WX_RXD_RSCCNT_MASK GENMASK(20, 17)
|
||||
#define WX_RXD_RSCCNT_SHIFT 17
|
||||
#define WX_RXD_NEXTP_MASK GENMASK(19, 4)
|
||||
#define WX_RXD_NEXTP_SHIFT 4
|
||||
|
||||
/*********************** Transmit Descriptor Config Masks ****************/
|
||||
#define WX_TXD_STAT_DD BIT(0) /* Descriptor Done */
|
||||
#define WX_TXD_DTYP_DATA 0 /* Adv Data Descriptor */
|
||||
@@ -1039,6 +1043,8 @@ struct wx_rx_queue_stats {
|
||||
u64 csum_good_cnt;
|
||||
u64 csum_err;
|
||||
u64 alloc_rx_buff_failed;
|
||||
u64 rsc_count;
|
||||
u64 rsc_flush;
|
||||
};
|
||||
|
||||
/* iterator for handling rings in ring container */
|
||||
@@ -1081,6 +1087,7 @@ struct wx_ring {
|
||||
*/
|
||||
u16 next_to_use;
|
||||
u16 next_to_clean;
|
||||
u16 rx_buf_len;
|
||||
union {
|
||||
u16 next_to_alloc;
|
||||
struct {
|
||||
@@ -1237,6 +1244,7 @@ enum wx_pf_flags {
|
||||
WX_FLAG_FDIR_HASH,
|
||||
WX_FLAG_FDIR_PERFECT,
|
||||
WX_FLAG_RSC_CAPABLE,
|
||||
WX_FLAG_RSC_ENABLED,
|
||||
WX_FLAG_RX_HWTSTAMP_ENABLED,
|
||||
WX_FLAG_RX_HWTSTAMP_IN_REGISTER,
|
||||
WX_FLAG_PTP_PPS_ENABLED,
|
||||
@@ -1352,6 +1360,8 @@ struct wx {
|
||||
u64 hw_csum_rx_good;
|
||||
u64 hw_csum_rx_error;
|
||||
u64 alloc_rx_buff_failed;
|
||||
u64 rsc_count;
|
||||
u64 rsc_flush;
|
||||
unsigned int num_vfs;
|
||||
struct vf_data_storage *vfinfo;
|
||||
struct vf_macvlans vf_mvs;
|
||||
@@ -1483,4 +1493,15 @@ static inline int wx_set_state_reset(struct wx *wx)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline unsigned int wx_rx_pg_order(struct wx_ring *ring)
|
||||
{
|
||||
#if (PAGE_SIZE < 8192)
|
||||
if (ring->rx_buf_len == WX_RXBUFFER_3K)
|
||||
return 1;
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define wx_rx_pg_size(_ring) (PAGE_SIZE << wx_rx_pg_order(_ring))
|
||||
|
||||
#endif /* _WX_TYPE_H_ */
|
||||
|
||||
@@ -398,6 +398,7 @@ static int txgbe_sw_init(struct wx *wx)
|
||||
wx->configure_fdir = txgbe_configure_fdir;
|
||||
|
||||
set_bit(WX_FLAG_RSC_CAPABLE, wx->flags);
|
||||
set_bit(WX_FLAG_RSC_ENABLED, wx->flags);
|
||||
set_bit(WX_FLAG_MULTI_64_FUNC, wx->flags);
|
||||
|
||||
/* enable itr by default in dynamic mode */
|
||||
@@ -803,6 +804,8 @@ static int txgbe_probe(struct pci_dev *pdev,
|
||||
netdev->features |= NETIF_F_HIGHDMA;
|
||||
netdev->hw_features |= NETIF_F_GRO;
|
||||
netdev->features |= NETIF_F_GRO;
|
||||
netdev->hw_features |= NETIF_F_LRO;
|
||||
netdev->features |= NETIF_F_LRO;
|
||||
netdev->features |= NETIF_F_RX_UDP_TUNNEL_PORT;
|
||||
|
||||
netdev->priv_flags |= IFF_UNICAST_FLT;
|
||||
|
||||
Reference in New Issue
Block a user