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Merge tag 'renesas-clk-for-v6.11-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven: - Remove obsolete clock DT binding header files - Add Battery Backup (VBATTB) and I2C clocks, resets, and power domains on RZ/G3S - Add audio clocks on R-Car V4M - Add video capture (ISPCS, CSI-2, VIN) clocks on R-Car V4M - Miscellaneous fixes and improvements * tag 'renesas-clk-for-v6.11-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r9a08g045: Add clock, reset and power domain support for I2C clk: renesas: r8a779h0: Add Audio clocks clk: renesas: r9a08g045: Add clock, reset and power domain support for the VBATTB IP dt-bindings: clock: rcar-gen2: Remove obsolete header files dt-bindings: clock: r8a7779: Remove duplicate newline clk: renesas: Drop "Renesas" from individual driver descriptions clk: renesas: r8a779h0: Fix PLL2/PLL4 multipliers in comments clk: renesas: r8a779h0: Add VIN clocks dt-bindings: clock: renesas,rzg2l-cpg: Update description for #reset-cells clk: renesas: rcar-gen2: Use DEFINE_SPINLOCK() for static spinlock clk: renesas: cpg-lib: Use DEFINE_SPINLOCK() for global spinlock clk: renesas: r8a77970: Use common cpg_lock clk: renesas: r8a779h0: Add CSI-2 clocks clk: renesas: r8a779h0: Add ISPCS clocks
This commit is contained in:
Stephen Boyd
@@ -62,7 +62,7 @@ properties:
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'#reset-cells':
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description:
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The single reset specifier cell must be the module number, as defined in
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The single reset specifier cell must be the reset number, as defined in
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<dt-bindings/clock/r9a0*-cpg.h>.
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const: 1
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@@ -218,14 +218,14 @@ config CLK_RCAR_GEN4_CPG
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select CLK_RENESAS_CPG_MSSR
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config CLK_RCAR_USB2_CLOCK_SEL
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bool "Renesas R-Car USB2 clock selector support"
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bool "R-Car USB2 clock selector support"
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depends on ARCH_RENESAS || COMPILE_TEST
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select RESET_CONTROLLER
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help
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This is a driver for R-Car USB2 clock selector
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config CLK_RZG2L
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bool "Renesas RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST
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bool "RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST
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select RESET_CONTROLLER
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# Generic
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@@ -18,6 +18,7 @@
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#include <dt-bindings/clock/r8a77970-cpg-mssr.h>
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#include "renesas-cpg-mssr.h"
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#include "rcar-cpg-lib.h"
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#include "rcar-gen3-cpg.h"
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#define CPG_SD0CKCR 0x0074
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@@ -47,8 +48,6 @@ enum clk_ids {
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MOD_CLK_BASE
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};
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static spinlock_t cpg_lock;
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static const struct clk_div_table cpg_sd0h_div_table[] = {
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{ 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
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{ 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
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@@ -213,8 +212,6 @@ static int __init r8a77970_cpg_mssr_init(struct device *dev)
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if (error)
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return error;
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spin_lock_init(&cpg_lock);
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cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
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return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
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@@ -176,6 +176,8 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
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DEF_MOD("avb0:rgmii0", 211, R8A779H0_CLK_S0D8_HSC),
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DEF_MOD("avb1:rgmii1", 212, R8A779H0_CLK_S0D8_HSC),
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DEF_MOD("avb2:rgmii2", 213, R8A779H0_CLK_S0D8_HSC),
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DEF_MOD("csi40", 331, R8A779H0_CLK_CSI),
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DEF_MOD("csi41", 400, R8A779H0_CLK_CSI),
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DEF_MOD("hscif0", 514, R8A779H0_CLK_SASYNCPERD1),
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DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1),
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DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1),
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@@ -185,6 +187,8 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
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DEF_MOD("i2c2", 520, R8A779H0_CLK_S0D6_PER),
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DEF_MOD("i2c3", 521, R8A779H0_CLK_S0D6_PER),
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DEF_MOD("irqc", 611, R8A779H0_CLK_CL16M),
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DEF_MOD("ispcs0", 612, R8A779H0_CLK_S0D2_VIO),
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DEF_MOD("ispcs1", 613, R8A779H0_CLK_S0D2_VIO),
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DEF_MOD("msi0", 618, R8A779H0_CLK_MSO),
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DEF_MOD("msi1", 619, R8A779H0_CLK_MSO),
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DEF_MOD("msi2", 620, R8A779H0_CLK_MSO),
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@@ -204,6 +208,22 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
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DEF_MOD("tmu2", 715, R8A779H0_CLK_SASYNCPERD2),
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DEF_MOD("tmu3", 716, R8A779H0_CLK_SASYNCPERD2),
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DEF_MOD("tmu4", 717, R8A779H0_CLK_SASYNCPERD2),
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DEF_MOD("vin00", 730, R8A779H0_CLK_S0D4_VIO),
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DEF_MOD("vin01", 731, R8A779H0_CLK_S0D4_VIO),
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DEF_MOD("vin02", 800, R8A779H0_CLK_S0D4_VIO),
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DEF_MOD("vin03", 801, R8A779H0_CLK_S0D4_VIO),
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DEF_MOD("vin04", 802, R8A779H0_CLK_S0D4_VIO),
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DEF_MOD("vin05", 803, R8A779H0_CLK_S0D4_VIO),
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DEF_MOD("vin06", 804, R8A779H0_CLK_S0D4_VIO),
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DEF_MOD("vin07", 805, R8A779H0_CLK_S0D4_VIO),
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DEF_MOD("vin10", 806, R8A779H0_CLK_S0D4_VIO),
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DEF_MOD("vin11", 807, R8A779H0_CLK_S0D4_VIO),
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DEF_MOD("vin12", 808, R8A779H0_CLK_S0D4_VIO),
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DEF_MOD("vin13", 809, R8A779H0_CLK_S0D4_VIO),
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DEF_MOD("vin14", 810, R8A779H0_CLK_S0D4_VIO),
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DEF_MOD("vin15", 811, R8A779H0_CLK_S0D4_VIO),
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DEF_MOD("vin16", 812, R8A779H0_CLK_S0D4_VIO),
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DEF_MOD("vin17", 813, R8A779H0_CLK_S0D4_VIO),
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DEF_MOD("wdt1:wdt0", 907, R8A779H0_CLK_R),
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DEF_MOD("cmt0", 910, R8A779H0_CLK_R),
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DEF_MOD("cmt1", 911, R8A779H0_CLK_R),
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@@ -213,6 +233,8 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
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DEF_MOD("pfc1", 916, R8A779H0_CLK_CP),
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DEF_MOD("pfc2", 917, R8A779H0_CLK_CP),
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DEF_MOD("tsc2:tsc1", 919, R8A779H0_CLK_CL16M),
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DEF_MOD("ssiu", 2926, R8A779H0_CLK_S0D6_PER),
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DEF_MOD("ssi", 2927, R8A779H0_CLK_S0D6_PER),
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};
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/*
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@@ -222,10 +244,10 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
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* MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
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* 14 13 (MHz)
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* ------------------------------------------------------------------------
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* 0 0 16.66 / 1 x192 x204 x192 x144 x192 x168 /16
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* 0 1 20 / 1 x160 x170 x160 x120 x160 x140 /19
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* 0 0 16.66 / 1 x192 x240 x192 x240 x192 x168 /16
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* 0 1 20 / 1 x160 x200 x160 x200 x160 x140 /19
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* 1 0 Prohibited setting
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* 1 1 33.33 / 2 x192 x204 x192 x144 x192 x168 /32
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* 1 1 33.33 / 2 x192 x240 x192 x240 x192 x168 /32
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*/
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#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
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(((md) & BIT(13)) >> 13))
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@@ -213,8 +213,13 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
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DEF_COUPLED("eth1_axi", R9A08G045_ETH1_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 1),
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DEF_COUPLED("eth1_chi", R9A08G045_ETH1_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 1),
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DEF_MOD("eth1_refclk", R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9),
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DEF_MOD("i2c0_pclk", R9A08G045_I2C0_PCLK, R9A08G045_CLK_P0, 0x580, 0),
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DEF_MOD("i2c1_pclk", R9A08G045_I2C1_PCLK, R9A08G045_CLK_P0, 0x580, 1),
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DEF_MOD("i2c2_pclk", R9A08G045_I2C2_PCLK, R9A08G045_CLK_P0, 0x580, 2),
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DEF_MOD("i2c3_pclk", R9A08G045_I2C3_PCLK, R9A08G045_CLK_P0, 0x580, 3),
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DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0),
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DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0),
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DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0),
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};
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static const struct rzg2l_reset r9a08g045_resets[] = {
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@@ -227,10 +232,15 @@ static const struct rzg2l_reset r9a08g045_resets[] = {
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DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2),
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DEF_RST(R9A08G045_ETH0_RST_HW_N, 0x87c, 0),
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DEF_RST(R9A08G045_ETH1_RST_HW_N, 0x87c, 1),
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DEF_RST(R9A08G045_I2C0_MRST, 0x880, 0),
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DEF_RST(R9A08G045_I2C1_MRST, 0x880, 1),
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DEF_RST(R9A08G045_I2C2_MRST, 0x880, 2),
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DEF_RST(R9A08G045_I2C3_MRST, 0x880, 3),
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DEF_RST(R9A08G045_SCIF0_RST_SYSTEM_N, 0x884, 0),
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DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0),
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DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1),
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DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2),
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DEF_RST(R9A08G045_VBAT_BRESETN, 0x914, 0),
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};
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static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
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@@ -238,6 +248,7 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
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MOD_CLK_BASE + R9A08G045_IA55_PCLK,
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MOD_CLK_BASE + R9A08G045_IA55_CLK,
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MOD_CLK_BASE + R9A08G045_DMAC_ACLK,
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MOD_CLK_BASE + R9A08G045_VBAT_BCLK,
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};
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static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
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@@ -272,9 +283,24 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
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DEF_PD("eth1", R9A08G045_PD_ETHER1,
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DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(3)),
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RZG2L_PD_F_NONE),
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DEF_PD("i2c0", R9A08G045_PD_I2C0,
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DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(10)),
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RZG2L_PD_F_NONE),
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DEF_PD("i2c1", R9A08G045_PD_I2C1,
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DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(11)),
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RZG2L_PD_F_NONE),
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DEF_PD("i2c2", R9A08G045_PD_I2C2,
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DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(12)),
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RZG2L_PD_F_NONE),
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DEF_PD("i2c3", R9A08G045_PD_I2C3,
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DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(13)),
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RZG2L_PD_F_NONE),
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DEF_PD("scif0", R9A08G045_PD_SCIF0,
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DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)),
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RZG2L_PD_F_NONE),
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DEF_PD("vbat", R9A08G045_PD_VBAT,
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DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)),
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RZG2L_PD_F_ALWAYS_ON),
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};
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const struct rzg2l_cpg_info r9a08g045_cpg_info = {
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@@ -22,7 +22,7 @@
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#include "rcar-cpg-lib.h"
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spinlock_t cpg_lock;
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DEFINE_SPINLOCK(cpg_lock);
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void cpg_reg_modify(void __iomem *reg, u32 clear, u32 set)
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{
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@@ -30,7 +30,7 @@
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#define CPG_ADSPCKCR 0x025c
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#define CPG_RCANCKCR 0x0270
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static spinlock_t cpg_lock;
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static DEFINE_SPINLOCK(cpg_lock);
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/*
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* Z Clock
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@@ -387,7 +387,5 @@ int __init rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config,
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cpg_quirks = (uintptr_t)attr->data;
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pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks);
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spin_lock_init(&cpg_lock);
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return 0;
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}
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@@ -551,7 +551,5 @@ int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
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cpg_quirks = (uintptr_t)attr->data;
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pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks);
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spin_lock_init(&cpg_lock);
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return 0;
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}
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@@ -466,7 +466,5 @@ int __init rcar_gen4_cpg_init(const struct rcar_gen4_cpg_pll_config *config,
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cpg_clk_extalr = clk_extalr;
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cpg_mode = mode;
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spin_lock_init(&cpg_lock);
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return 0;
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}
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@@ -57,5 +57,4 @@
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#define R8A7779_CLK_MMC1 30
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#define R8A7779_CLK_MMC0 31
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#endif /* __DT_BINDINGS_CLOCK_R8A7779_H__ */
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@@ -1,158 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright 2013 Ideas On Board SPRL
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*/
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#ifndef __DT_BINDINGS_CLOCK_R8A7790_H__
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#define __DT_BINDINGS_CLOCK_R8A7790_H__
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/* CPG */
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#define R8A7790_CLK_MAIN 0
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#define R8A7790_CLK_PLL0 1
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#define R8A7790_CLK_PLL1 2
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#define R8A7790_CLK_PLL3 3
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#define R8A7790_CLK_LB 4
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#define R8A7790_CLK_QSPI 5
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#define R8A7790_CLK_SDH 6
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#define R8A7790_CLK_SD0 7
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#define R8A7790_CLK_SD1 8
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#define R8A7790_CLK_Z 9
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#define R8A7790_CLK_RCAN 10
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#define R8A7790_CLK_ADSP 11
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/* MSTP0 */
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#define R8A7790_CLK_MSIOF0 0
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/* MSTP1 */
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#define R8A7790_CLK_VCP1 0
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#define R8A7790_CLK_VCP0 1
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#define R8A7790_CLK_VPC1 2
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#define R8A7790_CLK_VPC0 3
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#define R8A7790_CLK_JPU 6
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#define R8A7790_CLK_SSP1 9
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#define R8A7790_CLK_TMU1 11
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#define R8A7790_CLK_3DG 12
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#define R8A7790_CLK_2DDMAC 15
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#define R8A7790_CLK_FDP1_2 17
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#define R8A7790_CLK_FDP1_1 18
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#define R8A7790_CLK_FDP1_0 19
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#define R8A7790_CLK_TMU3 21
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#define R8A7790_CLK_TMU2 22
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#define R8A7790_CLK_CMT0 24
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#define R8A7790_CLK_TMU0 25
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#define R8A7790_CLK_VSP1_DU1 27
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#define R8A7790_CLK_VSP1_DU0 28
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#define R8A7790_CLK_VSP1_R 30
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#define R8A7790_CLK_VSP1_S 31
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/* MSTP2 */
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#define R8A7790_CLK_SCIFA2 2
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#define R8A7790_CLK_SCIFA1 3
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#define R8A7790_CLK_SCIFA0 4
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#define R8A7790_CLK_MSIOF2 5
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#define R8A7790_CLK_SCIFB0 6
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#define R8A7790_CLK_SCIFB1 7
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#define R8A7790_CLK_MSIOF1 8
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#define R8A7790_CLK_MSIOF3 15
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#define R8A7790_CLK_SCIFB2 16
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#define R8A7790_CLK_SYS_DMAC1 18
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#define R8A7790_CLK_SYS_DMAC0 19
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/* MSTP3 */
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#define R8A7790_CLK_IIC2 0
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#define R8A7790_CLK_TPU0 4
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#define R8A7790_CLK_MMCIF1 5
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#define R8A7790_CLK_SCIF2 10
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#define R8A7790_CLK_SDHI3 11
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#define R8A7790_CLK_SDHI2 12
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#define R8A7790_CLK_SDHI1 13
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#define R8A7790_CLK_SDHI0 14
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#define R8A7790_CLK_MMCIF0 15
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#define R8A7790_CLK_IIC0 18
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#define R8A7790_CLK_PCIEC 19
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#define R8A7790_CLK_IIC1 23
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#define R8A7790_CLK_SSUSB 28
|
||||
#define R8A7790_CLK_CMT1 29
|
||||
#define R8A7790_CLK_USBDMAC0 30
|
||||
#define R8A7790_CLK_USBDMAC1 31
|
||||
|
||||
/* MSTP4 */
|
||||
#define R8A7790_CLK_IRQC 7
|
||||
#define R8A7790_CLK_INTC_SYS 8
|
||||
|
||||
/* MSTP5 */
|
||||
#define R8A7790_CLK_AUDIO_DMAC1 1
|
||||
#define R8A7790_CLK_AUDIO_DMAC0 2
|
||||
#define R8A7790_CLK_ADSP_MOD 6
|
||||
#define R8A7790_CLK_THERMAL 22
|
||||
#define R8A7790_CLK_PWM 23
|
||||
|
||||
/* MSTP7 */
|
||||
#define R8A7790_CLK_EHCI 3
|
||||
#define R8A7790_CLK_HSUSB 4
|
||||
#define R8A7790_CLK_HSCIF1 16
|
||||
#define R8A7790_CLK_HSCIF0 17
|
||||
#define R8A7790_CLK_SCIF1 20
|
||||
#define R8A7790_CLK_SCIF0 21
|
||||
#define R8A7790_CLK_DU2 22
|
||||
#define R8A7790_CLK_DU1 23
|
||||
#define R8A7790_CLK_DU0 24
|
||||
#define R8A7790_CLK_LVDS1 25
|
||||
#define R8A7790_CLK_LVDS0 26
|
||||
|
||||
/* MSTP8 */
|
||||
#define R8A7790_CLK_MLB 2
|
||||
#define R8A7790_CLK_VIN3 8
|
||||
#define R8A7790_CLK_VIN2 9
|
||||
#define R8A7790_CLK_VIN1 10
|
||||
#define R8A7790_CLK_VIN0 11
|
||||
#define R8A7790_CLK_ETHERAVB 12
|
||||
#define R8A7790_CLK_ETHER 13
|
||||
#define R8A7790_CLK_SATA1 14
|
||||
#define R8A7790_CLK_SATA0 15
|
||||
|
||||
/* MSTP9 */
|
||||
#define R8A7790_CLK_GPIO5 7
|
||||
#define R8A7790_CLK_GPIO4 8
|
||||
#define R8A7790_CLK_GPIO3 9
|
||||
#define R8A7790_CLK_GPIO2 10
|
||||
#define R8A7790_CLK_GPIO1 11
|
||||
#define R8A7790_CLK_GPIO0 12
|
||||
#define R8A7790_CLK_RCAN1 15
|
||||
#define R8A7790_CLK_RCAN0 16
|
||||
#define R8A7790_CLK_QSPI_MOD 17
|
||||
#define R8A7790_CLK_IICDVFS 26
|
||||
#define R8A7790_CLK_I2C3 28
|
||||
#define R8A7790_CLK_I2C2 29
|
||||
#define R8A7790_CLK_I2C1 30
|
||||
#define R8A7790_CLK_I2C0 31
|
||||
|
||||
/* MSTP10 */
|
||||
#define R8A7790_CLK_SSI_ALL 5
|
||||
#define R8A7790_CLK_SSI9 6
|
||||
#define R8A7790_CLK_SSI8 7
|
||||
#define R8A7790_CLK_SSI7 8
|
||||
#define R8A7790_CLK_SSI6 9
|
||||
#define R8A7790_CLK_SSI5 10
|
||||
#define R8A7790_CLK_SSI4 11
|
||||
#define R8A7790_CLK_SSI3 12
|
||||
#define R8A7790_CLK_SSI2 13
|
||||
#define R8A7790_CLK_SSI1 14
|
||||
#define R8A7790_CLK_SSI0 15
|
||||
#define R8A7790_CLK_SCU_ALL 17
|
||||
#define R8A7790_CLK_SCU_DVC1 18
|
||||
#define R8A7790_CLK_SCU_DVC0 19
|
||||
#define R8A7790_CLK_SCU_CTU1_MIX1 20
|
||||
#define R8A7790_CLK_SCU_CTU0_MIX0 21
|
||||
#define R8A7790_CLK_SCU_SRC9 22
|
||||
#define R8A7790_CLK_SCU_SRC8 23
|
||||
#define R8A7790_CLK_SCU_SRC7 24
|
||||
#define R8A7790_CLK_SCU_SRC6 25
|
||||
#define R8A7790_CLK_SCU_SRC5 26
|
||||
#define R8A7790_CLK_SCU_SRC4 27
|
||||
#define R8A7790_CLK_SCU_SRC3 28
|
||||
#define R8A7790_CLK_SCU_SRC2 29
|
||||
#define R8A7790_CLK_SCU_SRC1 30
|
||||
#define R8A7790_CLK_SCU_SRC0 31
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */
|
||||
@@ -1,161 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* Copyright 2013 Ideas On Board SPRL
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7791_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A7791_H__
|
||||
|
||||
/* CPG */
|
||||
#define R8A7791_CLK_MAIN 0
|
||||
#define R8A7791_CLK_PLL0 1
|
||||
#define R8A7791_CLK_PLL1 2
|
||||
#define R8A7791_CLK_PLL3 3
|
||||
#define R8A7791_CLK_LB 4
|
||||
#define R8A7791_CLK_QSPI 5
|
||||
#define R8A7791_CLK_SDH 6
|
||||
#define R8A7791_CLK_SD0 7
|
||||
#define R8A7791_CLK_Z 8
|
||||
#define R8A7791_CLK_RCAN 9
|
||||
#define R8A7791_CLK_ADSP 10
|
||||
|
||||
/* MSTP0 */
|
||||
#define R8A7791_CLK_MSIOF0 0
|
||||
|
||||
/* MSTP1 */
|
||||
#define R8A7791_CLK_VCP0 1
|
||||
#define R8A7791_CLK_VPC0 3
|
||||
#define R8A7791_CLK_JPU 6
|
||||
#define R8A7791_CLK_SSP1 9
|
||||
#define R8A7791_CLK_TMU1 11
|
||||
#define R8A7791_CLK_3DG 12
|
||||
#define R8A7791_CLK_2DDMAC 15
|
||||
#define R8A7791_CLK_FDP1_1 18
|
||||
#define R8A7791_CLK_FDP1_0 19
|
||||
#define R8A7791_CLK_TMU3 21
|
||||
#define R8A7791_CLK_TMU2 22
|
||||
#define R8A7791_CLK_CMT0 24
|
||||
#define R8A7791_CLK_TMU0 25
|
||||
#define R8A7791_CLK_VSP1_DU1 27
|
||||
#define R8A7791_CLK_VSP1_DU0 28
|
||||
#define R8A7791_CLK_VSP1_S 31
|
||||
|
||||
/* MSTP2 */
|
||||
#define R8A7791_CLK_SCIFA2 2
|
||||
#define R8A7791_CLK_SCIFA1 3
|
||||
#define R8A7791_CLK_SCIFA0 4
|
||||
#define R8A7791_CLK_MSIOF2 5
|
||||
#define R8A7791_CLK_SCIFB0 6
|
||||
#define R8A7791_CLK_SCIFB1 7
|
||||
#define R8A7791_CLK_MSIOF1 8
|
||||
#define R8A7791_CLK_SCIFB2 16
|
||||
#define R8A7791_CLK_SYS_DMAC1 18
|
||||
#define R8A7791_CLK_SYS_DMAC0 19
|
||||
|
||||
/* MSTP3 */
|
||||
#define R8A7791_CLK_TPU0 4
|
||||
#define R8A7791_CLK_SDHI2 11
|
||||
#define R8A7791_CLK_SDHI1 12
|
||||
#define R8A7791_CLK_SDHI0 14
|
||||
#define R8A7791_CLK_MMCIF0 15
|
||||
#define R8A7791_CLK_IIC0 18
|
||||
#define R8A7791_CLK_PCIEC 19
|
||||
#define R8A7791_CLK_IIC1 23
|
||||
#define R8A7791_CLK_SSUSB 28
|
||||
#define R8A7791_CLK_CMT1 29
|
||||
#define R8A7791_CLK_USBDMAC0 30
|
||||
#define R8A7791_CLK_USBDMAC1 31
|
||||
|
||||
/* MSTP4 */
|
||||
#define R8A7791_CLK_IRQC 7
|
||||
#define R8A7791_CLK_INTC_SYS 8
|
||||
|
||||
/* MSTP5 */
|
||||
#define R8A7791_CLK_AUDIO_DMAC1 1
|
||||
#define R8A7791_CLK_AUDIO_DMAC0 2
|
||||
#define R8A7791_CLK_ADSP_MOD 6
|
||||
#define R8A7791_CLK_THERMAL 22
|
||||
#define R8A7791_CLK_PWM 23
|
||||
|
||||
/* MSTP7 */
|
||||
#define R8A7791_CLK_EHCI 3
|
||||
#define R8A7791_CLK_HSUSB 4
|
||||
#define R8A7791_CLK_HSCIF2 13
|
||||
#define R8A7791_CLK_SCIF5 14
|
||||
#define R8A7791_CLK_SCIF4 15
|
||||
#define R8A7791_CLK_HSCIF1 16
|
||||
#define R8A7791_CLK_HSCIF0 17
|
||||
#define R8A7791_CLK_SCIF3 18
|
||||
#define R8A7791_CLK_SCIF2 19
|
||||
#define R8A7791_CLK_SCIF1 20
|
||||
#define R8A7791_CLK_SCIF0 21
|
||||
#define R8A7791_CLK_DU1 23
|
||||
#define R8A7791_CLK_DU0 24
|
||||
#define R8A7791_CLK_LVDS0 26
|
||||
|
||||
/* MSTP8 */
|
||||
#define R8A7791_CLK_IPMMU_SGX 0
|
||||
#define R8A7791_CLK_MLB 2
|
||||
#define R8A7791_CLK_VIN2 9
|
||||
#define R8A7791_CLK_VIN1 10
|
||||
#define R8A7791_CLK_VIN0 11
|
||||
#define R8A7791_CLK_ETHERAVB 12
|
||||
#define R8A7791_CLK_ETHER 13
|
||||
#define R8A7791_CLK_SATA1 14
|
||||
#define R8A7791_CLK_SATA0 15
|
||||
|
||||
/* MSTP9 */
|
||||
#define R8A7791_CLK_GYROADC 1
|
||||
#define R8A7791_CLK_GPIO7 4
|
||||
#define R8A7791_CLK_GPIO6 5
|
||||
#define R8A7791_CLK_GPIO5 7
|
||||
#define R8A7791_CLK_GPIO4 8
|
||||
#define R8A7791_CLK_GPIO3 9
|
||||
#define R8A7791_CLK_GPIO2 10
|
||||
#define R8A7791_CLK_GPIO1 11
|
||||
#define R8A7791_CLK_GPIO0 12
|
||||
#define R8A7791_CLK_RCAN1 15
|
||||
#define R8A7791_CLK_RCAN0 16
|
||||
#define R8A7791_CLK_QSPI_MOD 17
|
||||
#define R8A7791_CLK_I2C5 25
|
||||
#define R8A7791_CLK_IICDVFS 26
|
||||
#define R8A7791_CLK_I2C4 27
|
||||
#define R8A7791_CLK_I2C3 28
|
||||
#define R8A7791_CLK_I2C2 29
|
||||
#define R8A7791_CLK_I2C1 30
|
||||
#define R8A7791_CLK_I2C0 31
|
||||
|
||||
/* MSTP10 */
|
||||
#define R8A7791_CLK_SSI_ALL 5
|
||||
#define R8A7791_CLK_SSI9 6
|
||||
#define R8A7791_CLK_SSI8 7
|
||||
#define R8A7791_CLK_SSI7 8
|
||||
#define R8A7791_CLK_SSI6 9
|
||||
#define R8A7791_CLK_SSI5 10
|
||||
#define R8A7791_CLK_SSI4 11
|
||||
#define R8A7791_CLK_SSI3 12
|
||||
#define R8A7791_CLK_SSI2 13
|
||||
#define R8A7791_CLK_SSI1 14
|
||||
#define R8A7791_CLK_SSI0 15
|
||||
#define R8A7791_CLK_SCU_ALL 17
|
||||
#define R8A7791_CLK_SCU_DVC1 18
|
||||
#define R8A7791_CLK_SCU_DVC0 19
|
||||
#define R8A7791_CLK_SCU_CTU1_MIX1 20
|
||||
#define R8A7791_CLK_SCU_CTU0_MIX0 21
|
||||
#define R8A7791_CLK_SCU_SRC9 22
|
||||
#define R8A7791_CLK_SCU_SRC8 23
|
||||
#define R8A7791_CLK_SCU_SRC7 24
|
||||
#define R8A7791_CLK_SCU_SRC6 25
|
||||
#define R8A7791_CLK_SCU_SRC5 26
|
||||
#define R8A7791_CLK_SCU_SRC4 27
|
||||
#define R8A7791_CLK_SCU_SRC3 28
|
||||
#define R8A7791_CLK_SCU_SRC2 29
|
||||
#define R8A7791_CLK_SCU_SRC1 30
|
||||
#define R8A7791_CLK_SCU_SRC0 31
|
||||
|
||||
/* MSTP11 */
|
||||
#define R8A7791_CLK_SCIFA3 6
|
||||
#define R8A7791_CLK_SCIFA4 7
|
||||
#define R8A7791_CLK_SCIFA5 8
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A7791_H__ */
|
||||
@@ -1,98 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* Copyright (C) 2016 Cogent Embedded, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7792_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A7792_H__
|
||||
|
||||
/* CPG */
|
||||
#define R8A7792_CLK_MAIN 0
|
||||
#define R8A7792_CLK_PLL0 1
|
||||
#define R8A7792_CLK_PLL1 2
|
||||
#define R8A7792_CLK_PLL3 3
|
||||
#define R8A7792_CLK_LB 4
|
||||
#define R8A7792_CLK_QSPI 5
|
||||
|
||||
/* MSTP0 */
|
||||
#define R8A7792_CLK_MSIOF0 0
|
||||
|
||||
/* MSTP1 */
|
||||
#define R8A7792_CLK_JPU 6
|
||||
#define R8A7792_CLK_TMU1 11
|
||||
#define R8A7792_CLK_TMU3 21
|
||||
#define R8A7792_CLK_TMU2 22
|
||||
#define R8A7792_CLK_CMT0 24
|
||||
#define R8A7792_CLK_TMU0 25
|
||||
#define R8A7792_CLK_VSP1DU1 27
|
||||
#define R8A7792_CLK_VSP1DU0 28
|
||||
#define R8A7792_CLK_VSP1_SY 31
|
||||
|
||||
/* MSTP2 */
|
||||
#define R8A7792_CLK_MSIOF1 8
|
||||
#define R8A7792_CLK_SYS_DMAC1 18
|
||||
#define R8A7792_CLK_SYS_DMAC0 19
|
||||
|
||||
/* MSTP3 */
|
||||
#define R8A7792_CLK_TPU0 4
|
||||
#define R8A7792_CLK_SDHI0 14
|
||||
#define R8A7792_CLK_CMT1 29
|
||||
|
||||
/* MSTP4 */
|
||||
#define R8A7792_CLK_IRQC 7
|
||||
#define R8A7792_CLK_INTC_SYS 8
|
||||
|
||||
/* MSTP5 */
|
||||
#define R8A7792_CLK_AUDIO_DMAC0 2
|
||||
#define R8A7792_CLK_THERMAL 22
|
||||
#define R8A7792_CLK_PWM 23
|
||||
|
||||
/* MSTP7 */
|
||||
#define R8A7792_CLK_HSCIF1 16
|
||||
#define R8A7792_CLK_HSCIF0 17
|
||||
#define R8A7792_CLK_SCIF3 18
|
||||
#define R8A7792_CLK_SCIF2 19
|
||||
#define R8A7792_CLK_SCIF1 20
|
||||
#define R8A7792_CLK_SCIF0 21
|
||||
#define R8A7792_CLK_DU1 23
|
||||
#define R8A7792_CLK_DU0 24
|
||||
|
||||
/* MSTP8 */
|
||||
#define R8A7792_CLK_VIN5 4
|
||||
#define R8A7792_CLK_VIN4 5
|
||||
#define R8A7792_CLK_VIN3 8
|
||||
#define R8A7792_CLK_VIN2 9
|
||||
#define R8A7792_CLK_VIN1 10
|
||||
#define R8A7792_CLK_VIN0 11
|
||||
#define R8A7792_CLK_ETHERAVB 12
|
||||
|
||||
/* MSTP9 */
|
||||
#define R8A7792_CLK_GPIO7 4
|
||||
#define R8A7792_CLK_GPIO6 5
|
||||
#define R8A7792_CLK_GPIO5 7
|
||||
#define R8A7792_CLK_GPIO4 8
|
||||
#define R8A7792_CLK_GPIO3 9
|
||||
#define R8A7792_CLK_GPIO2 10
|
||||
#define R8A7792_CLK_GPIO1 11
|
||||
#define R8A7792_CLK_GPIO0 12
|
||||
#define R8A7792_CLK_GPIO11 13
|
||||
#define R8A7792_CLK_GPIO10 14
|
||||
#define R8A7792_CLK_CAN1 15
|
||||
#define R8A7792_CLK_CAN0 16
|
||||
#define R8A7792_CLK_QSPI_MOD 17
|
||||
#define R8A7792_CLK_GPIO9 19
|
||||
#define R8A7792_CLK_GPIO8 21
|
||||
#define R8A7792_CLK_I2C5 25
|
||||
#define R8A7792_CLK_IICDVFS 26
|
||||
#define R8A7792_CLK_I2C4 27
|
||||
#define R8A7792_CLK_I2C3 28
|
||||
#define R8A7792_CLK_I2C2 29
|
||||
#define R8A7792_CLK_I2C1 30
|
||||
#define R8A7792_CLK_I2C0 31
|
||||
|
||||
/* MSTP10 */
|
||||
#define R8A7792_CLK_SSI_ALL 5
|
||||
#define R8A7792_CLK_SSI4 11
|
||||
#define R8A7792_CLK_SSI3 12
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A7792_H__ */
|
||||
@@ -1,159 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* r8a7793 clock definition
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7793_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A7793_H__
|
||||
|
||||
/* CPG */
|
||||
#define R8A7793_CLK_MAIN 0
|
||||
#define R8A7793_CLK_PLL0 1
|
||||
#define R8A7793_CLK_PLL1 2
|
||||
#define R8A7793_CLK_PLL3 3
|
||||
#define R8A7793_CLK_LB 4
|
||||
#define R8A7793_CLK_QSPI 5
|
||||
#define R8A7793_CLK_SDH 6
|
||||
#define R8A7793_CLK_SD0 7
|
||||
#define R8A7793_CLK_Z 8
|
||||
#define R8A7793_CLK_RCAN 9
|
||||
#define R8A7793_CLK_ADSP 10
|
||||
|
||||
/* MSTP0 */
|
||||
#define R8A7793_CLK_MSIOF0 0
|
||||
|
||||
/* MSTP1 */
|
||||
#define R8A7793_CLK_VCP0 1
|
||||
#define R8A7793_CLK_VPC0 3
|
||||
#define R8A7793_CLK_SSP1 9
|
||||
#define R8A7793_CLK_TMU1 11
|
||||
#define R8A7793_CLK_3DG 12
|
||||
#define R8A7793_CLK_2DDMAC 15
|
||||
#define R8A7793_CLK_FDP1_1 18
|
||||
#define R8A7793_CLK_FDP1_0 19
|
||||
#define R8A7793_CLK_TMU3 21
|
||||
#define R8A7793_CLK_TMU2 22
|
||||
#define R8A7793_CLK_CMT0 24
|
||||
#define R8A7793_CLK_TMU0 25
|
||||
#define R8A7793_CLK_VSP1_DU1 27
|
||||
#define R8A7793_CLK_VSP1_DU0 28
|
||||
#define R8A7793_CLK_VSP1_S 31
|
||||
|
||||
/* MSTP2 */
|
||||
#define R8A7793_CLK_SCIFA2 2
|
||||
#define R8A7793_CLK_SCIFA1 3
|
||||
#define R8A7793_CLK_SCIFA0 4
|
||||
#define R8A7793_CLK_MSIOF2 5
|
||||
#define R8A7793_CLK_SCIFB0 6
|
||||
#define R8A7793_CLK_SCIFB1 7
|
||||
#define R8A7793_CLK_MSIOF1 8
|
||||
#define R8A7793_CLK_SCIFB2 16
|
||||
#define R8A7793_CLK_SYS_DMAC1 18
|
||||
#define R8A7793_CLK_SYS_DMAC0 19
|
||||
|
||||
/* MSTP3 */
|
||||
#define R8A7793_CLK_TPU0 4
|
||||
#define R8A7793_CLK_SDHI2 11
|
||||
#define R8A7793_CLK_SDHI1 12
|
||||
#define R8A7793_CLK_SDHI0 14
|
||||
#define R8A7793_CLK_MMCIF0 15
|
||||
#define R8A7793_CLK_IIC0 18
|
||||
#define R8A7793_CLK_PCIEC 19
|
||||
#define R8A7793_CLK_IIC1 23
|
||||
#define R8A7793_CLK_SSUSB 28
|
||||
#define R8A7793_CLK_CMT1 29
|
||||
#define R8A7793_CLK_USBDMAC0 30
|
||||
#define R8A7793_CLK_USBDMAC1 31
|
||||
|
||||
/* MSTP4 */
|
||||
#define R8A7793_CLK_IRQC 7
|
||||
#define R8A7793_CLK_INTC_SYS 8
|
||||
|
||||
/* MSTP5 */
|
||||
#define R8A7793_CLK_AUDIO_DMAC1 1
|
||||
#define R8A7793_CLK_AUDIO_DMAC0 2
|
||||
#define R8A7793_CLK_ADSP_MOD 6
|
||||
#define R8A7793_CLK_THERMAL 22
|
||||
#define R8A7793_CLK_PWM 23
|
||||
|
||||
/* MSTP7 */
|
||||
#define R8A7793_CLK_EHCI 3
|
||||
#define R8A7793_CLK_HSUSB 4
|
||||
#define R8A7793_CLK_HSCIF2 13
|
||||
#define R8A7793_CLK_SCIF5 14
|
||||
#define R8A7793_CLK_SCIF4 15
|
||||
#define R8A7793_CLK_HSCIF1 16
|
||||
#define R8A7793_CLK_HSCIF0 17
|
||||
#define R8A7793_CLK_SCIF3 18
|
||||
#define R8A7793_CLK_SCIF2 19
|
||||
#define R8A7793_CLK_SCIF1 20
|
||||
#define R8A7793_CLK_SCIF0 21
|
||||
#define R8A7793_CLK_DU1 23
|
||||
#define R8A7793_CLK_DU0 24
|
||||
#define R8A7793_CLK_LVDS0 26
|
||||
|
||||
/* MSTP8 */
|
||||
#define R8A7793_CLK_IPMMU_SGX 0
|
||||
#define R8A7793_CLK_VIN2 9
|
||||
#define R8A7793_CLK_VIN1 10
|
||||
#define R8A7793_CLK_VIN0 11
|
||||
#define R8A7793_CLK_ETHER 13
|
||||
#define R8A7793_CLK_SATA1 14
|
||||
#define R8A7793_CLK_SATA0 15
|
||||
|
||||
/* MSTP9 */
|
||||
#define R8A7793_CLK_GPIO7 4
|
||||
#define R8A7793_CLK_GPIO6 5
|
||||
#define R8A7793_CLK_GPIO5 7
|
||||
#define R8A7793_CLK_GPIO4 8
|
||||
#define R8A7793_CLK_GPIO3 9
|
||||
#define R8A7793_CLK_GPIO2 10
|
||||
#define R8A7793_CLK_GPIO1 11
|
||||
#define R8A7793_CLK_GPIO0 12
|
||||
#define R8A7793_CLK_RCAN1 15
|
||||
#define R8A7793_CLK_RCAN0 16
|
||||
#define R8A7793_CLK_QSPI_MOD 17
|
||||
#define R8A7793_CLK_I2C5 25
|
||||
#define R8A7793_CLK_IICDVFS 26
|
||||
#define R8A7793_CLK_I2C4 27
|
||||
#define R8A7793_CLK_I2C3 28
|
||||
#define R8A7793_CLK_I2C2 29
|
||||
#define R8A7793_CLK_I2C1 30
|
||||
#define R8A7793_CLK_I2C0 31
|
||||
|
||||
/* MSTP10 */
|
||||
#define R8A7793_CLK_SSI_ALL 5
|
||||
#define R8A7793_CLK_SSI9 6
|
||||
#define R8A7793_CLK_SSI8 7
|
||||
#define R8A7793_CLK_SSI7 8
|
||||
#define R8A7793_CLK_SSI6 9
|
||||
#define R8A7793_CLK_SSI5 10
|
||||
#define R8A7793_CLK_SSI4 11
|
||||
#define R8A7793_CLK_SSI3 12
|
||||
#define R8A7793_CLK_SSI2 13
|
||||
#define R8A7793_CLK_SSI1 14
|
||||
#define R8A7793_CLK_SSI0 15
|
||||
#define R8A7793_CLK_SCU_ALL 17
|
||||
#define R8A7793_CLK_SCU_DVC1 18
|
||||
#define R8A7793_CLK_SCU_DVC0 19
|
||||
#define R8A7793_CLK_SCU_CTU1_MIX1 20
|
||||
#define R8A7793_CLK_SCU_CTU0_MIX0 21
|
||||
#define R8A7793_CLK_SCU_SRC9 22
|
||||
#define R8A7793_CLK_SCU_SRC8 23
|
||||
#define R8A7793_CLK_SCU_SRC7 24
|
||||
#define R8A7793_CLK_SCU_SRC6 25
|
||||
#define R8A7793_CLK_SCU_SRC5 26
|
||||
#define R8A7793_CLK_SCU_SRC4 27
|
||||
#define R8A7793_CLK_SCU_SRC3 28
|
||||
#define R8A7793_CLK_SCU_SRC2 29
|
||||
#define R8A7793_CLK_SCU_SRC1 30
|
||||
#define R8A7793_CLK_SCU_SRC0 31
|
||||
|
||||
/* MSTP11 */
|
||||
#define R8A7793_CLK_SCIFA3 6
|
||||
#define R8A7793_CLK_SCIFA4 7
|
||||
#define R8A7793_CLK_SCIFA5 8
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A7793_H__ */
|
||||
@@ -1,137 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation
|
||||
* Copyright 2013 Ideas On Board SPRL
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7794_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A7794_H__
|
||||
|
||||
/* CPG */
|
||||
#define R8A7794_CLK_MAIN 0
|
||||
#define R8A7794_CLK_PLL0 1
|
||||
#define R8A7794_CLK_PLL1 2
|
||||
#define R8A7794_CLK_PLL3 3
|
||||
#define R8A7794_CLK_LB 4
|
||||
#define R8A7794_CLK_QSPI 5
|
||||
#define R8A7794_CLK_SDH 6
|
||||
#define R8A7794_CLK_SD0 7
|
||||
#define R8A7794_CLK_RCAN 8
|
||||
|
||||
/* MSTP0 */
|
||||
#define R8A7794_CLK_MSIOF0 0
|
||||
|
||||
/* MSTP1 */
|
||||
#define R8A7794_CLK_VCP0 1
|
||||
#define R8A7794_CLK_VPC0 3
|
||||
#define R8A7794_CLK_TMU1 11
|
||||
#define R8A7794_CLK_3DG 12
|
||||
#define R8A7794_CLK_2DDMAC 15
|
||||
#define R8A7794_CLK_FDP1_0 19
|
||||
#define R8A7794_CLK_TMU3 21
|
||||
#define R8A7794_CLK_TMU2 22
|
||||
#define R8A7794_CLK_CMT0 24
|
||||
#define R8A7794_CLK_TMU0 25
|
||||
#define R8A7794_CLK_VSP1_DU0 28
|
||||
#define R8A7794_CLK_VSP1_S 31
|
||||
|
||||
/* MSTP2 */
|
||||
#define R8A7794_CLK_SCIFA2 2
|
||||
#define R8A7794_CLK_SCIFA1 3
|
||||
#define R8A7794_CLK_SCIFA0 4
|
||||
#define R8A7794_CLK_MSIOF2 5
|
||||
#define R8A7794_CLK_SCIFB0 6
|
||||
#define R8A7794_CLK_SCIFB1 7
|
||||
#define R8A7794_CLK_MSIOF1 8
|
||||
#define R8A7794_CLK_SCIFB2 16
|
||||
#define R8A7794_CLK_SYS_DMAC1 18
|
||||
#define R8A7794_CLK_SYS_DMAC0 19
|
||||
|
||||
/* MSTP3 */
|
||||
#define R8A7794_CLK_SDHI2 11
|
||||
#define R8A7794_CLK_SDHI1 12
|
||||
#define R8A7794_CLK_SDHI0 14
|
||||
#define R8A7794_CLK_MMCIF0 15
|
||||
#define R8A7794_CLK_IIC0 18
|
||||
#define R8A7794_CLK_IIC1 23
|
||||
#define R8A7794_CLK_CMT1 29
|
||||
#define R8A7794_CLK_USBDMAC0 30
|
||||
#define R8A7794_CLK_USBDMAC1 31
|
||||
|
||||
/* MSTP4 */
|
||||
#define R8A7794_CLK_IRQC 7
|
||||
#define R8A7794_CLK_INTC_SYS 8
|
||||
|
||||
/* MSTP5 */
|
||||
#define R8A7794_CLK_AUDIO_DMAC0 2
|
||||
#define R8A7794_CLK_PWM 23
|
||||
|
||||
/* MSTP7 */
|
||||
#define R8A7794_CLK_EHCI 3
|
||||
#define R8A7794_CLK_HSUSB 4
|
||||
#define R8A7794_CLK_HSCIF2 13
|
||||
#define R8A7794_CLK_SCIF5 14
|
||||
#define R8A7794_CLK_SCIF4 15
|
||||
#define R8A7794_CLK_HSCIF1 16
|
||||
#define R8A7794_CLK_HSCIF0 17
|
||||
#define R8A7794_CLK_SCIF3 18
|
||||
#define R8A7794_CLK_SCIF2 19
|
||||
#define R8A7794_CLK_SCIF1 20
|
||||
#define R8A7794_CLK_SCIF0 21
|
||||
#define R8A7794_CLK_DU1 23
|
||||
#define R8A7794_CLK_DU0 24
|
||||
|
||||
/* MSTP8 */
|
||||
#define R8A7794_CLK_VIN1 10
|
||||
#define R8A7794_CLK_VIN0 11
|
||||
#define R8A7794_CLK_ETHERAVB 12
|
||||
#define R8A7794_CLK_ETHER 13
|
||||
|
||||
/* MSTP9 */
|
||||
#define R8A7794_CLK_GPIO6 5
|
||||
#define R8A7794_CLK_GPIO5 7
|
||||
#define R8A7794_CLK_GPIO4 8
|
||||
#define R8A7794_CLK_GPIO3 9
|
||||
#define R8A7794_CLK_GPIO2 10
|
||||
#define R8A7794_CLK_GPIO1 11
|
||||
#define R8A7794_CLK_GPIO0 12
|
||||
#define R8A7794_CLK_RCAN1 15
|
||||
#define R8A7794_CLK_RCAN0 16
|
||||
#define R8A7794_CLK_QSPI_MOD 17
|
||||
#define R8A7794_CLK_I2C5 25
|
||||
#define R8A7794_CLK_I2C4 27
|
||||
#define R8A7794_CLK_I2C3 28
|
||||
#define R8A7794_CLK_I2C2 29
|
||||
#define R8A7794_CLK_I2C1 30
|
||||
#define R8A7794_CLK_I2C0 31
|
||||
|
||||
/* MSTP10 */
|
||||
#define R8A7794_CLK_SSI_ALL 5
|
||||
#define R8A7794_CLK_SSI9 6
|
||||
#define R8A7794_CLK_SSI8 7
|
||||
#define R8A7794_CLK_SSI7 8
|
||||
#define R8A7794_CLK_SSI6 9
|
||||
#define R8A7794_CLK_SSI5 10
|
||||
#define R8A7794_CLK_SSI4 11
|
||||
#define R8A7794_CLK_SSI3 12
|
||||
#define R8A7794_CLK_SSI2 13
|
||||
#define R8A7794_CLK_SSI1 14
|
||||
#define R8A7794_CLK_SSI0 15
|
||||
#define R8A7794_CLK_SCU_ALL 17
|
||||
#define R8A7794_CLK_SCU_DVC1 18
|
||||
#define R8A7794_CLK_SCU_DVC0 19
|
||||
#define R8A7794_CLK_SCU_CTU1_MIX1 20
|
||||
#define R8A7794_CLK_SCU_CTU0_MIX0 21
|
||||
#define R8A7794_CLK_SCU_SRC6 25
|
||||
#define R8A7794_CLK_SCU_SRC5 26
|
||||
#define R8A7794_CLK_SCU_SRC4 27
|
||||
#define R8A7794_CLK_SCU_SRC3 28
|
||||
#define R8A7794_CLK_SCU_SRC2 29
|
||||
#define R8A7794_CLK_SCU_SRC1 30
|
||||
|
||||
/* MSTP11 */
|
||||
#define R8A7794_CLK_SCIFA3 6
|
||||
#define R8A7794_CLK_SCIFA4 7
|
||||
#define R8A7794_CLK_SCIFA5 8
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */
|
||||
Reference in New Issue
Block a user