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drm/xe/xe3p_xpc: Add L3 bank mask

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Expose L3 bank mask through topology query interface.

In Xe3p_XPC, MIRROR_L3BANK_ENABLE represents the full L3 bank mask (not
just a per-node mask), and each bit represents a single bank. With that
there's no extra complexity to calculate the L3 bank mask like there was
in previous platforms.

Bspec: 73439
Signed-off-by: Fei Yang <fei.yang@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20251016-xe3p-v3-15-3dd173a3097a@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
This commit is contained in:
Fei Yang
2025-10-16 19:26:34 -07:00
committed by Lucas De Marchi
parent e320b8841e
commit e82a97bf6a
1 changed files with 5 additions and 1 deletions
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6
drivers/gpu/drm/xe/xe_gt_topology.c
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@@ -148,7 +148,11 @@ load_l3_bank_mask(struct xe_gt *gt, xe_l3_bank_mask_t l3_bank_mask)
if (!xe_gt_topology_report_l3(gt))
return;
if (GRAPHICS_VER(xe) >= 30) {
if (GRAPHICS_VER(xe) >= 35) {
u32 fuse_val = xe_mmio_read32(mmio, MIRROR_L3BANK_ENABLE);
bitmap_from_arr32(l3_bank_mask, &fuse_val, 32);
} else if (GRAPHICS_VER(xe) >= 30) {
xe_l3_bank_mask_t per_node = {};
u32 meml3_en = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, fuse3);
u32 mirror_l3bank_enable = xe_mmio_read32(mmio, MIRROR_L3BANK_ENABLE);