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misc: amd-sbi: CPUID/MCAMSR protocol for Revision 0x21
- CPUID and MCAMSR protocol for newer platform with revision 0x21 and later is modified as per two byte register address size. - Modify the CPUID and MCAMSR protocol to return error, "-EOPNOTSUPP", for revision 0x21. - Next set of patches will add support for CPUID and MCAMSR for Turin and later platforms. Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com> Link: https://patch.msgid.link/20250915103649.1705078-4-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
committed by
Greg Kroah-Hartman
parent
45392fd439
commit
dd68c06380
@@ -122,8 +122,8 @@ static int rmi_cpuid_read(struct sbrmi_data *data,
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if (ret < 0)
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goto exit_unlock;
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}
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/* CPUID protocol for REV 0x10 is not supported*/
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if (data->rev == 0x10) {
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/* CPUID protocol for REV 0x20 is only supported*/
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if (data->rev != 0x20) {
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ret = -EOPNOTSUPP;
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goto exit_unlock;
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}
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@@ -203,8 +203,8 @@ static int rmi_mca_msr_read(struct sbrmi_data *data,
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if (ret < 0)
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goto exit_unlock;
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}
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/* MCA MSR protocol for REV 0x10 is not supported*/
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if (data->rev == 0x10) {
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/* MCA MSR protocol for REV 0x20 is supported*/
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if (data->rev != 0x20) {
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ret = -EOPNOTSUPP;
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goto exit_unlock;
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}
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