drm/i915: include gen 2 in HAS_128_BYTE_Y_TILING()

Gen 2 platforms actually have 128-byte Y-tile, it's just different from
the 128-byte Y-tile on i945+. Make the HAS_128_BYTE_Y_TILING() feature
check macro and its usage slightly less convoluted by including gen 2 in
it.

i915_tiling_ok() would strictly not need changing, but separate the if
clauses to emphasize gen 2 X-tile also being 128 bytes.

Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://lore.kernel.org/r/41bf9d67a11f38f4ab0f82740f38d5c8fe0bb58b.1760094361.git.jani.nikula@intel.com
This commit is contained in:
Jani Nikula
2025-10-10 14:07:51 +03:00
parent 2acee98fcc
commit dd1409b62e
3 changed files with 5 additions and 5 deletions

View File

@@ -814,7 +814,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
return 64;
fallthrough;
case I915_FORMAT_MOD_Y_TILED:
if (DISPLAY_VER(display) == 2 || HAS_128_BYTE_Y_TILING(i915))
if (HAS_128_BYTE_Y_TILING(i915))
return 128;
else
return 512;

View File

@@ -145,8 +145,9 @@ i915_tiling_ok(struct drm_i915_gem_object *obj,
return false;
}
if (GRAPHICS_VER(i915) == 2 ||
(tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915)))
if (tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915))
tile_width = 128;
else if (GRAPHICS_VER(i915) == 2)
tile_width = 128;
else
tile_width = 512;

View File

@@ -602,8 +602,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
* rows, which changed the alignment requirements and fence programming.
*/
#define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \
!(IS_I915G(i915) || IS_I915GM(i915)))
#define HAS_128_BYTE_Y_TILING(i915) (!IS_I915G(i915) && !IS_I915GM(i915))
#define HAS_RC6(i915) (INTEL_INFO(i915)->has_rc6)
#define HAS_RC6p(i915) (INTEL_INFO(i915)->has_rc6p)