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regulator: pca9450: Add support for setting debounce settings
Make the different debounce timers configurable from the devicetree. Depending on the board design, these have to be set different than the default register values. Signed-off-by: Martijn de Gouw <martijn.de.gouw@prodrive-technologies.com> Link: https://patch.msgid.link/20251117202215.1936139-2-martijn.de.gouw@prodrive-technologies.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Martijn de Gouw
committed by
Mark Brown
Mark Brown
parent
93218e3f2c
commit
d9d0be59be
@@ -1147,6 +1147,143 @@ static int pca9450_i2c_restart_handler(struct sys_off_data *data)
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return 0;
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}
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static int pca9450_of_init(struct pca9450 *pca9450)
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{
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struct i2c_client *i2c = container_of(pca9450->dev, struct i2c_client, dev);
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int ret;
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unsigned int val;
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unsigned int reset_ctrl;
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unsigned int rstb_deb_ctrl;
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unsigned int t_on_deb, t_off_deb;
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unsigned int t_on_step, t_off_step;
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unsigned int t_restart;
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if (of_property_read_bool(i2c->dev.of_node, "nxp,wdog_b-warm-reset"))
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reset_ctrl = WDOG_B_CFG_WARM;
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else
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reset_ctrl = WDOG_B_CFG_COLD_LDO12;
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/* Set reset behavior on assertion of WDOG_B signal */
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ret = regmap_update_bits(pca9450->regmap, PCA9450_REG_RESET_CTRL,
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WDOG_B_CFG_MASK, reset_ctrl);
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if (ret)
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return dev_err_probe(&i2c->dev, ret, "Failed to set WDOG_B reset behavior\n");
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ret = of_property_read_u32(i2c->dev.of_node, "npx,pmic-rst-b-debounce-ms", &val);
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if (ret == -EINVAL)
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rstb_deb_ctrl = T_PMIC_RST_DEB_50MS;
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else if (ret)
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return ret;
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else {
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switch (val) {
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case 10: rstb_deb_ctrl = T_PMIC_RST_DEB_10MS; break;
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case 50: rstb_deb_ctrl = T_PMIC_RST_DEB_50MS; break;
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case 100: rstb_deb_ctrl = T_PMIC_RST_DEB_100MS; break;
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case 500: rstb_deb_ctrl = T_PMIC_RST_DEB_500MS; break;
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case 1000: rstb_deb_ctrl = T_PMIC_RST_DEB_1S; break;
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case 2000: rstb_deb_ctrl = T_PMIC_RST_DEB_2S; break;
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case 4000: rstb_deb_ctrl = T_PMIC_RST_DEB_4S; break;
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case 8000: rstb_deb_ctrl = T_PMIC_RST_DEB_8S; break;
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default: return -EINVAL;
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}
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}
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ret = regmap_update_bits(pca9450->regmap, PCA9450_REG_RESET_CTRL,
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T_PMIC_RST_DEB_MASK, rstb_deb_ctrl);
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if (ret)
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return dev_err_probe(&i2c->dev, ret, "Failed to set PMIC_RST_B debounce time\n");
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ret = of_property_read_u32(i2c->dev.of_node, "nxp,pmic-on-req-on-debounce-us", &val);
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if (ret == -EINVAL)
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t_on_deb = T_ON_DEB_20MS;
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else if (ret)
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return ret;
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else {
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switch (val) {
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case 120: t_on_deb = T_ON_DEB_120US; break;
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case 20000: t_on_deb = T_ON_DEB_20MS; break;
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case 100000: t_on_deb = T_ON_DEB_100MS; break;
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case 750000: t_on_deb = T_ON_DEB_750MS; break;
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default: return -EINVAL;
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}
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}
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ret = of_property_read_u32(i2c->dev.of_node, "nxp,pmic-on-req-off-debounce-us", &val);
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if (ret == -EINVAL)
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t_off_deb = T_OFF_DEB_120US;
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else if (ret)
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return ret;
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else {
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switch (val) {
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case 120: t_off_deb = T_OFF_DEB_120US; break;
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case 2000: t_off_deb = T_OFF_DEB_2MS; break;
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default: return -EINVAL;
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}
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}
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ret = of_property_read_u32(i2c->dev.of_node, "nxp,power-on-step-ms", &val);
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if (ret == -EINVAL)
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t_on_step = T_ON_STEP_2MS;
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else if (ret)
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return ret;
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else {
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switch (val) {
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case 1: t_on_step = T_ON_STEP_1MS; break;
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case 2: t_on_step = T_ON_STEP_2MS; break;
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case 4: t_on_step = T_ON_STEP_4MS; break;
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case 8: t_on_step = T_ON_STEP_8MS; break;
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default: return -EINVAL;
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}
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}
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ret = of_property_read_u32(i2c->dev.of_node, "nxp,power-down-step-ms", &val);
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if (ret == -EINVAL)
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t_off_step = T_OFF_STEP_8MS;
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else if (ret)
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return ret;
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else {
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switch (val) {
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case 2: t_off_step = T_OFF_STEP_2MS; break;
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case 4: t_off_step = T_OFF_STEP_4MS; break;
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case 8: t_off_step = T_OFF_STEP_8MS; break;
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case 16: t_off_step = T_OFF_STEP_16MS; break;
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default: return -EINVAL;
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}
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}
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ret = of_property_read_u32(i2c->dev.of_node, "nxp,restart-ms", &val);
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if (ret == -EINVAL)
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t_restart = T_RESTART_250MS;
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else if (ret)
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return ret;
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else {
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switch (val) {
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case 250: t_restart = T_RESTART_250MS; break;
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case 500: t_restart = T_RESTART_500MS; break;
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default: return -EINVAL;
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}
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}
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ret = regmap_update_bits(pca9450->regmap, PCA9450_REG_PWRCTRL,
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T_ON_DEB_MASK | T_OFF_DEB_MASK | T_ON_STEP_MASK |
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T_OFF_STEP_MASK | T_RESTART_MASK,
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t_on_deb | t_off_deb | t_on_step |
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t_off_step | t_restart);
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if (ret)
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return dev_err_probe(&i2c->dev, ret,
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"Failed to set PWR_CTRL debounce configuration\n");
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if (of_property_read_bool(i2c->dev.of_node, "nxp,i2c-lt-enable")) {
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/* Enable I2C Level Translator */
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ret = regmap_update_bits(pca9450->regmap, PCA9450_REG_CONFIG2,
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I2C_LT_MASK, I2C_LT_ON_STANDBY_RUN);
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if (ret)
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return dev_err_probe(&i2c->dev, ret,
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"Failed to enable I2C level translator\n");
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}
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return 0;
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}
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static int pca9450_i2c_probe(struct i2c_client *i2c)
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{
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enum pca9450_chip_type type = (unsigned int)(uintptr_t)
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@@ -1156,7 +1293,6 @@ static int pca9450_i2c_probe(struct i2c_client *i2c)
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struct regulator_dev *ldo5;
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struct pca9450 *pca9450;
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unsigned int device_id, i;
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unsigned int reset_ctrl;
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int ret;
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pca9450 = devm_kzalloc(&i2c->dev, sizeof(struct pca9450), GFP_KERNEL);
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@@ -1254,25 +1390,9 @@ static int pca9450_i2c_probe(struct i2c_client *i2c)
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if (ret)
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return dev_err_probe(&i2c->dev, ret, "Failed to clear PRESET_EN bit\n");
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if (of_property_read_bool(i2c->dev.of_node, "nxp,wdog_b-warm-reset"))
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reset_ctrl = WDOG_B_CFG_WARM;
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else
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reset_ctrl = WDOG_B_CFG_COLD_LDO12;
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/* Set reset behavior on assertion of WDOG_B signal */
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ret = regmap_update_bits(pca9450->regmap, PCA9450_REG_RESET_CTRL,
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WDOG_B_CFG_MASK, reset_ctrl);
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ret = pca9450_of_init(pca9450);
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if (ret)
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return dev_err_probe(&i2c->dev, ret, "Failed to set WDOG_B reset behavior\n");
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if (of_property_read_bool(i2c->dev.of_node, "nxp,i2c-lt-enable")) {
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/* Enable I2C Level Translator */
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ret = regmap_update_bits(pca9450->regmap, PCA9450_REG_CONFIG2,
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I2C_LT_MASK, I2C_LT_ON_STANDBY_RUN);
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if (ret)
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return dev_err_probe(&i2c->dev, ret,
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"Failed to enable I2C level translator\n");
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}
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return dev_err_probe(&i2c->dev, ret, "Unable to parse OF data\n");
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/*
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* For LDO5 we need to be able to check the status of the SD_VSEL input in
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@@ -223,12 +223,44 @@ enum {
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#define IRQ_THERM_105 0x02
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#define IRQ_THERM_125 0x01
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/* PCA9450_REG_PWRCTRL bits */
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#define T_ON_DEB_MASK 0xC0
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#define T_ON_DEB_120US (0 << 6)
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#define T_ON_DEB_20MS (1 << 6)
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#define T_ON_DEB_100MS (2 << 6)
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#define T_ON_DEB_750MS (3 << 6)
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#define T_OFF_DEB_MASK 0x20
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#define T_OFF_DEB_120US (0 << 5)
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#define T_OFF_DEB_2MS (1 << 5)
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#define T_ON_STEP_MASK 0x18
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#define T_ON_STEP_1MS (0 << 3)
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#define T_ON_STEP_2MS (1 << 3)
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#define T_ON_STEP_4MS (2 << 3)
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#define T_ON_STEP_8MS (3 << 3)
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#define T_OFF_STEP_MASK 0x06
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#define T_OFF_STEP_2MS (0 << 1)
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#define T_OFF_STEP_4MS (1 << 1)
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#define T_OFF_STEP_8MS (2 << 1)
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#define T_OFF_STEP_16MS (3 << 1)
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#define T_RESTART_MASK 0x01
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#define T_RESTART_250MS 0
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#define T_RESTART_500MS 1
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/* PCA9450_REG_RESET_CTRL bits */
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#define WDOG_B_CFG_MASK 0xC0
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#define WDOG_B_CFG_NONE 0x00
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#define WDOG_B_CFG_WARM 0x40
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#define WDOG_B_CFG_COLD_LDO12 0x80
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#define WDOG_B_CFG_COLD 0xC0
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#define T_PMIC_RST_DEB_MASK 0x07
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#define T_PMIC_RST_DEB_10MS 0x00
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#define T_PMIC_RST_DEB_50MS 0x01
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#define T_PMIC_RST_DEB_100MS 0x02
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#define T_PMIC_RST_DEB_500MS 0x03
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#define T_PMIC_RST_DEB_1S 0x04
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#define T_PMIC_RST_DEB_2S 0x05
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#define T_PMIC_RST_DEB_4S 0x06
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#define T_PMIC_RST_DEB_8S 0x07
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/* PCA9450_REG_CONFIG2 bits */
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#define I2C_LT_MASK 0x03
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