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spi: sophgo: Fix incorrect use of bus width value macros

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The previous code initialized the 'reg' value with specific bus-width
values (BUS_WIDTH_2_BIT and BUS_WIDTH_4_BIT), which introduces ambiguity.
Replace them with BUS_WIDTH_MASK to express the intention clearly.

Fixes: de16c322ee ("spi: sophgo: add SG2044 SPI NOR controller driver")
Signed-off-by: Longbin Li <looong.bin@gmail.com>
Link: https://patch.msgid.link/20251117090559.78288-1-looong.bin@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Longbin Li
2025-11-17 17:05:39 +08:00
committed by Mark Brown
parent bd79452b39
commit d9813cd23d
1 changed files with 2 additions and 2 deletions
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4
drivers/spi/spi-sg2044-nor.c
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@@ -42,6 +42,7 @@
#define SPIFMC_TRAN_CSR_TRAN_MODE_RX BIT(0)
#define SPIFMC_TRAN_CSR_TRAN_MODE_TX BIT(1)
#define SPIFMC_TRAN_CSR_FAST_MODE BIT(3)
#define SPIFMC_TRAN_CSR_BUS_WIDTH_MASK GENMASK(5, 4)
#define SPIFMC_TRAN_CSR_BUS_WIDTH_1_BIT (0x00 << 4)
#define SPIFMC_TRAN_CSR_BUS_WIDTH_2_BIT (0x01 << 4)
#define SPIFMC_TRAN_CSR_BUS_WIDTH_4_BIT (0x02 << 4)
@@ -122,8 +123,7 @@ static u32 sg2044_spifmc_init_reg(struct sg2044_spifmc *spifmc)
reg = readl(spifmc->io_base + SPIFMC_TRAN_CSR);
reg &= ~(SPIFMC_TRAN_CSR_TRAN_MODE_MASK |
SPIFMC_TRAN_CSR_FAST_MODE |
SPIFMC_TRAN_CSR_BUS_WIDTH_2_BIT |
SPIFMC_TRAN_CSR_BUS_WIDTH_4_BIT |
SPIFMC_TRAN_CSR_BUS_WIDTH_MASK |
SPIFMC_TRAN_CSR_DMA_EN |
SPIFMC_TRAN_CSR_ADDR_BYTES_MASK |
SPIFMC_TRAN_CSR_WITH_CMD |