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drm/amdgpu/vce1: Implement VCE1 IP block (v2)
Implement the necessary functionality to support the VCE1. This implementation is based on: - VCE2 code from amdgpu - VCE1 code from radeon (the old driver) - Some trial and error A subsequent commit will ensure correct mapping for the VCPU BO, which will make this actually work. v2: - Use memset_io more. - Use memcpy_toio more. - Remove __func__ from warnings. - Don't reserve and map the VCPU BO anymore. - Add empty line to multi-line comments Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Co-developed-by: Alexandre Demers <alexandre.f.demers@gmail.com> Signed-off-by: Alexandre Demers <alexandre.f.demers@gmail.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Timur Kristóf
committed by
Alex Deucher
Alex Deucher
parent
e40251971c
commit
d4a640d4b9
@@ -78,7 +78,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o \
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dce_v8_0.o gfx_v7_0.o cik_sdma.o uvd_v4_2.o vce_v2_0.o
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amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o \
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uvd_v3_1.o
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uvd_v3_1.o vce_v1_0.o
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amdgpu-y += \
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vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \
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@@ -51,6 +51,7 @@ struct amdgpu_vce {
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struct drm_sched_entity entity;
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uint32_t srbm_soft_reset;
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unsigned num_rings;
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uint32_t keyselect;
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};
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int amdgpu_vce_early_init(struct amdgpu_device *adev);
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784
drivers/gpu/drm/amd/amdgpu/vce_v1_0.c
Normal file
784
drivers/gpu/drm/amd/amdgpu/vce_v1_0.c
Normal file
@@ -0,0 +1,784 @@
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// SPDX-License-Identifier: MIT
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/*
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* Copyright 2013 Advanced Micro Devices, Inc.
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* Copyright 2025 Valve Corporation
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* Copyright 2025 Alexandre Demers
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* Authors: Christian König <christian.koenig@amd.com>
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* Timur Kristóf <timur.kristof@gmail.com>
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* Alexandre Demers <alexandre.f.demers@gmail.com>
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*/
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#include <linux/firmware.h>
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#include "amdgpu.h"
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#include "amdgpu_vce.h"
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#include "sid.h"
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#include "vce_v1_0.h"
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#include "vce/vce_1_0_d.h"
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#include "vce/vce_1_0_sh_mask.h"
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#include "oss/oss_1_0_d.h"
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#include "oss/oss_1_0_sh_mask.h"
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#define VCE_V1_0_FW_SIZE (256 * 1024)
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#define VCE_V1_0_STACK_SIZE (64 * 1024)
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#define VCE_V1_0_DATA_SIZE (7808 * (AMDGPU_MAX_VCE_HANDLES + 1))
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#define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02
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static void vce_v1_0_set_ring_funcs(struct amdgpu_device *adev);
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static void vce_v1_0_set_irq_funcs(struct amdgpu_device *adev);
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struct vce_v1_0_fw_signature {
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int32_t offset;
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uint32_t length;
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int32_t number;
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struct {
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uint32_t chip_id;
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uint32_t keyselect;
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uint32_t nonce[4];
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uint32_t sigval[4];
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} val[8];
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};
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/**
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* vce_v1_0_ring_get_rptr - get read pointer
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*
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* @ring: amdgpu_ring pointer
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*
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* Returns the current hardware read pointer
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*/
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static uint64_t vce_v1_0_ring_get_rptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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if (ring->me == 0)
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return RREG32(mmVCE_RB_RPTR);
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else
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return RREG32(mmVCE_RB_RPTR2);
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}
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/**
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* vce_v1_0_ring_get_wptr - get write pointer
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*
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* @ring: amdgpu_ring pointer
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*
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* Returns the current hardware write pointer
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*/
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static uint64_t vce_v1_0_ring_get_wptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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if (ring->me == 0)
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return RREG32(mmVCE_RB_WPTR);
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else
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return RREG32(mmVCE_RB_WPTR2);
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}
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/**
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* vce_v1_0_ring_set_wptr - set write pointer
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*
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* @ring: amdgpu_ring pointer
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*
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* Commits the write pointer to the hardware
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*/
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static void vce_v1_0_ring_set_wptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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if (ring->me == 0)
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WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
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else
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WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
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}
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static int vce_v1_0_lmi_clean(struct amdgpu_device *adev)
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{
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int i, j;
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for (i = 0; i < 10; ++i) {
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for (j = 0; j < 100; ++j) {
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if (RREG32(mmVCE_LMI_STATUS) & 0x337f)
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return 0;
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mdelay(10);
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}
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}
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return -ETIMEDOUT;
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}
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static int vce_v1_0_firmware_loaded(struct amdgpu_device *adev)
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{
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int i, j;
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for (i = 0; i < 10; ++i) {
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for (j = 0; j < 100; ++j) {
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if (RREG32(mmVCE_STATUS) & VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK)
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return 0;
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mdelay(10);
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}
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dev_err(adev->dev, "VCE not responding, trying to reset the ECPU\n");
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WREG32_P(mmVCE_SOFT_RESET,
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VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
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~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
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mdelay(10);
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WREG32_P(mmVCE_SOFT_RESET, 0,
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~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
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mdelay(10);
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}
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return -ETIMEDOUT;
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}
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static void vce_v1_0_init_cg(struct amdgpu_device *adev)
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{
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u32 tmp;
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tmp = RREG32(mmVCE_CLOCK_GATING_A);
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tmp |= VCE_CLOCK_GATING_A__CGC_DYN_CLOCK_MODE_MASK;
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WREG32(mmVCE_CLOCK_GATING_A, tmp);
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tmp = RREG32(mmVCE_CLOCK_GATING_B);
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tmp |= 0x1e;
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tmp &= ~0xe100e1;
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WREG32(mmVCE_CLOCK_GATING_B, tmp);
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tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
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tmp &= ~0xff9ff000;
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WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
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tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
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tmp &= ~0x3ff;
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WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
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}
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/**
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* vce_v1_0_load_fw_signature - load firmware signature into VCPU BO
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*
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* @adev: amdgpu_device pointer
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*
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* The VCE1 firmware validation mechanism needs a firmware signature.
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* This function finds the signature appropriate for the current
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* ASIC and writes that into the VCPU BO.
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*/
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static int vce_v1_0_load_fw_signature(struct amdgpu_device *adev)
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{
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const struct common_firmware_header *hdr;
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struct vce_v1_0_fw_signature *sign;
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unsigned int ucode_offset;
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uint32_t chip_id;
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u32 *cpu_addr;
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int i;
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hdr = (const struct common_firmware_header *)adev->vce.fw->data;
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ucode_offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
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cpu_addr = adev->vce.cpu_addr;
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sign = (void *)adev->vce.fw->data + ucode_offset;
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switch (adev->asic_type) {
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case CHIP_TAHITI:
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chip_id = 0x01000014;
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break;
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case CHIP_VERDE:
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chip_id = 0x01000015;
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break;
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case CHIP_PITCAIRN:
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chip_id = 0x01000016;
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break;
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default:
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dev_err(adev->dev, "asic_type %#010x was not found!", adev->asic_type);
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return -EINVAL;
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}
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for (i = 0; i < le32_to_cpu(sign->number); ++i) {
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if (le32_to_cpu(sign->val[i].chip_id) == chip_id)
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break;
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}
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if (i == le32_to_cpu(sign->number)) {
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dev_err(adev->dev, "chip_id 0x%x for %s was not found in VCE firmware",
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chip_id, amdgpu_asic_name[adev->asic_type]);
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return -EINVAL;
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}
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cpu_addr += (256 - 64) / 4;
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memcpy_toio(&cpu_addr[0], &sign->val[i].nonce[0], 16);
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cpu_addr[4] = cpu_to_le32(le32_to_cpu(sign->length) + 64);
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memset_io(&cpu_addr[5], 0, 44);
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memcpy_toio(&cpu_addr[16], &sign[1], hdr->ucode_size_bytes - sizeof(*sign));
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cpu_addr += (le32_to_cpu(sign->length) + 64) / 4;
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memcpy_toio(&cpu_addr[0], &sign->val[i].sigval[0], 16);
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adev->vce.keyselect = le32_to_cpu(sign->val[i].keyselect);
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return 0;
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}
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static int vce_v1_0_wait_for_fw_validation(struct amdgpu_device *adev)
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{
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int i;
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dev_dbg(adev->dev, "VCE keyselect: %d", adev->vce.keyselect);
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WREG32(mmVCE_LMI_FW_START_KEYSEL, adev->vce.keyselect);
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for (i = 0; i < 10; ++i) {
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mdelay(10);
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if (RREG32(mmVCE_FW_REG_STATUS) & VCE_FW_REG_STATUS__DONE_MASK)
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break;
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}
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if (!(RREG32(mmVCE_FW_REG_STATUS) & VCE_FW_REG_STATUS__DONE_MASK)) {
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dev_err(adev->dev, "VCE FW validation timeout\n");
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return -ETIMEDOUT;
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}
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if (!(RREG32(mmVCE_FW_REG_STATUS) & VCE_FW_REG_STATUS__PASS_MASK)) {
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dev_err(adev->dev, "VCE FW validation failed\n");
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return -EINVAL;
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}
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for (i = 0; i < 10; ++i) {
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mdelay(10);
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if (!(RREG32(mmVCE_FW_REG_STATUS) & VCE_FW_REG_STATUS__BUSY_MASK))
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break;
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}
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if (RREG32(mmVCE_FW_REG_STATUS) & VCE_FW_REG_STATUS__BUSY_MASK) {
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dev_err(adev->dev, "VCE FW busy timeout\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int vce_v1_0_mc_resume(struct amdgpu_device *adev)
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{
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uint32_t offset;
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uint32_t size;
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/*
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* When the keyselect is already set, don't perturb VCE FW.
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* Validation seems to always fail the second time.
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*/
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if (RREG32(mmVCE_LMI_FW_START_KEYSEL)) {
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dev_dbg(adev->dev, "keyselect already set: 0x%x (on CPU: 0x%x)\n",
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RREG32(mmVCE_LMI_FW_START_KEYSEL), adev->vce.keyselect);
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WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);
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return 0;
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}
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WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));
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WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
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WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
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WREG32(mmVCE_CLOCK_GATING_B, 0);
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WREG32_P(mmVCE_LMI_FW_PERIODIC_CTRL, 0x4, ~0x4);
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WREG32(mmVCE_LMI_CTRL, 0x00398000);
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WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);
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WREG32(mmVCE_LMI_SWAP_CNTL, 0);
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WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
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WREG32(mmVCE_LMI_VM_CTRL, 0);
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WREG32(mmVCE_VCPU_SCRATCH7, AMDGPU_MAX_VCE_HANDLES);
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offset = adev->vce.gpu_addr + AMDGPU_VCE_FIRMWARE_OFFSET;
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size = VCE_V1_0_FW_SIZE;
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WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff);
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WREG32(mmVCE_VCPU_CACHE_SIZE0, size);
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offset += size;
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size = VCE_V1_0_STACK_SIZE;
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WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff);
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WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
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offset += size;
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size = VCE_V1_0_DATA_SIZE;
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WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff);
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WREG32(mmVCE_VCPU_CACHE_SIZE2, size);
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WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);
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return vce_v1_0_wait_for_fw_validation(adev);
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}
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/**
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* vce_v1_0_is_idle() - Check idle status of VCE1 IP block
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*
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* @ip_block: amdgpu_ip_block pointer
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*
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* Check whether VCE is busy according to VCE_STATUS.
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* Also check whether the SRBM thinks VCE is busy, although
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* SRBM_STATUS.VCE_BUSY seems to be bogus because it
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* appears to mirror the VCE_STATUS.VCPU_REPORT_FW_LOADED bit.
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*/
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static bool vce_v1_0_is_idle(struct amdgpu_ip_block *ip_block)
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{
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struct amdgpu_device *adev = ip_block->adev;
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bool busy =
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(RREG32(mmVCE_STATUS) & (VCE_STATUS__JOB_BUSY_MASK | VCE_STATUS__UENC_BUSY_MASK)) ||
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(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);
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return !busy;
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}
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static int vce_v1_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
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{
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struct amdgpu_device *adev = ip_block->adev;
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unsigned int i;
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for (i = 0; i < adev->usec_timeout; i++) {
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udelay(1);
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if (vce_v1_0_is_idle(ip_block))
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return 0;
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}
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return -ETIMEDOUT;
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}
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/**
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* vce_v1_0_start - start VCE block
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*
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* @adev: amdgpu_device pointer
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*
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* Setup and start the VCE block
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*/
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static int vce_v1_0_start(struct amdgpu_device *adev)
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{
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struct amdgpu_ring *ring;
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int r;
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WREG32_P(mmVCE_STATUS, 1, ~1);
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r = vce_v1_0_mc_resume(adev);
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if (r)
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return r;
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ring = &adev->vce.ring[0];
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WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr));
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WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
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WREG32(mmVCE_RB_BASE_LO, lower_32_bits(ring->gpu_addr));
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WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
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WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);
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|
||||
ring = &adev->vce.ring[1];
|
||||
WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr));
|
||||
WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
|
||||
WREG32(mmVCE_RB_BASE_LO2, lower_32_bits(ring->gpu_addr));
|
||||
WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
|
||||
WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);
|
||||
|
||||
WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK,
|
||||
~VCE_VCPU_CNTL__CLK_EN_MASK);
|
||||
|
||||
WREG32_P(mmVCE_SOFT_RESET,
|
||||
VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK |
|
||||
VCE_SOFT_RESET__FME_SOFT_RESET_MASK,
|
||||
~(VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK |
|
||||
VCE_SOFT_RESET__FME_SOFT_RESET_MASK));
|
||||
|
||||
mdelay(100);
|
||||
|
||||
WREG32_P(mmVCE_SOFT_RESET, 0,
|
||||
~(VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK |
|
||||
VCE_SOFT_RESET__FME_SOFT_RESET_MASK));
|
||||
|
||||
r = vce_v1_0_firmware_loaded(adev);
|
||||
|
||||
/* Clear VCE_STATUS, otherwise SRBM thinks VCE1 is busy. */
|
||||
WREG32(mmVCE_STATUS, 0);
|
||||
|
||||
if (r) {
|
||||
dev_err(adev->dev, "VCE not responding, giving up\n");
|
||||
return r;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int vce_v1_0_stop(struct amdgpu_device *adev)
|
||||
{
|
||||
struct amdgpu_ip_block *ip_block;
|
||||
int status;
|
||||
int i;
|
||||
|
||||
ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE);
|
||||
if (!ip_block)
|
||||
return -EINVAL;
|
||||
|
||||
if (vce_v1_0_lmi_clean(adev))
|
||||
dev_warn(adev->dev, "VCE not idle\n");
|
||||
|
||||
if (vce_v1_0_wait_for_idle(ip_block))
|
||||
dev_warn(adev->dev, "VCE busy: VCE_STATUS=0x%x, SRBM_STATUS2=0x%x\n",
|
||||
RREG32(mmVCE_STATUS), RREG32(mmSRBM_STATUS2));
|
||||
|
||||
/* Stall UMC and register bus before resetting VCPU */
|
||||
WREG32_P(mmVCE_LMI_CTRL2, 1 << 8, ~(1 << 8));
|
||||
|
||||
for (i = 0; i < 100; ++i) {
|
||||
status = RREG32(mmVCE_LMI_STATUS);
|
||||
if (status & 0x240)
|
||||
break;
|
||||
mdelay(1);
|
||||
}
|
||||
|
||||
WREG32_P(mmVCE_VCPU_CNTL, 0, ~VCE_VCPU_CNTL__CLK_EN_MASK);
|
||||
|
||||
WREG32_P(mmVCE_SOFT_RESET,
|
||||
VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK |
|
||||
VCE_SOFT_RESET__FME_SOFT_RESET_MASK,
|
||||
~(VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK |
|
||||
VCE_SOFT_RESET__FME_SOFT_RESET_MASK));
|
||||
|
||||
WREG32(mmVCE_STATUS, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void vce_v1_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)) {
|
||||
tmp = RREG32(mmVCE_CLOCK_GATING_A);
|
||||
tmp |= VCE_CLOCK_GATING_A__CGC_DYN_CLOCK_MODE_MASK;
|
||||
WREG32(mmVCE_CLOCK_GATING_A, tmp);
|
||||
|
||||
tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
|
||||
tmp &= ~0x1ff000;
|
||||
tmp |= 0xff800000;
|
||||
WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
|
||||
|
||||
tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
|
||||
tmp &= ~0x3ff;
|
||||
WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
|
||||
} else {
|
||||
tmp = RREG32(mmVCE_CLOCK_GATING_A);
|
||||
tmp &= ~VCE_CLOCK_GATING_A__CGC_DYN_CLOCK_MODE_MASK;
|
||||
WREG32(mmVCE_CLOCK_GATING_A, tmp);
|
||||
|
||||
tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
|
||||
tmp |= 0x1ff000;
|
||||
tmp &= ~0xff800000;
|
||||
WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
|
||||
|
||||
tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
|
||||
tmp |= 0x3ff;
|
||||
WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
|
||||
}
|
||||
}
|
||||
|
||||
static int vce_v1_0_early_init(struct amdgpu_ip_block *ip_block)
|
||||
{
|
||||
struct amdgpu_device *adev = ip_block->adev;
|
||||
int r;
|
||||
|
||||
r = amdgpu_vce_early_init(adev);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
adev->vce.num_rings = 2;
|
||||
|
||||
vce_v1_0_set_ring_funcs(adev);
|
||||
vce_v1_0_set_irq_funcs(adev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int vce_v1_0_sw_init(struct amdgpu_ip_block *ip_block)
|
||||
{
|
||||
struct amdgpu_device *adev = ip_block->adev;
|
||||
struct amdgpu_ring *ring;
|
||||
int r, i;
|
||||
|
||||
r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 167, &adev->vce.irq);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
r = amdgpu_vce_sw_init(adev, VCE_V1_0_FW_SIZE +
|
||||
VCE_V1_0_STACK_SIZE + VCE_V1_0_DATA_SIZE);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
r = amdgpu_vce_resume(adev);
|
||||
if (r)
|
||||
return r;
|
||||
r = vce_v1_0_load_fw_signature(adev);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
for (i = 0; i < adev->vce.num_rings; i++) {
|
||||
enum amdgpu_ring_priority_level hw_prio = amdgpu_vce_get_ring_prio(i);
|
||||
|
||||
ring = &adev->vce.ring[i];
|
||||
sprintf(ring->name, "vce%d", i);
|
||||
r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0,
|
||||
hw_prio, NULL);
|
||||
if (r)
|
||||
return r;
|
||||
}
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static int vce_v1_0_sw_fini(struct amdgpu_ip_block *ip_block)
|
||||
{
|
||||
struct amdgpu_device *adev = ip_block->adev;
|
||||
int r;
|
||||
|
||||
r = amdgpu_vce_suspend(adev);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
return amdgpu_vce_sw_fini(adev);
|
||||
}
|
||||
|
||||
/**
|
||||
* vce_v1_0_hw_init - start and test VCE block
|
||||
*
|
||||
* @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
|
||||
*
|
||||
* Initialize the hardware, boot up the VCPU and do some testing
|
||||
*/
|
||||
static int vce_v1_0_hw_init(struct amdgpu_ip_block *ip_block)
|
||||
{
|
||||
struct amdgpu_device *adev = ip_block->adev;
|
||||
int i, r;
|
||||
|
||||
if (adev->pm.dpm_enabled)
|
||||
amdgpu_dpm_enable_vce(adev, true);
|
||||
else
|
||||
amdgpu_asic_set_vce_clocks(adev, 10000, 10000);
|
||||
|
||||
for (i = 0; i < adev->vce.num_rings; i++) {
|
||||
r = amdgpu_ring_test_helper(&adev->vce.ring[i]);
|
||||
if (r)
|
||||
return r;
|
||||
}
|
||||
|
||||
dev_info(adev->dev, "VCE initialized successfully.\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int vce_v1_0_hw_fini(struct amdgpu_ip_block *ip_block)
|
||||
{
|
||||
int r;
|
||||
|
||||
r = vce_v1_0_stop(ip_block->adev);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
cancel_delayed_work_sync(&ip_block->adev->vce.idle_work);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int vce_v1_0_suspend(struct amdgpu_ip_block *ip_block)
|
||||
{
|
||||
struct amdgpu_device *adev = ip_block->adev;
|
||||
int r;
|
||||
|
||||
/*
|
||||
* Proper cleanups before halting the HW engine:
|
||||
* - cancel the delayed idle work
|
||||
* - enable powergating
|
||||
* - enable clockgating
|
||||
* - disable dpm
|
||||
*
|
||||
* TODO: to align with the VCN implementation, move the
|
||||
* jobs for clockgating/powergating/dpm setting to
|
||||
* ->set_powergating_state().
|
||||
*/
|
||||
cancel_delayed_work_sync(&adev->vce.idle_work);
|
||||
|
||||
if (adev->pm.dpm_enabled) {
|
||||
amdgpu_dpm_enable_vce(adev, false);
|
||||
} else {
|
||||
amdgpu_asic_set_vce_clocks(adev, 0, 0);
|
||||
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
|
||||
AMD_PG_STATE_GATE);
|
||||
amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
|
||||
AMD_CG_STATE_GATE);
|
||||
}
|
||||
|
||||
r = vce_v1_0_hw_fini(ip_block);
|
||||
if (r) {
|
||||
dev_err(adev->dev, "vce_v1_0_hw_fini() failed with error %i", r);
|
||||
return r;
|
||||
}
|
||||
|
||||
return amdgpu_vce_suspend(adev);
|
||||
}
|
||||
|
||||
static int vce_v1_0_resume(struct amdgpu_ip_block *ip_block)
|
||||
{
|
||||
struct amdgpu_device *adev = ip_block->adev;
|
||||
int r;
|
||||
|
||||
r = amdgpu_vce_resume(adev);
|
||||
if (r)
|
||||
return r;
|
||||
r = vce_v1_0_load_fw_signature(adev);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
return vce_v1_0_hw_init(ip_block);
|
||||
}
|
||||
|
||||
static int vce_v1_0_set_interrupt_state(struct amdgpu_device *adev,
|
||||
struct amdgpu_irq_src *source,
|
||||
unsigned int type,
|
||||
enum amdgpu_interrupt_state state)
|
||||
{
|
||||
uint32_t val = 0;
|
||||
|
||||
if (state == AMDGPU_IRQ_STATE_ENABLE)
|
||||
val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK;
|
||||
|
||||
WREG32_P(mmVCE_SYS_INT_EN, val,
|
||||
~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int vce_v1_0_process_interrupt(struct amdgpu_device *adev,
|
||||
struct amdgpu_irq_src *source,
|
||||
struct amdgpu_iv_entry *entry)
|
||||
{
|
||||
dev_dbg(adev->dev, "IH: VCE\n");
|
||||
switch (entry->src_data[0]) {
|
||||
case 0:
|
||||
case 1:
|
||||
amdgpu_fence_process(&adev->vce.ring[entry->src_data[0]]);
|
||||
break;
|
||||
default:
|
||||
dev_err(adev->dev, "Unhandled interrupt: %d %d\n",
|
||||
entry->src_id, entry->src_data[0]);
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int vce_v1_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
|
||||
enum amd_clockgating_state state)
|
||||
{
|
||||
struct amdgpu_device *adev = ip_block->adev;
|
||||
|
||||
vce_v1_0_init_cg(adev);
|
||||
vce_v1_0_enable_mgcg(adev, state == AMD_CG_STATE_GATE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int vce_v1_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
|
||||
enum amd_powergating_state state)
|
||||
{
|
||||
struct amdgpu_device *adev = ip_block->adev;
|
||||
|
||||
/*
|
||||
* This doesn't actually powergate the VCE block.
|
||||
* That's done in the dpm code via the SMC. This
|
||||
* just re-inits the block as necessary. The actual
|
||||
* gating still happens in the dpm code. We should
|
||||
* revisit this when there is a cleaner line between
|
||||
* the smc and the hw blocks
|
||||
*/
|
||||
if (state == AMD_PG_STATE_GATE)
|
||||
return vce_v1_0_stop(adev);
|
||||
else
|
||||
return vce_v1_0_start(adev);
|
||||
}
|
||||
|
||||
static const struct amd_ip_funcs vce_v1_0_ip_funcs = {
|
||||
.name = "vce_v1_0",
|
||||
.early_init = vce_v1_0_early_init,
|
||||
.sw_init = vce_v1_0_sw_init,
|
||||
.sw_fini = vce_v1_0_sw_fini,
|
||||
.hw_init = vce_v1_0_hw_init,
|
||||
.hw_fini = vce_v1_0_hw_fini,
|
||||
.suspend = vce_v1_0_suspend,
|
||||
.resume = vce_v1_0_resume,
|
||||
.is_idle = vce_v1_0_is_idle,
|
||||
.wait_for_idle = vce_v1_0_wait_for_idle,
|
||||
.set_clockgating_state = vce_v1_0_set_clockgating_state,
|
||||
.set_powergating_state = vce_v1_0_set_powergating_state,
|
||||
};
|
||||
|
||||
static const struct amdgpu_ring_funcs vce_v1_0_ring_funcs = {
|
||||
.type = AMDGPU_RING_TYPE_VCE,
|
||||
.align_mask = 0xf,
|
||||
.nop = VCE_CMD_NO_OP,
|
||||
.support_64bit_ptrs = false,
|
||||
.no_user_fence = true,
|
||||
.get_rptr = vce_v1_0_ring_get_rptr,
|
||||
.get_wptr = vce_v1_0_ring_get_wptr,
|
||||
.set_wptr = vce_v1_0_ring_set_wptr,
|
||||
.parse_cs = amdgpu_vce_ring_parse_cs,
|
||||
.emit_frame_size = 6, /* amdgpu_vce_ring_emit_fence x1 no user fence */
|
||||
.emit_ib_size = 4, /* amdgpu_vce_ring_emit_ib */
|
||||
.emit_ib = amdgpu_vce_ring_emit_ib,
|
||||
.emit_fence = amdgpu_vce_ring_emit_fence,
|
||||
.test_ring = amdgpu_vce_ring_test_ring,
|
||||
.test_ib = amdgpu_vce_ring_test_ib,
|
||||
.insert_nop = amdgpu_ring_insert_nop,
|
||||
.pad_ib = amdgpu_ring_generic_pad_ib,
|
||||
.begin_use = amdgpu_vce_ring_begin_use,
|
||||
.end_use = amdgpu_vce_ring_end_use,
|
||||
};
|
||||
|
||||
static void vce_v1_0_set_ring_funcs(struct amdgpu_device *adev)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < adev->vce.num_rings; i++) {
|
||||
adev->vce.ring[i].funcs = &vce_v1_0_ring_funcs;
|
||||
adev->vce.ring[i].me = i;
|
||||
}
|
||||
};
|
||||
|
||||
static const struct amdgpu_irq_src_funcs vce_v1_0_irq_funcs = {
|
||||
.set = vce_v1_0_set_interrupt_state,
|
||||
.process = vce_v1_0_process_interrupt,
|
||||
};
|
||||
|
||||
static void vce_v1_0_set_irq_funcs(struct amdgpu_device *adev)
|
||||
{
|
||||
adev->vce.irq.num_types = 1;
|
||||
adev->vce.irq.funcs = &vce_v1_0_irq_funcs;
|
||||
};
|
||||
|
||||
const struct amdgpu_ip_block_version vce_v1_0_ip_block = {
|
||||
.type = AMD_IP_BLOCK_TYPE_VCE,
|
||||
.major = 1,
|
||||
.minor = 0,
|
||||
.rev = 0,
|
||||
.funcs = &vce_v1_0_ip_funcs,
|
||||
};
|
||||
32
drivers/gpu/drm/amd/amdgpu/vce_v1_0.h
Normal file
32
drivers/gpu/drm/amd/amdgpu/vce_v1_0.h
Normal file
@@ -0,0 +1,32 @@
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
/*
|
||||
* Copyright 2025 Advanced Micro Devices, Inc.
|
||||
* Copyright 2025 Valve Corporation
|
||||
* Copyright 2025 Alexandre Demers
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __VCE_V1_0_H__
|
||||
#define __VCE_V1_0_H__
|
||||
|
||||
extern const struct amdgpu_ip_block_version vce_v1_0_ip_block;
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user