drm/amdgpu: Configure max beneficial TTM pool allocation order

Let the TTM pool allocator know that we can afford for it to expend less
effort for satisfying contiguous allocations larger than 2MiB. The latter
is the maximum relevant PTE entry size and the driver and hardware are
happy to get larger blocks only opportunistically.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Thadeu Lima de Souza Cascardo <cascardo@igalia.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
Link: https://lore.kernel.org/r/20251020115411.36818-6-tvrtko.ursulin@igalia.com
This commit is contained in:
Tvrtko Ursulin
2025-10-20 12:54:10 +01:00
committed by Tvrtko Ursulin
parent 7e9c548d37
commit ccbadd9eea

View File

@@ -1837,7 +1837,7 @@ static int amdgpu_ttm_pools_init(struct amdgpu_device *adev)
for (i = 0; i < adev->gmc.num_mem_partitions; i++) {
ttm_pool_init(&adev->mman.ttm_pools[i], adev->dev,
adev->gmc.mem_partitions[i].numa.node,
0);
TTM_ALLOCATION_POOL_BENEFICIAL_ORDER(get_order(SZ_2M)));
}
return 0;
}
@@ -1933,7 +1933,8 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
(adev->need_swiotlb ?
TTM_ALLOCATION_POOL_USE_DMA_ALLOC : 0) |
(dma_addressing_limited(adev->dev) ?
TTM_ALLOCATION_POOL_USE_DMA32 : 0));
TTM_ALLOCATION_POOL_USE_DMA32 : 0) |
TTM_ALLOCATION_POOL_BENEFICIAL_ORDER(get_order(SZ_2M)));
if (r) {
dev_err(adev->dev,
"failed initializing buffer object driver(%d).\n", r);