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Revert "arm64: dts: marvell: cn9132-clearfog: fix multi-lane pci x2 and x4 ports"

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This reverts commit 794a066688 because it
misunderstood interworking between arm trusted firmware and the common
phy driver, and does not consistently resolve the issue it was intended
to address.

Further diagnostics have revealed the root cause for the reported system
lock-up in a race condition between pci driver probe and clock core
disabling unused clocks.

Revert the wrong change restoring driver control over all pci lanes.
As a temporary workaround for the original issue, users can boot with
"clk_ignore_unused".

Signed-off-by: Josua Mayer <josua@solid-run.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This commit is contained in:
Josua Mayer
2025-10-30 16:16:25 +01:00
committed by Gregory CLEMENT
parent da69aeac10
commit c9b6a83670
1 changed files with 2 additions and 14 deletions
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16
arch/arm64/boot/dts/marvell/cn9132-clearfog.dts
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@@ -413,13 +413,7 @@
/* SRDS #0,#1,#2,#3 - PCIe */
&cp0_pcie0 {
num-lanes = <4>;
/*
* The mvebu-comphy driver does not currently know how to pass correct
* lane-count to ATF while configuring the serdes lanes.
* Rely on bootloader configuration only.
*
* phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>;
*/
phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>;
status = "okay";
};
@@ -481,13 +475,7 @@
/* SRDS #0,#1 - PCIe */
&cp1_pcie0 {
num-lanes = <2>;
/*
* The mvebu-comphy driver does not currently know how to pass correct
* lane-count to ATF while configuring the serdes lanes.
* Rely on bootloader configuration only.
*
* phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>;
*/
phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>;
status = "okay";
};