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wifi: rtw89: use separated function to set RX filter
Normally use rtw89_write32_mask() with a consecutive bit mask, but mask of RX filter B_AX_RX_FLTR_CFG_MASK is bits 31-22 and 15-0, which excludes bits of B_AX_RX_MPDU_MAX_LEN_MASK (bits 21-16). Though the original logic is well to set RX filter, change it to a separate function to avoid the tricky design. Cc: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251113053459.34995-1-pkshih@realtek.com
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@@ -4173,12 +4173,10 @@ void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
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void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
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{
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const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
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struct ieee80211_hw *hw = rtwdev->hw;
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struct rtw89_roc *roc = &rtwvif->roc;
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struct rtw89_vif_link *rtwvif_link;
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struct rtw89_vif *tmp_vif;
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u32 reg;
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int ret;
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lockdep_assert_wiphy(hw->wiphy);
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@@ -4195,8 +4193,7 @@ void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
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return;
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}
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reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, rtwvif_link->mac_idx);
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rtw89_write32_mask(rtwdev, reg, B_AX_RX_FLTR_CFG_MASK, rtwdev->hal.rx_fltr);
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rtw89_mac_set_rx_fltr(rtwdev, rtwvif_link->mac_idx, rtwdev->hal.rx_fltr);
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roc->state = RTW89_ROC_IDLE;
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rtw89_config_roc_chandef(rtwdev, rtwvif_link, NULL);
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@@ -8103,7 +8103,6 @@ int rtw89_hw_scan_start(struct rtw89_dev *rtwdev,
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struct rtw89_vif_link *rtwvif_link,
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struct ieee80211_scan_request *scan_req)
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{
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const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
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enum rtw89_entity_mode mode = rtw89_get_entity_mode(rtwdev);
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struct cfg80211_scan_request *req = &scan_req->req;
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const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
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@@ -8115,7 +8114,6 @@ int rtw89_hw_scan_start(struct rtw89_dev *rtwdev,
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};
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u32 rx_fltr = rtwdev->hal.rx_fltr;
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u8 mac_addr[ETH_ALEN];
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u32 reg;
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int ret;
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/* clone op and keep it during scan */
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@@ -8155,8 +8153,7 @@ int rtw89_hw_scan_start(struct rtw89_dev *rtwdev,
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rx_fltr &= ~B_AX_A_BC;
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rx_fltr &= ~B_AX_A_A1_MATCH;
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reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, rtwvif_link->mac_idx);
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rtw89_write32_mask(rtwdev, reg, B_AX_RX_FLTR_CFG_MASK, rx_fltr);
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rtw89_mac_set_rx_fltr(rtwdev, rtwvif_link->mac_idx, rx_fltr);
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rtw89_chanctx_pause(rtwdev, &pause_parm);
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rtw89_phy_dig_suspend(rtwdev);
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@@ -8174,20 +8171,17 @@ struct rtw89_hw_scan_complete_cb_data {
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static int rtw89_hw_scan_complete_cb(struct rtw89_dev *rtwdev, void *data)
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{
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const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
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enum rtw89_entity_mode mode = rtw89_get_entity_mode(rtwdev);
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struct rtw89_hw_scan_complete_cb_data *cb_data = data;
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struct rtw89_vif_link *rtwvif_link = cb_data->rtwvif_link;
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struct cfg80211_scan_info info = {
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.aborted = cb_data->aborted,
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};
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u32 reg;
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if (!rtwvif_link)
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return -EINVAL;
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reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, rtwvif_link->mac_idx);
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rtw89_write32_mask(rtwdev, reg, B_AX_RX_FLTR_CFG_MASK, rtwdev->hal.rx_fltr);
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rtw89_mac_set_rx_fltr(rtwdev, rtwvif_link->mac_idx, rtwdev->hal.rx_fltr);
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rtw89_core_scan_complete(rtwdev, rtwvif_link, true);
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ieee80211_scan_completed(rtwdev->hw, &info);
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@@ -2543,6 +2543,20 @@ static int rtw89_mac_typ_fltr_opt_ax(struct rtw89_dev *rtwdev,
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return 0;
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}
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void rtw89_mac_set_rx_fltr(struct rtw89_dev *rtwdev, u8 mac_idx, u32 rx_fltr)
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{
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const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
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u32 reg;
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u32 val;
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reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, mac_idx);
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val = rtw89_read32(rtwdev, reg);
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/* B_AX_RX_FLTR_CFG_MASK is not a consecutive bit mask */
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val = (val & ~B_AX_RX_FLTR_CFG_MASK) | (rx_fltr & B_AX_RX_FLTR_CFG_MASK);
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rtw89_write32(rtwdev, reg, val);
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}
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static int rx_fltr_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
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{
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int ret, i;
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@@ -1340,6 +1340,7 @@ int rtw89_mac_cfg_ppdu_status_bands(struct rtw89_dev *rtwdev, bool enable)
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return rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_1, enable);
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}
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void rtw89_mac_set_rx_fltr(struct rtw89_dev *rtwdev, u8 mac_idx, u32 rx_fltr);
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void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev);
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void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop);
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int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex);
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@@ -307,7 +307,6 @@ static void rtw89_ops_configure_filter(struct ieee80211_hw *hw,
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u64 multicast)
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{
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struct rtw89_dev *rtwdev = hw->priv;
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const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
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u32 rx_fltr;
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lockdep_assert_wiphy(hw->wiphy);
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@@ -369,16 +368,10 @@ static void rtw89_ops_configure_filter(struct ieee80211_hw *hw,
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rx_fltr &= ~B_AX_A_A1_MATCH;
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}
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rtw89_write32_mask(rtwdev,
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rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_0),
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B_AX_RX_FLTR_CFG_MASK,
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rx_fltr);
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rtw89_mac_set_rx_fltr(rtwdev, RTW89_MAC_0, rx_fltr);
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if (!rtwdev->dbcc_en)
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return;
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rtw89_write32_mask(rtwdev,
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rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_1),
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B_AX_RX_FLTR_CFG_MASK,
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rx_fltr);
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rtw89_mac_set_rx_fltr(rtwdev, RTW89_MAC_1, rx_fltr);
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}
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static const u8 ac_to_fw_idx[IEEE80211_NUM_ACS] = {
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