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serial: sc16is7xx: reformat comments to improve readability
Fold some multi-line comments into a single line, taking advantage of the new 100 line length limit to improve readability and to have uniform style across driver. Add missing 's' to SC16IS7XX_MCR_TCRTLR_BIT registers comments. Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com> Link: https://patch.msgid.link/20251027142957.1032073-14-hugo@hugovil.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Hugo Villeneuve
committed by
Greg Kroah-Hartman
Greg Kroah-Hartman
parent
b90871cba6
commit
bee8828a76
@@ -50,18 +50,10 @@
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#define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */
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#define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */
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#define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
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#define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction
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* - only on 75x/76x
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*/
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#define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State
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* - only on 75x/76x
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*/
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#define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable
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* - only on 75x/76x
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*/
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#define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control
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* - only on 75x/76x
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*/
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#define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction - only on 75x/76x */
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#define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State - only on 75x/76x */
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#define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable - only on 75x/76x */
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#define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control - only on 75x/76x */
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#define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */
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/* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
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@@ -81,12 +73,9 @@
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/* IER register bits */
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#define SC16IS7XX_IER_RDI_BIT BIT(0) /* Enable RX data interrupt */
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#define SC16IS7XX_IER_THRI_BIT BIT(1) /* Enable TX holding register
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* interrupt */
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#define SC16IS7XX_IER_RLSI_BIT BIT(2) /* Enable RX line status
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* interrupt */
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#define SC16IS7XX_IER_MSI_BIT BIT(3) /* Enable Modem status
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* interrupt */
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#define SC16IS7XX_IER_THRI_BIT BIT(1) /* Enable TX holding register interrupt */
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#define SC16IS7XX_IER_RLSI_BIT BIT(2) /* Enable RX line status interrupt */
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#define SC16IS7XX_IER_MSI_BIT BIT(3) /* Enable Modem status interrupt */
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/* IER register bits - write only if (EFR[4] == 1) */
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#define SC16IS7XX_IER_SLEEP_BIT BIT(4) /* Enable Sleep mode */
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@@ -119,9 +108,8 @@
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* - only on 75x/76x
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*/
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#define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */
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#define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state
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* from active (LOW)
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* to inactive (HIGH)
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#define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state from active
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* (LOW) to inactive (HIGH)
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*/
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/* LCR register bits */
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#define SC16IS7XX_LCR_LENGTH0_BIT BIT(0) /* Word length bit 0 */
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@@ -137,8 +125,7 @@
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*
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* STOP length bit table:
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* 0 -> 1 stop bit
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* 1 -> 1-1.5 stop bits if
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* word length is 5,
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* 1 -> 1-1.5 stop bits if word length is 5,
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* 2 stop bits otherwise
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*/
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#define SC16IS7XX_LCR_PARITY_BIT BIT(3) /* Parity bit enable */
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@@ -150,31 +137,22 @@
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#define SC16IS7XX_LCR_WORD_LEN_6 (0x01)
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#define SC16IS7XX_LCR_WORD_LEN_7 (0x02)
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#define SC16IS7XX_LCR_WORD_LEN_8 (0x03)
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#define SC16IS7XX_LCR_REG_SET_SPECIAL SC16IS7XX_LCR_DLAB_BIT /* Special
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* reg set
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*/
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#define SC16IS7XX_LCR_REG_SET_ENHANCED 0xBF /* Enhanced
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* reg set
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*/
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#define SC16IS7XX_LCR_REG_SET_SPECIAL SC16IS7XX_LCR_DLAB_BIT /* Special reg set */
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#define SC16IS7XX_LCR_REG_SET_ENHANCED 0xBF /* Enhanced reg set */
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/* MCR register bits */
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#define SC16IS7XX_MCR_DTR_BIT BIT(0) /* DTR complement
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* - only on 75x/76x
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*/
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#define SC16IS7XX_MCR_DTR_BIT BIT(0) /* DTR complement - only on 75x/76x */
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#define SC16IS7XX_MCR_RTS_BIT BIT(1) /* RTS complement */
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#define SC16IS7XX_MCR_TCRTLR_BIT BIT(2) /* TCR/TLR register enable */
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#define SC16IS7XX_MCR_TCRTLR_BIT BIT(2) /* TCR/TLR registers enable */
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#define SC16IS7XX_MCR_LOOP_BIT BIT(4) /* Enable loopback test mode */
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#define SC16IS7XX_MCR_XONANY_BIT BIT(5) /* Enable Xon Any
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* - write enabled
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* if (EFR[4] == 1)
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* - write enabled if (EFR[4] == 1)
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*/
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#define SC16IS7XX_MCR_IRDA_BIT BIT(6) /* Enable IrDA mode
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* - write enabled
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* if (EFR[4] == 1)
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* - write enabled if (EFR[4] == 1)
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*/
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#define SC16IS7XX_MCR_CLKSEL_BIT BIT(7) /* Divide clock by 4
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* - write enabled
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* if (EFR[4] == 1)
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* - write enabled if (EFR[4] == 1)
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*/
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/* LSR register bits */
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@@ -195,28 +173,19 @@
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/* MSR register bits */
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#define SC16IS7XX_MSR_DCTS_BIT BIT(0) /* Delta CTS Clear To Send */
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#define SC16IS7XX_MSR_DDSR_BIT BIT(1) /* Delta DSR Data Set Ready
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* or (IO4)
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#define SC16IS7XX_MSR_DDSR_BIT BIT(1) /* Delta DSR Data Set Ready or (IO4)
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* - only on 75x/76x
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*/
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#define SC16IS7XX_MSR_DRI_BIT BIT(2) /* Delta RI Ring Indicator
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* or (IO7)
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#define SC16IS7XX_MSR_DRI_BIT BIT(2) /* Delta RI Ring Indicator or (IO7)
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* - only on 75x/76x
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*/
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#define SC16IS7XX_MSR_DCD_BIT BIT(3) /* Delta CD Carrier Detect
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* or (IO6)
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#define SC16IS7XX_MSR_DCD_BIT BIT(3) /* Delta CD Carrier Detect or (IO6)
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* - only on 75x/76x
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*/
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#define SC16IS7XX_MSR_CTS_BIT BIT(4) /* CTS */
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#define SC16IS7XX_MSR_DSR_BIT BIT(5) /* DSR (IO4)
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* - only on 75x/76x
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*/
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#define SC16IS7XX_MSR_RI_BIT BIT(6) /* RI (IO7)
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* - only on 75x/76x
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*/
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#define SC16IS7XX_MSR_CD_BIT BIT(7) /* CD (IO6)
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* - only on 75x/76x
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*/
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#define SC16IS7XX_MSR_DSR_BIT BIT(5) /* DSR (IO4) - only on 75x/76x */
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#define SC16IS7XX_MSR_RI_BIT BIT(6) /* RI (IO7) - only on 75x/76x */
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#define SC16IS7XX_MSR_CD_BIT BIT(7) /* CD (IO6) - only on 75x/76x */
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/*
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* TCR register bits
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@@ -255,54 +224,42 @@
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#define SC16IS7XX_IOCONTROL_SRESET_BIT BIT(3) /* Software Reset */
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/* EFCR register bits */
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#define SC16IS7XX_EFCR_9BIT_MODE_BIT BIT(0) /* Enable 9-bit or Multidrop
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* mode (RS485) */
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#define SC16IS7XX_EFCR_9BIT_MODE_BIT BIT(0) /* Enable 9-bit or Multidrop mode (RS485) */
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#define SC16IS7XX_EFCR_RXDISABLE_BIT BIT(1) /* Disable receiver */
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#define SC16IS7XX_EFCR_TXDISABLE_BIT BIT(2) /* Disable transmitter */
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#define SC16IS7XX_EFCR_AUTO_RS485_BIT BIT(4) /* Auto RS485 RTS direction */
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#define SC16IS7XX_EFCR_RTS_INVERT_BIT BIT(5) /* RTS output inversion */
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#define SC16IS7XX_EFCR_IRDA_MODE_BIT BIT(7) /* IrDA mode
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* 0 = rate upto 115.2 kbit/s
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* - Only 75x/76x
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* 1 = rate upto 1.152 Mbit/s
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* - Only 76x
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* 0 = rate up to 115.2 kbit/s - Only 75x/76x
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* 1 = rate up to 1.152 Mbit/s - Only 76x
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*/
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/* EFR register bits */
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#define SC16IS7XX_EFR_AUTORTS_BIT BIT(6) /* Auto RTS flow ctrl enable */
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#define SC16IS7XX_EFR_AUTOCTS_BIT BIT(7) /* Auto CTS flow ctrl enable */
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#define SC16IS7XX_EFR_XOFF2_DETECT_BIT BIT(5) /* Enable Xoff2 detection */
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#define SC16IS7XX_EFR_ENABLE_BIT BIT(4) /* Enable enhanced functions
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* and writing to IER[7:4],
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* FCR[5:4], MCR[7:5]
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#define SC16IS7XX_EFR_ENABLE_BIT BIT(4) /* Enable enhanced functions and writing to
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* IER[7:4], FCR[5:4], MCR[7:5]
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*/
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#define SC16IS7XX_EFR_SWFLOW3_BIT BIT(3)
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#define SC16IS7XX_EFR_SWFLOW2_BIT BIT(2)
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/*
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* SWFLOW bits 3 & 2 table:
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* 00 -> no transmitter flow
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* control
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* 01 -> transmitter generates
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* XON2 and XOFF2
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* 10 -> transmitter generates
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* XON1 and XOFF1
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* 11 -> transmitter generates
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* XON1, XON2, XOFF1 and
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* XOFF2
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* 00 -> no transmitter flow control
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* 01 -> transmitter generates XON2 and XOFF2
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* 10 -> transmitter generates XON1 and XOFF1
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* 11 -> transmitter generates XON1, XON2,
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* XOFF1 and XOFF2
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*/
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#define SC16IS7XX_EFR_SWFLOW1_BIT BIT(1)
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#define SC16IS7XX_EFR_SWFLOW0_BIT BIT(0)
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/*
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* SWFLOW bits 1 & 0 table:
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* 00 -> no received flow
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* control
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* 01 -> receiver compares
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* XON2 and XOFF2
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* 10 -> receiver compares
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* XON1 and XOFF1
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* 11 -> receiver compares
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* XON1, XON2, XOFF1 and
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* XOFF2
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* 00 -> no received flow control
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* 01 -> receiver compares XON2 and XOFF2
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* 10 -> receiver compares XON1 and XOFF1
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* 11 -> receiver compares XON1, XON2,
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* XOFF1 and XOFF2
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*/
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#define SC16IS7XX_EFR_FLOWCTRL_BITS (SC16IS7XX_EFR_AUTORTS_BIT | \
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SC16IS7XX_EFR_AUTOCTS_BIT | \
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@@ -1152,7 +1109,7 @@ static int sc16is7xx_startup(struct uart_port *port)
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sc16is7xx_power(port, 1);
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/* Reset FIFOs*/
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/* Reset FIFOs */
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val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
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sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
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udelay(5);
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