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dt-bindings: media: Describe Qualcomm SM8650 CAMSS IP
Add device tree bindings for Qualcomm SM8650 camera subsystem. Qualcomm SM8650 CAMSS IP contains the next subdevices: * 6 x CSIPHY, * 3 x CSID, 2 x CSID Lite, * 3 x IFE, 2 x IFE Lite. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD Signed-off-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
This commit is contained in:
Vladimir Zapolskiy
committed by
Hans Verkuil
Hans Verkuil
parent
ec697196d6
commit
bbad9ae1cc
375
Documentation/devicetree/bindings/media/qcom,sm8650-camss.yaml
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375
Documentation/devicetree/bindings/media/qcom,sm8650-camss.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/qcom,sm8650-camss.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SM8650 Camera Subsystem (CAMSS)
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maintainers:
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- Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
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description:
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The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
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properties:
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compatible:
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const: qcom,sm8650-camss
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reg:
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maxItems: 17
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reg-names:
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items:
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- const: csid_wrapper
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- const: csid0
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- const: csid1
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- const: csid2
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- const: csid_lite0
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- const: csid_lite1
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- const: csiphy0
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- const: csiphy1
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- const: csiphy2
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- const: csiphy3
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- const: csiphy4
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- const: csiphy5
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- const: vfe0
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- const: vfe1
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- const: vfe2
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- const: vfe_lite0
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- const: vfe_lite1
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clocks:
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maxItems: 33
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clock-names:
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items:
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- const: camnoc_axi
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- const: cpas_ahb
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- const: cpas_fast_ahb
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- const: cpas_vfe0
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- const: cpas_vfe1
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- const: cpas_vfe2
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- const: cpas_vfe_lite
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- const: csid
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- const: csiphy0
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- const: csiphy0_timer
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- const: csiphy1
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- const: csiphy1_timer
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- const: csiphy2
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- const: csiphy2_timer
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- const: csiphy3
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- const: csiphy3_timer
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- const: csiphy4
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- const: csiphy4_timer
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- const: csiphy5
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- const: csiphy5_timer
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- const: csiphy_rx
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- const: gcc_axi_hf
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- const: qdss_debug_xo
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- const: vfe0
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- const: vfe0_fast_ahb
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- const: vfe1
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- const: vfe1_fast_ahb
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- const: vfe2
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- const: vfe2_fast_ahb
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- const: vfe_lite
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- const: vfe_lite_ahb
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- const: vfe_lite_cphy_rx
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- const: vfe_lite_csid
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interrupts:
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maxItems: 16
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interrupt-names:
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items:
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- const: csid0
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- const: csid1
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- const: csid2
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- const: csid_lite0
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- const: csid_lite1
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- const: csiphy0
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- const: csiphy1
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- const: csiphy2
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- const: csiphy3
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- const: csiphy4
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- const: csiphy5
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- const: vfe0
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- const: vfe1
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- const: vfe2
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- const: vfe_lite0
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- const: vfe_lite1
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interconnects:
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maxItems: 2
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interconnect-names:
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items:
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- const: ahb
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- const: hf_mnoc
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iommus:
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maxItems: 3
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power-domains:
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items:
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- description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
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- description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
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- description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller.
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- description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
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power-domain-names:
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items:
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- const: ife0
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- const: ife1
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- const: ife2
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- const: top
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description:
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CSI input ports.
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patternProperties:
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"^port@[0-5]$":
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description:
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Input port for receiving CSI data from a CSIPHY.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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data-lanes:
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minItems: 1
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maxItems: 4
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bus-type:
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enum:
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- 1 # MEDIA_BUS_TYPE_CSI2_CPHY
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- 4 # MEDIA_BUS_TYPE_CSI2_DPHY
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required:
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- data-lanes
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vdd-csiphy01-0p9-supply:
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description:
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Phandle to a 0.9V regulator supply to CSIPHY0 and CSIPHY1 IP blocks.
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vdd-csiphy01-1p2-supply:
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description:
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Phandle to a 1.2V regulator supply to CSIPHY0 and CSIPHY1 IP blocks.
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vdd-csiphy24-0p9-supply:
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description:
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Phandle to a 0.9V regulator supply to CSIPHY2 and CSIPHY4 IP blocks.
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vdd-csiphy24-1p2-supply:
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description:
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Phandle to a 1.2V regulator supply to CSIPHY2 and CSIPHY4 IP blocks.
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vdd-csiphy35-0p9-supply:
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description:
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Phandle to a 0.9V regulator supply to CSIPHY3 and CSIPHY5 IP blocks.
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vdd-csiphy35-1p2-supply:
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description:
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Phandle to a 1.2V regulator supply to CSIPHY3 and CSIPHY5 IP blocks.
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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- interconnects
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- interconnect-names
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- interrupts
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- interrupt-names
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- iommus
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- power-domains
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- power-domain-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,sm8650-camcc.h>
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#include <dt-bindings/clock/qcom,sm8650-gcc.h>
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#include <dt-bindings/interconnect/qcom,sm8650-rpmh.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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isp@acb6000 {
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compatible = "qcom,sm8650-camss";
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reg = <0 0x0acb6000 0 0x1000>,
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<0 0x0acb8000 0 0x1000>,
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<0 0x0acba000 0 0x1000>,
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<0 0x0acbc000 0 0x1000>,
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<0 0x0accb000 0 0x1000>,
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<0 0x0acd0000 0 0x1000>,
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<0 0x0ace4000 0 0x2000>,
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<0 0x0ace6000 0 0x2000>,
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<0 0x0ace8000 0 0x2000>,
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<0 0x0acea000 0 0x2000>,
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<0 0x0acec000 0 0x2000>,
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<0 0x0acee000 0 0x2000>,
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<0 0x0ac62000 0 0xf000>,
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<0 0x0ac71000 0 0xf000>,
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<0 0x0ac80000 0 0xf000>,
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<0 0x0accc000 0 0x2000>,
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<0 0x0acd1000 0 0x2000>;
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reg-names = "csid_wrapper",
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"csid0",
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"csid1",
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"csid2",
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"csid_lite0",
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"csid_lite1",
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"csiphy0",
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"csiphy1",
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"csiphy2",
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"csiphy3",
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"csiphy4",
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"csiphy5",
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"vfe0",
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"vfe1",
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"vfe2",
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"vfe_lite0",
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"vfe_lite1";
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clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
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<&camcc CAM_CC_CPAS_AHB_CLK>,
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<&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
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<&camcc CAM_CC_CPAS_IFE_0_CLK>,
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<&camcc CAM_CC_CPAS_IFE_1_CLK>,
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<&camcc CAM_CC_CPAS_IFE_2_CLK>,
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<&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
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<&camcc CAM_CC_CSID_CLK>,
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<&camcc CAM_CC_CSIPHY0_CLK>,
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<&camcc CAM_CC_CSI0PHYTIMER_CLK>,
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<&camcc CAM_CC_CSI1PHYTIMER_CLK>,
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<&camcc CAM_CC_CSIPHY1_CLK>,
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<&camcc CAM_CC_CSI2PHYTIMER_CLK>,
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<&camcc CAM_CC_CSIPHY2_CLK>,
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<&camcc CAM_CC_CSI3PHYTIMER_CLK>,
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<&camcc CAM_CC_CSIPHY3_CLK>,
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<&camcc CAM_CC_CSI4PHYTIMER_CLK>,
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<&camcc CAM_CC_CSIPHY4_CLK>,
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<&camcc CAM_CC_CSI5PHYTIMER_CLK>,
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<&camcc CAM_CC_CSIPHY5_CLK>,
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<&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
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<&gcc GCC_CAMERA_HF_AXI_CLK>,
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<&camcc CAM_CC_QDSS_DEBUG_XO_CLK>,
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<&camcc CAM_CC_IFE_0_CLK>,
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<&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
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<&camcc CAM_CC_IFE_1_CLK>,
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<&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
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<&camcc CAM_CC_IFE_2_CLK>,
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<&camcc CAM_CC_IFE_2_FAST_AHB_CLK>,
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<&camcc CAM_CC_IFE_LITE_CLK>,
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<&camcc CAM_CC_IFE_LITE_AHB_CLK>,
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<&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
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<&camcc CAM_CC_IFE_LITE_CSID_CLK>;
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clock-names = "camnoc_axi",
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"cpas_ahb",
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"cpas_fast_ahb",
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"cpas_vfe0",
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"cpas_vfe1",
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"cpas_vfe2",
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"cpas_vfe_lite",
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"csid",
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"csiphy0",
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"csiphy0_timer",
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"csiphy1",
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"csiphy1_timer",
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"csiphy2",
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"csiphy2_timer",
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"csiphy3",
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"csiphy3_timer",
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"csiphy4",
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"csiphy4_timer",
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"csiphy5",
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"csiphy5_timer",
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"csiphy_rx",
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"gcc_axi_hf",
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"qdss_debug_xo",
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"vfe0",
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"vfe0_fast_ahb",
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"vfe1",
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"vfe1_fast_ahb",
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"vfe2",
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"vfe2_fast_ahb",
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"vfe_lite",
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"vfe_lite_ahb",
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"vfe_lite_cphy_rx",
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"vfe_lite_csid";
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interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 602 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 688 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 606 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 377 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "csid0",
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"csid1",
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"csid2",
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"csid_lite0",
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"csid_lite1",
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"csiphy0",
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"csiphy1",
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"csiphy2",
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"csiphy3",
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"csiphy4",
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"csiphy5",
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"vfe0",
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"vfe1",
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"vfe2",
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"vfe_lite0",
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"vfe_lite1";
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interconnects = <&gem_noc MASTER_APPSS_PROC 0
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&config_noc SLAVE_CAMERA_CFG 0>,
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<&mmss_noc MASTER_CAMNOC_HF 0
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&mc_virt SLAVE_EBI1 0>;
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interconnect-names = "ahb", "hf_mnoc";
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iommus = <&apps_smmu 0x800 0x20>,
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<&apps_smmu 0x18a0 0x40>,
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<&apps_smmu 0x1860 0x00>;
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power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
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<&camcc CAM_CC_IFE_1_GDSC>,
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<&camcc CAM_CC_IFE_2_GDSC>,
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<&camcc CAM_CC_TITAN_TOP_GDSC>;
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power-domain-names = "ife0", "ife1", "ife2", "top";
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vdd-csiphy01-0p9-supply = <&vreg_0p9>;
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vdd-csiphy01-1p2-supply = <&vreg_1p2>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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reg = <1>;
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csiphy1_ep: endpoint {
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data-lanes = <0 1>;
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remote-endpoint = <&camera_sensor>;
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};
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};
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};
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};
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};
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