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arm64: dts: renesas: r9a09g011: Add CSI nodes

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The Renesas RZ/V2M comes with 6 Clocked Serial Interface (CSI)
IPs (CSI0, CSI1, CSI2, CSI3, CSI4, CSI5), but Linux is only
allowed access to CSI0 and CSI4.

This commit adds SoC specific device tree support for CSI0 and
CSI4.

Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230622113341.657842-5-fabrizio.castro.jz@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Fabrizio Castro
2023-06-22 12:33:40 +01:00
committed by Geert Uytterhoeven
parent db67345716
commit ba81bf44c6
1 changed files with 28 additions and 0 deletions
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28
arch/arm64/boot/dts/renesas/r9a09g011.dtsi
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@@ -236,6 +236,34 @@
reg = <0 0xa3f03000 0 0x400>;
};
csi0: spi@a4020000 {
compatible = "renesas,rzv2m-csi";
reg = <0 0xa4020000 0 0x80>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A09G011_CSI0_CLK>,
<&cpg CPG_MOD R9A09G011_CPERI_GRPG_PCLK>;
clock-names = "csiclk", "pclk";
resets = <&cpg R9A09G011_CSI_GPG_PRESETN>;
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
csi4: spi@a4020200 {
compatible = "renesas,rzv2m-csi";
reg = <0 0xa4020200 0 0x80>;
interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A09G011_CSI4_CLK>,
<&cpg CPG_MOD R9A09G011_CPERI_GRPH_PCLK>;
clock-names = "csiclk", "pclk";
resets = <&cpg R9A09G011_CSI_GPH_PRESETN>;
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c0: i2c@a4030000 {
#address-cells = <1>;
#size-cells = <0>;