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arm64/sysreg: Replace TCR_EL1 field macros
This just replaces all used TCR_EL1 field macros with tools sysreg variant based fields and subsequently drops them from the header (pgtable-hwdef.h), although while retaining the ones used for KVM (represented via the sysreg tools format). Cc: Will Deacon <will@kernel.org> Cc: Mark Brown <broonie@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Anshuman Khandual
committed by
Catalin Marinas
Catalin Marinas
parent
3a86608788
commit
b0a3f0e894
@@ -325,14 +325,14 @@ alternative_cb_end
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* tcr_set_t0sz - update TCR.T0SZ so that we can load the ID map
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*/
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.macro tcr_set_t0sz, valreg, t0sz
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bfi \valreg, \t0sz, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH
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bfi \valreg, \t0sz, #TCR_EL1_T0SZ_SHIFT, #TCR_EL1_T0SZ_WIDTH
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.endm
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/*
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* tcr_set_t1sz - update TCR.T1SZ
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*/
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.macro tcr_set_t1sz, valreg, t1sz
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bfi \valreg, \t1sz, #TCR_T1SZ_OFFSET, #TCR_TxSZ_WIDTH
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bfi \valreg, \t1sz, #TCR_EL1_T1SZ_SHIFT, #TCR_EL1_T1SZ_WIDTH
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.endm
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/*
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@@ -589,7 +589,7 @@ alternative_endif
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.macro offset_ttbr1, ttbr, tmp
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#if defined(CONFIG_ARM64_VA_BITS_52) && !defined(CONFIG_ARM64_LPA2)
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mrs \tmp, tcr_el1
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and \tmp, \tmp, #TCR_T1SZ_MASK
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and \tmp, \tmp, #TCR_EL1_T1SZ_MASK
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cmp \tmp, #TCR_T1SZ(VA_BITS_MIN)
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orr \tmp, \ttbr, #TTBR1_BADDR_4852_OFFSET
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csel \ttbr, \tmp, \ttbr, eq
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@@ -247,7 +247,7 @@
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/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
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#define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
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#define MIDR_FUJITSU_ERRATUM_010001_MASK (~MIDR_CPU_VAR_REV(1, 0))
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#define TCR_CLEAR_FUJITSU_ERRATUM_010001 (TCR_NFD1 | TCR_NFD0)
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#define TCR_CLEAR_FUJITSU_ERRATUM_010001 (TCR_EL1_NFD1 | TCR_EL1_NFD0)
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#ifndef __ASSEMBLY__
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@@ -73,10 +73,10 @@ static inline void __cpu_set_tcr_t0sz(unsigned long t0sz)
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{
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unsigned long tcr = read_sysreg(tcr_el1);
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if ((tcr & TCR_T0SZ_MASK) == t0sz)
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if ((tcr & TCR_EL1_T0SZ_MASK) == t0sz)
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return;
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tcr &= ~TCR_T0SZ_MASK;
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tcr &= ~TCR_EL1_T0SZ_MASK;
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tcr |= t0sz;
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write_sysreg(tcr, tcr_el1);
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isb();
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@@ -228,102 +228,53 @@
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/*
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* TCR flags.
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*/
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#define TCR_T0SZ_OFFSET 0
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#define TCR_T1SZ_OFFSET 16
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#define TCR_T0SZ(x) ((UL(64) - (x)) << TCR_T0SZ_OFFSET)
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#define TCR_T1SZ(x) ((UL(64) - (x)) << TCR_T1SZ_OFFSET)
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#define TCR_TxSZ(x) (TCR_T0SZ(x) | TCR_T1SZ(x))
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#define TCR_TxSZ_WIDTH 6
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#define TCR_T0SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET)
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#define TCR_T1SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T1SZ_OFFSET)
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#define TCR_T0SZ(x) ((UL(64) - (x)) << TCR_EL1_T0SZ_SHIFT)
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#define TCR_T1SZ(x) ((UL(64) - (x)) << TCR_EL1_T1SZ_SHIFT)
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#define TCR_EPD0_SHIFT 7
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#define TCR_EPD0_MASK (UL(1) << TCR_EPD0_SHIFT)
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#define TCR_IRGN0_SHIFT 8
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#define TCR_IRGN0_MASK (UL(3) << TCR_IRGN0_SHIFT)
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#define TCR_IRGN0_NC (UL(0) << TCR_IRGN0_SHIFT)
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#define TCR_IRGN0_WBWA (UL(1) << TCR_IRGN0_SHIFT)
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#define TCR_IRGN0_WT (UL(2) << TCR_IRGN0_SHIFT)
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#define TCR_IRGN0_WBnWA (UL(3) << TCR_IRGN0_SHIFT)
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#define TCR_T0SZ_MASK TCR_EL1_T0SZ_MASK
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#define TCR_T1SZ_MASK TCR_EL1_T1SZ_MASK
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#define TCR_EPD1_SHIFT 23
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#define TCR_EPD1_MASK (UL(1) << TCR_EPD1_SHIFT)
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#define TCR_IRGN1_SHIFT 24
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#define TCR_IRGN1_MASK (UL(3) << TCR_IRGN1_SHIFT)
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#define TCR_IRGN1_NC (UL(0) << TCR_IRGN1_SHIFT)
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#define TCR_IRGN1_WBWA (UL(1) << TCR_IRGN1_SHIFT)
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#define TCR_IRGN1_WT (UL(2) << TCR_IRGN1_SHIFT)
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#define TCR_IRGN1_WBnWA (UL(3) << TCR_IRGN1_SHIFT)
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#define TCR_EPD0_MASK TCR_EL1_EPD0_MASK
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#define TCR_EPD1_MASK TCR_EL1_EPD1_MASK
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#define TCR_IRGN_NC (TCR_IRGN0_NC | TCR_IRGN1_NC)
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#define TCR_IRGN_WBWA (TCR_IRGN0_WBWA | TCR_IRGN1_WBWA)
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#define TCR_IRGN_WT (TCR_IRGN0_WT | TCR_IRGN1_WT)
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#define TCR_IRGN_WBnWA (TCR_IRGN0_WBnWA | TCR_IRGN1_WBnWA)
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#define TCR_IRGN_MASK (TCR_IRGN0_MASK | TCR_IRGN1_MASK)
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#define TCR_IRGN0_MASK TCR_EL1_IRGN0_MASK
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#define TCR_IRGN0_WBWA (TCR_EL1_IRGN0_WBWA << TCR_EL1_IRGN0_SHIFT)
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#define TCR_ORGN0_MASK TCR_EL1_ORGN0_MASK
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#define TCR_ORGN0_WBWA (TCR_EL1_ORGN0_WBWA << TCR_EL1_ORGN0_SHIFT)
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#define TCR_ORGN0_SHIFT 10
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#define TCR_ORGN0_MASK (UL(3) << TCR_ORGN0_SHIFT)
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#define TCR_ORGN0_NC (UL(0) << TCR_ORGN0_SHIFT)
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#define TCR_ORGN0_WBWA (UL(1) << TCR_ORGN0_SHIFT)
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#define TCR_ORGN0_WT (UL(2) << TCR_ORGN0_SHIFT)
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#define TCR_ORGN0_WBnWA (UL(3) << TCR_ORGN0_SHIFT)
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#define TCR_SH0_MASK TCR_EL1_SH0_MASK
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#define TCR_SH0_INNER (TCR_EL1_SH0_INNER << TCR_EL1_SH0_SHIFT)
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#define TCR_ORGN1_SHIFT 26
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#define TCR_ORGN1_MASK (UL(3) << TCR_ORGN1_SHIFT)
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#define TCR_ORGN1_NC (UL(0) << TCR_ORGN1_SHIFT)
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#define TCR_ORGN1_WBWA (UL(1) << TCR_ORGN1_SHIFT)
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#define TCR_ORGN1_WT (UL(2) << TCR_ORGN1_SHIFT)
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#define TCR_ORGN1_WBnWA (UL(3) << TCR_ORGN1_SHIFT)
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#define TCR_SH1_MASK TCR_EL1_SH1_MASK
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#define TCR_ORGN_NC (TCR_ORGN0_NC | TCR_ORGN1_NC)
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#define TCR_ORGN_WBWA (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)
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#define TCR_ORGN_WT (TCR_ORGN0_WT | TCR_ORGN1_WT)
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#define TCR_ORGN_WBnWA (TCR_ORGN0_WBnWA | TCR_ORGN1_WBnWA)
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#define TCR_ORGN_MASK (TCR_ORGN0_MASK | TCR_ORGN1_MASK)
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#define TCR_TG0_SHIFT TCR_EL1_TG0_SHIFT
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#define TCR_TG0_MASK TCR_EL1_TG0_MASK
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#define TCR_TG0_4K (TCR_EL1_TG0_4K << TCR_EL1_TG0_SHIFT)
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#define TCR_TG0_64K (TCR_EL1_TG0_64K << TCR_EL1_TG0_SHIFT)
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#define TCR_TG0_16K (TCR_EL1_TG0_16K << TCR_EL1_TG0_SHIFT)
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#define TCR_SH0_SHIFT 12
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#define TCR_SH0_MASK (UL(3) << TCR_SH0_SHIFT)
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#define TCR_SH0_INNER (UL(3) << TCR_SH0_SHIFT)
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#define TCR_TG1_SHIFT TCR_EL1_TG1_SHIFT
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#define TCR_TG1_MASK TCR_EL1_TG1_MASK
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#define TCR_TG1_16K (TCR_EL1_TG1_16K << TCR_EL1_TG1_SHIFT)
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#define TCR_TG1_4K (TCR_EL1_TG1_4K << TCR_EL1_TG1_SHIFT)
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#define TCR_TG1_64K (TCR_EL1_TG1_64K << TCR_EL1_TG1_SHIFT)
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#define TCR_SH1_SHIFT 28
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#define TCR_SH1_MASK (UL(3) << TCR_SH1_SHIFT)
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#define TCR_SH1_INNER (UL(3) << TCR_SH1_SHIFT)
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#define TCR_SHARED (TCR_SH0_INNER | TCR_SH1_INNER)
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#define TCR_TG0_SHIFT 14
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#define TCR_TG0_MASK (UL(3) << TCR_TG0_SHIFT)
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#define TCR_TG0_4K (UL(0) << TCR_TG0_SHIFT)
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#define TCR_TG0_64K (UL(1) << TCR_TG0_SHIFT)
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#define TCR_TG0_16K (UL(2) << TCR_TG0_SHIFT)
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#define TCR_TG1_SHIFT 30
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#define TCR_TG1_MASK (UL(3) << TCR_TG1_SHIFT)
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#define TCR_TG1_16K (UL(1) << TCR_TG1_SHIFT)
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#define TCR_TG1_4K (UL(2) << TCR_TG1_SHIFT)
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#define TCR_TG1_64K (UL(3) << TCR_TG1_SHIFT)
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#define TCR_IPS_SHIFT 32
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#define TCR_IPS_MASK (UL(7) << TCR_IPS_SHIFT)
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#define TCR_A1 (UL(1) << 22)
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#define TCR_ASID16 (UL(1) << 36)
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#define TCR_TBI0 (UL(1) << 37)
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#define TCR_TBI1 (UL(1) << 38)
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#define TCR_HA (UL(1) << 39)
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#define TCR_HD (UL(1) << 40)
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#define TCR_HPD0_SHIFT 41
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#define TCR_HPD0 (UL(1) << TCR_HPD0_SHIFT)
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#define TCR_HPD1_SHIFT 42
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#define TCR_HPD1 (UL(1) << TCR_HPD1_SHIFT)
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#define TCR_TBID0 (UL(1) << 51)
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#define TCR_TBID1 (UL(1) << 52)
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#define TCR_NFD0 (UL(1) << 53)
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#define TCR_NFD1 (UL(1) << 54)
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#define TCR_E0PD0 (UL(1) << 55)
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#define TCR_E0PD1 (UL(1) << 56)
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#define TCR_TCMA0 (UL(1) << 57)
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#define TCR_TCMA1 (UL(1) << 58)
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#define TCR_DS (UL(1) << 59)
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#define TCR_IPS_SHIFT TCR_EL1_IPS_SHIFT
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#define TCR_IPS_MASK TCR_EL1_IPS_MASK
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#define TCR_A1 TCR_EL1_A1
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#define TCR_ASID16 TCR_EL1_AS
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#define TCR_TBI0 TCR_EL1_TBI0
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#define TCR_TBI1 TCR_EL1_TBI1
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#define TCR_HA TCR_EL1_HA
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#define TCR_HD TCR_EL1_HD
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#define TCR_HPD0 TCR_EL1_HPD0
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#define TCR_HPD1 TCR_EL1_HPD1
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#define TCR_TBID0 TCR_EL1_TBID0
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#define TCR_TBID1 TCR_EL1_TBID1
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#define TCR_E0PD0 TCR_EL1_E0PD0
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#define TCR_E0PD1 TCR_EL1_E0PD1
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#define TCR_DS TCR_EL1_DS
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/*
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* TTBR.
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@@ -84,7 +84,7 @@ extern unsigned long prot_ns_shared;
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#else
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static inline bool __pure lpa2_is_enabled(void)
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{
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return read_tcr() & TCR_DS;
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return read_tcr() & TCR_EL1_DS;
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}
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#define PTE_MAYBE_SHARED (lpa2_is_enabled() ? 0 : PTE_SHARED)
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@@ -1969,7 +1969,7 @@ static struct cpumask dbm_cpus __read_mostly;
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static inline void __cpu_enable_hw_dbm(void)
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{
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u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
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u64 tcr = read_sysreg(tcr_el1) | TCR_EL1_HD;
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write_sysreg(tcr, tcr_el1);
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isb();
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@@ -2255,7 +2255,7 @@ static bool has_generic_auth(const struct arm64_cpu_capabilities *entry,
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static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap)
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{
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if (this_cpu_has_cap(ARM64_HAS_E0PD))
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sysreg_clear_set(tcr_el1, 0, TCR_E0PD1);
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sysreg_clear_set(tcr_el1, 0, TCR_EL1_E0PD1);
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}
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#endif /* CONFIG_ARM64_E0PD */
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@@ -141,13 +141,13 @@ static void __init map_kernel(u64 kaslr_offset, u64 va_offset, int root_level)
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static void noinline __section(".idmap.text") set_ttbr0_for_lpa2(phys_addr_t ttbr)
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{
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u64 sctlr = read_sysreg(sctlr_el1);
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u64 tcr = read_sysreg(tcr_el1) | TCR_DS;
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u64 tcr = read_sysreg(tcr_el1) | TCR_EL1_DS;
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u64 mmfr0 = read_sysreg(id_aa64mmfr0_el1);
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u64 parange = cpuid_feature_extract_unsigned_field(mmfr0,
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ID_AA64MMFR0_EL1_PARANGE_SHIFT);
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tcr &= ~TCR_IPS_MASK;
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tcr |= parange << TCR_IPS_SHIFT;
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tcr &= ~TCR_EL1_IPS_MASK;
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tcr |= parange << TCR_EL1_IPS_SHIFT;
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asm(" msr sctlr_el1, %0 ;"
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" isb ;"
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@@ -263,7 +263,7 @@ asmlinkage void __init early_map_kernel(u64 boot_status, phys_addr_t fdt)
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}
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if (va_bits > VA_BITS_MIN)
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sysreg_clear_set(tcr_el1, TCR_T1SZ_MASK, TCR_T1SZ(va_bits));
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sysreg_clear_set(tcr_el1, TCR_EL1_T1SZ_MASK, TCR_T1SZ(va_bits));
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/*
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* The virtual KASLR displacement modulo 2MiB is decided by the
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@@ -14,7 +14,7 @@ static inline u64 get_tcr_el1_t1sz(void);
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static inline u64 get_tcr_el1_t1sz(void)
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{
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return (read_sysreg(tcr_el1) & TCR_T1SZ_MASK) >> TCR_T1SZ_OFFSET;
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return (read_sysreg(tcr_el1) & TCR_EL1_T1SZ_MASK) >> TCR_EL1_T1SZ_SHIFT;
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}
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void arch_crash_save_vmcoreinfo(void)
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@@ -23,15 +23,18 @@
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#include <asm/sysreg.h>
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#ifdef CONFIG_ARM64_64K_PAGES
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#define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K
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#define TCR_TG_FLAGS ((TCR_EL1_TG0_64K << TCR_EL1_TG0_SHIFT) |\
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(TCR_EL1_TG1_64K << TCR_EL1_TG1_SHIFT))
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#elif defined(CONFIG_ARM64_16K_PAGES)
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#define TCR_TG_FLAGS TCR_TG0_16K | TCR_TG1_16K
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#define TCR_TG_FLAGS ((TCR_EL1_TG0_16K << TCR_EL1_TG0_SHIFT) |\
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(TCR_EL1_TG1_16K << TCR_EL1_TG1_SHIFT))
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#else /* CONFIG_ARM64_4K_PAGES */
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#define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K
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#define TCR_TG_FLAGS ((TCR_EL1_TG0_4K << TCR_EL1_TG0_SHIFT) |\
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(TCR_EL1_TG1_4K << TCR_EL1_TG1_SHIFT))
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#endif
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#ifdef CONFIG_RANDOMIZE_BASE
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#define TCR_KASLR_FLAGS TCR_NFD1
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#define TCR_KASLR_FLAGS TCR_EL1_NFD1
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#else
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#define TCR_KASLR_FLAGS 0
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#endif
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@@ -40,23 +43,30 @@
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#define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA
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#ifdef CONFIG_KASAN_SW_TAGS
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#define TCR_KASAN_SW_FLAGS TCR_TBI1 | TCR_TBID1
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#define TCR_KASAN_SW_FLAGS TCR_EL1_TBI1 | TCR_EL1_TBID1
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#else
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#define TCR_KASAN_SW_FLAGS 0
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#endif
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#ifdef CONFIG_KASAN_HW_TAGS
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#define TCR_MTE_FLAGS TCR_TCMA1 | TCR_TBI1 | TCR_TBID1
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#define TCR_MTE_FLAGS TCR_EL1_TCMA1 | TCR_EL1_TBI1 | TCR_EL1_TBID1
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#elif defined(CONFIG_ARM64_MTE)
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/*
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* The mte_zero_clear_page_tags() implementation uses DC GZVA, which relies on
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* TBI being enabled at EL1.
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*/
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#define TCR_MTE_FLAGS TCR_TBI1 | TCR_TBID1
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#define TCR_MTE_FLAGS TCR_EL1_TBI1 | TCR_EL1_TBID1
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#else
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#define TCR_MTE_FLAGS 0
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#endif
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#define TCR_IRGN_WBWA ((TCR_EL1_IRGN0_WBWA << TCR_EL1_IRGN0_SHIFT) |\
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(TCR_EL1_IRGN1_WBWA << TCR_EL1_IRGN1_SHIFT))
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#define TCR_ORGN_WBWA ((TCR_EL1_ORGN0_WBWA << TCR_EL1_ORGN0_SHIFT) |\
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(TCR_EL1_ORGN1_WBWA << TCR_EL1_ORGN1_SHIFT))
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#define TCR_SHARED ((TCR_EL1_SH0_INNER << TCR_EL1_SH0_SHIFT) |\
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(TCR_EL1_SH1_INNER << TCR_EL1_SH1_SHIFT))
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/*
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* Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal memory and
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* changed during mte_cpu_setup to Normal Tagged if the system supports MTE.
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@@ -129,7 +139,7 @@ SYM_FUNC_START(cpu_do_resume)
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/* Don't change t0sz here, mask those bits when restoring */
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mrs x7, tcr_el1
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bfi x8, x7, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
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bfi x8, x7, TCR_EL1_T0SZ_SHIFT, TCR_EL1_T0SZ_WIDTH
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msr tcr_el1, x8
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msr vbar_el1, x9
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@@ -481,8 +491,8 @@ SYM_FUNC_START(__cpu_setup)
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tcr2 .req x15
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mov_q mair, MAIR_EL1_SET
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mov_q tcr, TCR_T0SZ(IDMAP_VA_BITS) | TCR_T1SZ(VA_BITS_MIN) | TCR_CACHE_FLAGS | \
|
||||
TCR_SHARED | TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \
|
||||
TCR_TBI0 | TCR_A1 | TCR_KASAN_SW_FLAGS | TCR_MTE_FLAGS
|
||||
TCR_SHARED | TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_EL1_AS | \
|
||||
TCR_EL1_TBI0 | TCR_EL1_A1 | TCR_KASAN_SW_FLAGS | TCR_MTE_FLAGS
|
||||
mov tcr2, xzr
|
||||
|
||||
tcr_clear_errata_bits tcr, x9, x5
|
||||
@@ -492,7 +502,7 @@ SYM_FUNC_START(__cpu_setup)
|
||||
alternative_if ARM64_HAS_VA52
|
||||
tcr_set_t1sz tcr, x9
|
||||
#ifdef CONFIG_ARM64_LPA2
|
||||
orr tcr, tcr, #TCR_DS
|
||||
orr tcr, tcr, #TCR_EL1_DS
|
||||
#endif
|
||||
alternative_else_nop_endif
|
||||
#endif
|
||||
@@ -500,7 +510,7 @@ alternative_else_nop_endif
|
||||
/*
|
||||
* Set the IPS bits in TCR_EL1.
|
||||
*/
|
||||
tcr_compute_pa_size tcr, #TCR_IPS_SHIFT, x5, x6
|
||||
tcr_compute_pa_size tcr, #TCR_EL1_IPS_SHIFT, x5, x6
|
||||
#ifdef CONFIG_ARM64_HW_AFDBM
|
||||
/*
|
||||
* Enable hardware update of the Access Flags bit.
|
||||
@@ -510,7 +520,7 @@ alternative_else_nop_endif
|
||||
mrs x9, ID_AA64MMFR1_EL1
|
||||
ubfx x9, x9, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, #4
|
||||
cbz x9, 1f
|
||||
orr tcr, tcr, #TCR_HA // hardware Access flag update
|
||||
orr tcr, tcr, #TCR_EL1_HA // hardware Access flag update
|
||||
#ifdef CONFIG_ARM64_HAFT
|
||||
cmp x9, ID_AA64MMFR1_EL1_HAFDBS_HAFT
|
||||
b.lt 1f
|
||||
|
||||
Reference in New Issue
Block a user