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Merge tag 'reset-for-v6.19' of https://git.pengutronix.de/git/pza/linux into soc/drivers

Browse Source 
Reset controller updates for v6.19

* Add support for LAN969x, eic770 and RZ/G3S reset controllers,
  for the RZ/G3S USB-PHY reset controller, and for the remaining
  TH1520 reset controllers.
* Drop legacy reset control lookup code.
* Include linux/bits.h from linux/reset.h to make it self-contained.

* tag 'reset-for-v6.19' of https://git.pengutronix.de/git/pza/linux:
  Documentation: reset: Remove reset_controller_add_lookup()
  reset: fix BIT macro reference
  reset: rzg2l-usbphy-ctrl: Fix a NULL vs IS_ERR() bug in probe
  reset: th1520: Support reset controllers in more subsystems
  reset: th1520: Prepare for supporting multiple controllers
  dt-bindings: reset: thead,th1520-reset: Add controllers for more subsys
  dt-bindings: reset: thead,th1520-reset: Remove non-VO-subsystem resets
  reset: remove legacy reset lookup code
  clk: davinci: psc: drop unused reset lookup
  reset: rzg2l-usbphy-ctrl: Add support for RZ/G3S SoC
  reset: rzg2l-usbphy-ctrl: Add support for USB PWRRDY
  dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/G3S support
  reset: eswin: Add eic7700 reset driver
  dt-bindings: reset: eswin: Documentation for eic7700 SoC
  reset: sparx5: add LAN969x support
  dt-bindings: reset: microchip: Add LAN969x support

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2025-11-25 14:11:21 +01:00
parent 73147be308 1387cb78f1
commit af058d5f32
16 changed files with 1936 additions and 189 deletions
Download Patch File Download Diff File Expand all files Collapse all files

42
Documentation/devicetree/bindings/reset/eswin,eic7700-reset.yaml Normal file
View File

@@ -0,0 +1,42 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/reset/eswin,eic7700-reset.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ESWIN EIC7700 SoC reset controller
maintainers:
- Yifeng Huang <huangyifeng@eswincomputing.com>
- Xuyang Dong <dongxuyang@eswincomputing.com>
description:
The system reset controller can be used to reset various peripheral
controllers in ESWIN eic7700 SoC.
properties:
compatible:
const: eswin,eic7700-reset
reg:
maxItems: 1
'#reset-cells':
const: 1
required:
- compatible
- reg
- '#reset-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/reset/eswin,eic7700-reset.h>
reset-controller@51828300 {
compatible = "eswin,eic7700-reset";
reg = <0x51828300 0x200>;
#reset-cells = <1>;
};

11
Documentation/devicetree/bindings/reset/microchip,rst.yaml
View File

@@ -20,9 +20,14 @@ properties:
pattern: "^reset-controller@[0-9a-f]+$"
compatible:
enum:
- microchip,sparx5-switch-reset
- microchip,lan966x-switch-reset
oneOf:
- enum:
- microchip,sparx5-switch-reset
- microchip,lan966x-switch-reset
- items:
- enum:
- microchip,lan9691-switch-reset
- const: microchip,lan966x-switch-reset
reg:
items:

41
Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
View File

@@ -15,12 +15,14 @@ description:
properties:
compatible:
items:
- enum:
- renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five
- renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC}
- renesas,r9a07g054-usbphy-ctrl # RZ/V2L
- const: renesas,rzg2l-usbphy-ctrl
oneOf:
- items:
- enum:
- renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five
- renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC}
- renesas,r9a07g054-usbphy-ctrl # RZ/V2L
- const: renesas,rzg2l-usbphy-ctrl
- const: renesas,r9a08g045-usbphy-ctrl # RZ/G3S
reg:
maxItems: 1
@@ -48,6 +50,20 @@ properties:
$ref: /schemas/regulator/regulator.yaml#
unevaluatedProperties: false
renesas,sysc-pwrrdy:
description:
The system controller PWRRDY indicates to the USB PHY if the power supply
is ready. PWRRDY needs to be set during power-on before applying any
other settings. It also needs to be set before powering off the USB.
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description:
System controller phandle required by USB PHY CTRL driver to set
PWRRDY
- description: Register offset associated with PWRRDY
- description: Register bitmask associated with PWRRDY
required:
- compatible
- reg
@@ -57,6 +73,19 @@ required:
- '#reset-cells'
- regulator-vbus
allOf:
- if:
properties:
compatible:
contains:
const: renesas,r9a08g045-usbphy-ctrl
then:
required:
- renesas,sysc-pwrrdy
else:
properties:
renesas,sysc-pwrrdy: false
additionalProperties: false
examples:

8
Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml
View File

@@ -16,7 +16,13 @@ maintainers:
properties:
compatible:
enum:
- thead,th1520-reset
- thead,th1520-reset # Reset controller for VO subsystem
- thead,th1520-reset-ao
- thead,th1520-reset-ap
- thead,th1520-reset-dsp
- thead,th1520-reset-misc
- thead,th1520-reset-vi
- thead,th1520-reset-vp
reg:
maxItems: 1

1
Documentation/driver-api/reset.rst
View File

@@ -218,4 +218,3 @@ devm_reset_controller_register().
reset_controller_register
reset_controller_unregister
devm_reset_controller_register
reset_controller_add_lookup

7
drivers/clk/davinci/psc-da850.c
View File

@@ -6,7 +6,6 @@
*/
#include <linux/clk-provider.h>
#include <linux/reset-controller.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/init.h>
@@ -66,14 +65,8 @@ LPSC_CLKDEV3(ecap_clkdev, "fck", "ecap.0",
"fck", "ecap.1",
"fck", "ecap.2");
static struct reset_control_lookup da850_psc0_reset_lookup_table[] = {
RESET_LOOKUP("da850-psc0", 15, "davinci-rproc.0", NULL),
};
static int da850_psc0_init(struct device *dev, void __iomem *base)
{
reset_controller_add_lookup(da850_psc0_reset_lookup_table,
ARRAY_SIZE(da850_psc0_reset_lookup_table));
return davinci_psc_register_clocks(dev, da850_psc0_info, 16, base);
}

13
drivers/reset/Kconfig
View File

@@ -73,6 +73,16 @@ config RESET_BRCMSTB_RESCAL
This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
BCM7216 or the BCM2712.
config RESET_EIC7700
bool "Reset controller driver for ESWIN SoCs"
depends on ARCH_ESWIN || COMPILE_TEST
default ARCH_ESWIN
help
This enables the reset controller driver for ESWIN SoCs. This driver is
specific to ESWIN SoCs and should only be enabled if using such hardware.
The driver supports eic7700 series chips and provides functionality for
asserting and deasserting resets on the chip.
config RESET_EYEQ
bool "Mobileye EyeQ reset controller"
depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST
@@ -170,7 +180,7 @@ config RESET_LPC18XX
config RESET_MCHP_SPARX5
tristate "Microchip Sparx5 reset driver"
depends on ARCH_SPARX5 || SOC_LAN966 || MCHP_LAN966X_PCI || COMPILE_TEST
depends on ARCH_SPARX5 || ARCH_LAN969X || SOC_LAN966 || MCHP_LAN966X_PCI || COMPILE_TEST
default y if SPARX5_SWITCH
select MFD_SYSCON
help
@@ -237,6 +247,7 @@ config RESET_RASPBERRYPI
config RESET_RZG2L_USBPHY_CTRL
tristate "Renesas RZ/G2L USBPHY control driver"
depends on ARCH_RZG2L || COMPILE_TEST
select MFD_SYSCON
help
Support for USBPHY Control found on RZ/G2L family. It mainly
controls reset and power down of the USB/PHY.

1
drivers/reset/Makefile
View File

@@ -13,6 +13,7 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o
obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o
obj-$(CONFIG_RESET_EIC7700) += reset-eic7700.o
obj-$(CONFIG_RESET_EYEQ) += reset-eyeq.o
obj-$(CONFIG_RESET_GPIO) += reset-gpio.o
obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o

124
drivers/reset/core.c
View File

@@ -25,9 +25,6 @@
static DEFINE_MUTEX(reset_list_mutex);
static LIST_HEAD(reset_controller_list);
static DEFINE_MUTEX(reset_lookup_mutex);
static LIST_HEAD(reset_lookup_list);
/* Protects reset_gpio_lookup_list */
static DEFINE_MUTEX(reset_gpio_lookup_mutex);
static LIST_HEAD(reset_gpio_lookup_list);
@@ -190,33 +187,6 @@ int devm_reset_controller_register(struct device *dev,
}
EXPORT_SYMBOL_GPL(devm_reset_controller_register);
/**
* reset_controller_add_lookup - register a set of lookup entries
* @lookup: array of reset lookup entries
* @num_entries: number of entries in the lookup array
*/
void reset_controller_add_lookup(struct reset_control_lookup *lookup,
unsigned int num_entries)
{
struct reset_control_lookup *entry;
unsigned int i;
mutex_lock(&reset_lookup_mutex);
for (i = 0; i < num_entries; i++) {
entry = &lookup[i];
if (!entry->dev_id || !entry->provider) {
pr_warn("%s(): reset lookup entry badly specified, skipping\n",
__func__);
continue;
}
list_add_tail(&entry->list, &reset_lookup_list);
}
mutex_unlock(&reset_lookup_mutex);
}
EXPORT_SYMBOL_GPL(reset_controller_add_lookup);
static inline struct reset_control_array *
rstc_to_array(struct reset_control *rstc) {
return container_of(rstc, struct reset_control_array, base);
@@ -1081,75 +1051,12 @@ out_put:
}
EXPORT_SYMBOL_GPL(__of_reset_control_get);
static struct reset_controller_dev *
__reset_controller_by_name(const char *name)
{
struct reset_controller_dev *rcdev;
lockdep_assert_held(&reset_list_mutex);
list_for_each_entry(rcdev, &reset_controller_list, list) {
if (!rcdev->dev)
continue;
if (!strcmp(name, dev_name(rcdev->dev)))
return rcdev;
}
return NULL;
}
static struct reset_control *
__reset_control_get_from_lookup(struct device *dev, const char *con_id,
enum reset_control_flags flags)
{
bool optional = flags & RESET_CONTROL_FLAGS_BIT_OPTIONAL;
const struct reset_control_lookup *lookup;
struct reset_controller_dev *rcdev;
const char *dev_id = dev_name(dev);
struct reset_control *rstc = NULL;
mutex_lock(&reset_lookup_mutex);
list_for_each_entry(lookup, &reset_lookup_list, list) {
if (strcmp(lookup->dev_id, dev_id))
continue;
if ((!con_id && !lookup->con_id) ||
((con_id && lookup->con_id) &&
!strcmp(con_id, lookup->con_id))) {
mutex_lock(&reset_list_mutex);
rcdev = __reset_controller_by_name(lookup->provider);
if (!rcdev) {
mutex_unlock(&reset_list_mutex);
mutex_unlock(&reset_lookup_mutex);
/* Reset provider may not be ready yet. */
return ERR_PTR(-EPROBE_DEFER);
}
flags &= ~RESET_CONTROL_FLAGS_BIT_OPTIONAL;
rstc = __reset_control_get_internal(rcdev,
lookup->index,
flags);
mutex_unlock(&reset_list_mutex);
break;
}
}
mutex_unlock(&reset_lookup_mutex);
if (!rstc)
return optional ? NULL : ERR_PTR(-ENOENT);
return rstc;
}
struct reset_control *__reset_control_get(struct device *dev, const char *id,
int index, enum reset_control_flags flags)
{
bool shared = flags & RESET_CONTROL_FLAGS_BIT_SHARED;
bool acquired = flags & RESET_CONTROL_FLAGS_BIT_ACQUIRED;
bool optional = flags & RESET_CONTROL_FLAGS_BIT_OPTIONAL;
if (WARN_ON(shared && acquired))
return ERR_PTR(-EINVAL);
@@ -1157,7 +1064,7 @@ struct reset_control *__reset_control_get(struct device *dev, const char *id,
if (dev->of_node)
return __of_reset_control_get(dev->of_node, id, index, flags);
return __reset_control_get_from_lookup(dev, id, flags);
return optional ? NULL : ERR_PTR(-ENOENT);
}
EXPORT_SYMBOL_GPL(__reset_control_get);
@@ -1492,31 +1399,6 @@ devm_reset_control_array_get(struct device *dev, enum reset_control_flags flags)
}
EXPORT_SYMBOL_GPL(devm_reset_control_array_get);
static int reset_control_get_count_from_lookup(struct device *dev)
{
const struct reset_control_lookup *lookup;
const char *dev_id;
int count = 0;
if (!dev)
return -EINVAL;
dev_id = dev_name(dev);
mutex_lock(&reset_lookup_mutex);
list_for_each_entry(lookup, &reset_lookup_list, list) {
if (!strcmp(lookup->dev_id, dev_id))
count++;
}
mutex_unlock(&reset_lookup_mutex);
if (count == 0)
count = -ENOENT;
return count;
}
/**
* reset_control_get_count - Count number of resets available with a device
*
@@ -1530,6 +1412,6 @@ int reset_control_get_count(struct device *dev)
if (dev->of_node)
return of_reset_control_get_count(dev->of_node);
return reset_control_get_count_from_lookup(dev);
return -ENOENT;
}
EXPORT_SYMBOL_GPL(reset_control_get_count);

429
drivers/reset/reset-eic7700.c Normal file
View File

@@ -0,0 +1,429 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2025, Beijing ESWIN Computing Technology Co., Ltd..
* All rights reserved.
*
* ESWIN Reset Driver
*
* Authors:
* Yifeng Huang <huangyifeng@eswincomputing.com>
* Xuyang Dong <dongxuyang@eswincomputing.com>
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <dt-bindings/reset/eswin,eic7700-reset.h>
#define SYSCRG_CLEAR_BOOT_INFO_OFFSET 0xC
#define CLEAR_BOOT_FLAG_BIT BIT(0)
#define SYSCRG_RESET_OFFSET 0x100
/**
* struct eic7700_reset_data - reset controller information structure
* @rcdev: reset controller entity
* @regmap: regmap handle containing the memory-mapped reset registers
*/
struct eic7700_reset_data {
struct reset_controller_dev rcdev;
struct regmap *regmap;
};
static const struct regmap_config eic7700_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = 0x1fc,
};
struct eic7700_reg {
u32 reg;
u32 bit;
};
static inline struct eic7700_reset_data *
to_eic7700_reset_data(struct reset_controller_dev *rcdev)
{
return container_of(rcdev, struct eic7700_reset_data, rcdev);
}
#define EIC7700_RESET(id, reg, bit)[id] = \
{ SYSCRG_RESET_OFFSET + (reg) * sizeof(u32), BIT(bit) }
/* mapping table for reset ID to register offset and reset bit */
static const struct eic7700_reg eic7700_reset[] = {
EIC7700_RESET(EIC7700_RESET_NOC_NSP, 0, 0),
EIC7700_RESET(EIC7700_RESET_NOC_CFG, 0, 1),
EIC7700_RESET(EIC7700_RESET_RNOC_NSP, 0, 2),
EIC7700_RESET(EIC7700_RESET_SNOC_TCU, 0, 3),
EIC7700_RESET(EIC7700_RESET_SNOC_U84, 0, 4),
EIC7700_RESET(EIC7700_RESET_SNOC_PCIE_XSR, 0, 5),
EIC7700_RESET(EIC7700_RESET_SNOC_PCIE_XMR, 0, 6),
EIC7700_RESET(EIC7700_RESET_SNOC_PCIE_PR, 0, 7),
EIC7700_RESET(EIC7700_RESET_SNOC_NPU, 0, 8),
EIC7700_RESET(EIC7700_RESET_SNOC_JTAG, 0, 9),
EIC7700_RESET(EIC7700_RESET_SNOC_DSP, 0, 10),
EIC7700_RESET(EIC7700_RESET_SNOC_DDRC1_P2, 0, 11),
EIC7700_RESET(EIC7700_RESET_SNOC_DDRC1_P1, 0, 12),
EIC7700_RESET(EIC7700_RESET_SNOC_DDRC0_P2, 0, 13),
EIC7700_RESET(EIC7700_RESET_SNOC_DDRC0_P1, 0, 14),
EIC7700_RESET(EIC7700_RESET_SNOC_D2D, 0, 15),
EIC7700_RESET(EIC7700_RESET_SNOC_AON, 0, 16),
EIC7700_RESET(EIC7700_RESET_GPU_AXI, 1, 0),
EIC7700_RESET(EIC7700_RESET_GPU_CFG, 1, 1),
EIC7700_RESET(EIC7700_RESET_GPU_GRAY, 1, 2),
EIC7700_RESET(EIC7700_RESET_GPU_JONES, 1, 3),
EIC7700_RESET(EIC7700_RESET_GPU_SPU, 1, 4),
EIC7700_RESET(EIC7700_RESET_DSP_AXI, 2, 0),
EIC7700_RESET(EIC7700_RESET_DSP_CFG, 2, 1),
EIC7700_RESET(EIC7700_RESET_DSP_DIV4, 2, 2),
EIC7700_RESET(EIC7700_RESET_DSP_DIV0, 2, 4),
EIC7700_RESET(EIC7700_RESET_DSP_DIV1, 2, 5),
EIC7700_RESET(EIC7700_RESET_DSP_DIV2, 2, 6),
EIC7700_RESET(EIC7700_RESET_DSP_DIV3, 2, 7),
EIC7700_RESET(EIC7700_RESET_D2D_AXI, 3, 0),
EIC7700_RESET(EIC7700_RESET_D2D_CFG, 3, 1),
EIC7700_RESET(EIC7700_RESET_D2D_PRST, 3, 2),
EIC7700_RESET(EIC7700_RESET_D2D_RAW_PCS, 3, 4),
EIC7700_RESET(EIC7700_RESET_D2D_RX, 3, 5),
EIC7700_RESET(EIC7700_RESET_D2D_TX, 3, 6),
EIC7700_RESET(EIC7700_RESET_D2D_CORE, 3, 7),
EIC7700_RESET(EIC7700_RESET_DDR1_ARST, 4, 0),
EIC7700_RESET(EIC7700_RESET_DDR1_TRACE, 4, 6),
EIC7700_RESET(EIC7700_RESET_DDR0_ARST, 4, 16),
EIC7700_RESET(EIC7700_RESET_DDR_CFG, 4, 21),
EIC7700_RESET(EIC7700_RESET_DDR0_TRACE, 4, 22),
EIC7700_RESET(EIC7700_RESET_DDR_CORE, 4, 23),
EIC7700_RESET(EIC7700_RESET_DDR_PRST, 4, 26),
EIC7700_RESET(EIC7700_RESET_TCU_AXI, 5, 0),
EIC7700_RESET(EIC7700_RESET_TCU_CFG, 5, 1),
EIC7700_RESET(EIC7700_RESET_TCU_TBU0, 5, 4),
EIC7700_RESET(EIC7700_RESET_TCU_TBU1, 5, 5),
EIC7700_RESET(EIC7700_RESET_TCU_TBU2, 5, 6),
EIC7700_RESET(EIC7700_RESET_TCU_TBU3, 5, 7),
EIC7700_RESET(EIC7700_RESET_TCU_TBU4, 5, 8),
EIC7700_RESET(EIC7700_RESET_TCU_TBU5, 5, 9),
EIC7700_RESET(EIC7700_RESET_TCU_TBU6, 5, 10),
EIC7700_RESET(EIC7700_RESET_TCU_TBU7, 5, 11),
EIC7700_RESET(EIC7700_RESET_TCU_TBU8, 5, 12),
EIC7700_RESET(EIC7700_RESET_TCU_TBU9, 5, 13),
EIC7700_RESET(EIC7700_RESET_TCU_TBU10, 5, 14),
EIC7700_RESET(EIC7700_RESET_TCU_TBU11, 5, 15),
EIC7700_RESET(EIC7700_RESET_TCU_TBU12, 5, 16),
EIC7700_RESET(EIC7700_RESET_TCU_TBU13, 5, 17),
EIC7700_RESET(EIC7700_RESET_TCU_TBU14, 5, 18),
EIC7700_RESET(EIC7700_RESET_TCU_TBU15, 5, 19),
EIC7700_RESET(EIC7700_RESET_TCU_TBU16, 5, 20),
EIC7700_RESET(EIC7700_RESET_NPU_AXI, 6, 0),
EIC7700_RESET(EIC7700_RESET_NPU_CFG, 6, 1),
EIC7700_RESET(EIC7700_RESET_NPU_CORE, 6, 2),
EIC7700_RESET(EIC7700_RESET_NPU_E31CORE, 6, 3),
EIC7700_RESET(EIC7700_RESET_NPU_E31BUS, 6, 4),
EIC7700_RESET(EIC7700_RESET_NPU_E31DBG, 6, 5),
EIC7700_RESET(EIC7700_RESET_NPU_LLC, 6, 6),
EIC7700_RESET(EIC7700_RESET_HSP_AXI, 7, 0),
EIC7700_RESET(EIC7700_RESET_HSP_CFG, 7, 1),
EIC7700_RESET(EIC7700_RESET_HSP_POR, 7, 2),
EIC7700_RESET(EIC7700_RESET_MSHC0_PHY, 7, 3),
EIC7700_RESET(EIC7700_RESET_MSHC1_PHY, 7, 4),
EIC7700_RESET(EIC7700_RESET_MSHC2_PHY, 7, 5),
EIC7700_RESET(EIC7700_RESET_MSHC0_TXRX, 7, 6),
EIC7700_RESET(EIC7700_RESET_MSHC1_TXRX, 7, 7),
EIC7700_RESET(EIC7700_RESET_MSHC2_TXRX, 7, 8),
EIC7700_RESET(EIC7700_RESET_SATA_ASIC0, 7, 9),
EIC7700_RESET(EIC7700_RESET_SATA_OOB, 7, 10),
EIC7700_RESET(EIC7700_RESET_SATA_PMALIVE, 7, 11),
EIC7700_RESET(EIC7700_RESET_SATA_RBC, 7, 12),
EIC7700_RESET(EIC7700_RESET_DMA0, 7, 13),
EIC7700_RESET(EIC7700_RESET_HSP_DMA, 7, 14),
EIC7700_RESET(EIC7700_RESET_USB0_VAUX, 7, 15),
EIC7700_RESET(EIC7700_RESET_USB1_VAUX, 7, 16),
EIC7700_RESET(EIC7700_RESET_HSP_SD1_PRST, 7, 17),
EIC7700_RESET(EIC7700_RESET_HSP_SD0_PRST, 7, 18),
EIC7700_RESET(EIC7700_RESET_HSP_EMMC_PRST, 7, 19),
EIC7700_RESET(EIC7700_RESET_HSP_DMA_PRST, 7, 20),
EIC7700_RESET(EIC7700_RESET_HSP_SD1_ARST, 7, 21),
EIC7700_RESET(EIC7700_RESET_HSP_SD0_ARST, 7, 22),
EIC7700_RESET(EIC7700_RESET_HSP_EMMC_ARST, 7, 23),
EIC7700_RESET(EIC7700_RESET_HSP_DMA_ARST, 7, 24),
EIC7700_RESET(EIC7700_RESET_HSP_ETH1_ARST, 7, 25),
EIC7700_RESET(EIC7700_RESET_HSP_ETH0_ARST, 7, 26),
EIC7700_RESET(EIC7700_RESET_SATA_ARST, 7, 27),
EIC7700_RESET(EIC7700_RESET_PCIE_CFG, 8, 0),
EIC7700_RESET(EIC7700_RESET_PCIE_POWEUP, 8, 1),
EIC7700_RESET(EIC7700_RESET_PCIE_PERST, 8, 2),
EIC7700_RESET(EIC7700_RESET_I2C0, 9, 0),
EIC7700_RESET(EIC7700_RESET_I2C1, 9, 1),
EIC7700_RESET(EIC7700_RESET_I2C2, 9, 2),
EIC7700_RESET(EIC7700_RESET_I2C3, 9, 3),
EIC7700_RESET(EIC7700_RESET_I2C4, 9, 4),
EIC7700_RESET(EIC7700_RESET_I2C5, 9, 5),
EIC7700_RESET(EIC7700_RESET_I2C6, 9, 6),
EIC7700_RESET(EIC7700_RESET_I2C7, 9, 7),
EIC7700_RESET(EIC7700_RESET_I2C8, 9, 8),
EIC7700_RESET(EIC7700_RESET_I2C9, 9, 9),
EIC7700_RESET(EIC7700_RESET_FAN, 10, 0),
EIC7700_RESET(EIC7700_RESET_PVT0, 11, 0),
EIC7700_RESET(EIC7700_RESET_PVT1, 11, 1),
EIC7700_RESET(EIC7700_RESET_MBOX0, 12, 0),
EIC7700_RESET(EIC7700_RESET_MBOX1, 12, 1),
EIC7700_RESET(EIC7700_RESET_MBOX2, 12, 2),
EIC7700_RESET(EIC7700_RESET_MBOX3, 12, 3),
EIC7700_RESET(EIC7700_RESET_MBOX4, 12, 4),
EIC7700_RESET(EIC7700_RESET_MBOX5, 12, 5),
EIC7700_RESET(EIC7700_RESET_MBOX6, 12, 6),
EIC7700_RESET(EIC7700_RESET_MBOX7, 12, 7),
EIC7700_RESET(EIC7700_RESET_MBOX8, 12, 8),
EIC7700_RESET(EIC7700_RESET_MBOX9, 12, 9),
EIC7700_RESET(EIC7700_RESET_MBOX10, 12, 10),
EIC7700_RESET(EIC7700_RESET_MBOX11, 12, 11),
EIC7700_RESET(EIC7700_RESET_MBOX12, 12, 12),
EIC7700_RESET(EIC7700_RESET_MBOX13, 12, 13),
EIC7700_RESET(EIC7700_RESET_MBOX14, 12, 14),
EIC7700_RESET(EIC7700_RESET_MBOX15, 12, 15),
EIC7700_RESET(EIC7700_RESET_UART0, 13, 0),
EIC7700_RESET(EIC7700_RESET_UART1, 13, 1),
EIC7700_RESET(EIC7700_RESET_UART2, 13, 2),
EIC7700_RESET(EIC7700_RESET_UART3, 13, 3),
EIC7700_RESET(EIC7700_RESET_UART4, 13, 4),
EIC7700_RESET(EIC7700_RESET_GPIO0, 14, 0),
EIC7700_RESET(EIC7700_RESET_GPIO1, 14, 1),
EIC7700_RESET(EIC7700_RESET_TIMER, 15, 0),
EIC7700_RESET(EIC7700_RESET_SSI0, 16, 0),
EIC7700_RESET(EIC7700_RESET_SSI1, 16, 1),
EIC7700_RESET(EIC7700_RESET_WDT0, 17, 0),
EIC7700_RESET(EIC7700_RESET_WDT1, 17, 1),
EIC7700_RESET(EIC7700_RESET_WDT2, 17, 2),
EIC7700_RESET(EIC7700_RESET_WDT3, 17, 3),
EIC7700_RESET(EIC7700_RESET_LSP_CFG, 18, 0),
EIC7700_RESET(EIC7700_RESET_U84_CORE0, 19, 0),
EIC7700_RESET(EIC7700_RESET_U84_CORE1, 19, 1),
EIC7700_RESET(EIC7700_RESET_U84_CORE2, 19, 2),
EIC7700_RESET(EIC7700_RESET_U84_CORE3, 19, 3),
EIC7700_RESET(EIC7700_RESET_U84_BUS, 19, 4),
EIC7700_RESET(EIC7700_RESET_U84_DBG, 19, 5),
EIC7700_RESET(EIC7700_RESET_U84_TRACECOM, 19, 6),
EIC7700_RESET(EIC7700_RESET_U84_TRACE0, 19, 8),
EIC7700_RESET(EIC7700_RESET_U84_TRACE1, 19, 9),
EIC7700_RESET(EIC7700_RESET_U84_TRACE2, 19, 10),
EIC7700_RESET(EIC7700_RESET_U84_TRACE3, 19, 11),
EIC7700_RESET(EIC7700_RESET_SCPU_CORE, 20, 0),
EIC7700_RESET(EIC7700_RESET_SCPU_BUS, 20, 1),
EIC7700_RESET(EIC7700_RESET_SCPU_DBG, 20, 2),
EIC7700_RESET(EIC7700_RESET_LPCPU_CORE, 21, 0),
EIC7700_RESET(EIC7700_RESET_LPCPU_BUS, 21, 1),
EIC7700_RESET(EIC7700_RESET_LPCPU_DBG, 21, 2),
EIC7700_RESET(EIC7700_RESET_VC_CFG, 22, 0),
EIC7700_RESET(EIC7700_RESET_VC_AXI, 22, 1),
EIC7700_RESET(EIC7700_RESET_VC_MONCFG, 22, 2),
EIC7700_RESET(EIC7700_RESET_JD_CFG, 23, 0),
EIC7700_RESET(EIC7700_RESET_JD_AXI, 23, 1),
EIC7700_RESET(EIC7700_RESET_JE_CFG, 24, 0),
EIC7700_RESET(EIC7700_RESET_JE_AXI, 24, 1),
EIC7700_RESET(EIC7700_RESET_VD_CFG, 25, 0),
EIC7700_RESET(EIC7700_RESET_VD_AXI, 25, 1),
EIC7700_RESET(EIC7700_RESET_VE_AXI, 26, 0),
EIC7700_RESET(EIC7700_RESET_VE_CFG, 26, 1),
EIC7700_RESET(EIC7700_RESET_G2D_CORE, 27, 0),
EIC7700_RESET(EIC7700_RESET_G2D_CFG, 27, 1),
EIC7700_RESET(EIC7700_RESET_G2D_AXI, 27, 2),
EIC7700_RESET(EIC7700_RESET_VI_AXI, 28, 0),
EIC7700_RESET(EIC7700_RESET_VI_CFG, 28, 1),
EIC7700_RESET(EIC7700_RESET_VI_DWE, 28, 2),
EIC7700_RESET(EIC7700_RESET_DVP, 29, 0),
EIC7700_RESET(EIC7700_RESET_ISP0, 30, 0),
EIC7700_RESET(EIC7700_RESET_ISP1, 31, 0),
EIC7700_RESET(EIC7700_RESET_SHUTTR0, 32, 0),
EIC7700_RESET(EIC7700_RESET_SHUTTR1, 32, 1),
EIC7700_RESET(EIC7700_RESET_SHUTTR2, 32, 2),
EIC7700_RESET(EIC7700_RESET_SHUTTR3, 32, 3),
EIC7700_RESET(EIC7700_RESET_SHUTTR4, 32, 4),
EIC7700_RESET(EIC7700_RESET_SHUTTR5, 32, 5),
EIC7700_RESET(EIC7700_RESET_VO_MIPI, 33, 0),
EIC7700_RESET(EIC7700_RESET_VO_PRST, 33, 1),
EIC7700_RESET(EIC7700_RESET_VO_HDMI_PRST, 33, 3),
EIC7700_RESET(EIC7700_RESET_VO_HDMI_PHY, 33, 4),
EIC7700_RESET(EIC7700_RESET_VO_HDMI, 33, 5),
EIC7700_RESET(EIC7700_RESET_VO_I2S, 34, 0),
EIC7700_RESET(EIC7700_RESET_VO_I2S_PRST, 34, 1),
EIC7700_RESET(EIC7700_RESET_VO_AXI, 35, 0),
EIC7700_RESET(EIC7700_RESET_VO_CFG, 35, 1),
EIC7700_RESET(EIC7700_RESET_VO_DC, 35, 2),
EIC7700_RESET(EIC7700_RESET_VO_DC_PRST, 35, 3),
EIC7700_RESET(EIC7700_RESET_BOOTSPI_HRST, 36, 0),
EIC7700_RESET(EIC7700_RESET_BOOTSPI, 36, 1),
EIC7700_RESET(EIC7700_RESET_ANO1, 37, 0),
EIC7700_RESET(EIC7700_RESET_ANO0, 38, 0),
EIC7700_RESET(EIC7700_RESET_DMA1_ARST, 39, 0),
EIC7700_RESET(EIC7700_RESET_DMA1_HRST, 39, 1),
EIC7700_RESET(EIC7700_RESET_FPRT, 40, 0),
EIC7700_RESET(EIC7700_RESET_HBLOCK, 41, 0),
EIC7700_RESET(EIC7700_RESET_SECSR, 42, 0),
EIC7700_RESET(EIC7700_RESET_OTP, 43, 0),
EIC7700_RESET(EIC7700_RESET_PKA, 44, 0),
EIC7700_RESET(EIC7700_RESET_SPACC, 45, 0),
EIC7700_RESET(EIC7700_RESET_TRNG, 46, 0),
EIC7700_RESET(EIC7700_RESET_TIMER0_0, 48, 0),
EIC7700_RESET(EIC7700_RESET_TIMER0_1, 48, 1),
EIC7700_RESET(EIC7700_RESET_TIMER0_2, 48, 2),
EIC7700_RESET(EIC7700_RESET_TIMER0_3, 48, 3),
EIC7700_RESET(EIC7700_RESET_TIMER0_4, 48, 4),
EIC7700_RESET(EIC7700_RESET_TIMER0_5, 48, 5),
EIC7700_RESET(EIC7700_RESET_TIMER0_6, 48, 6),
EIC7700_RESET(EIC7700_RESET_TIMER0_7, 48, 7),
EIC7700_RESET(EIC7700_RESET_TIMER0_N, 48, 8),
EIC7700_RESET(EIC7700_RESET_TIMER1_0, 49, 0),
EIC7700_RESET(EIC7700_RESET_TIMER1_1, 49, 1),
EIC7700_RESET(EIC7700_RESET_TIMER1_2, 49, 2),
EIC7700_RESET(EIC7700_RESET_TIMER1_3, 49, 3),
EIC7700_RESET(EIC7700_RESET_TIMER1_4, 49, 4),
EIC7700_RESET(EIC7700_RESET_TIMER1_5, 49, 5),
EIC7700_RESET(EIC7700_RESET_TIMER1_6, 49, 6),
EIC7700_RESET(EIC7700_RESET_TIMER1_7, 49, 7),
EIC7700_RESET(EIC7700_RESET_TIMER1_N, 49, 8),
EIC7700_RESET(EIC7700_RESET_TIMER2_0, 50, 0),
EIC7700_RESET(EIC7700_RESET_TIMER2_1, 50, 1),
EIC7700_RESET(EIC7700_RESET_TIMER2_2, 50, 2),
EIC7700_RESET(EIC7700_RESET_TIMER2_3, 50, 3),
EIC7700_RESET(EIC7700_RESET_TIMER2_4, 50, 4),
EIC7700_RESET(EIC7700_RESET_TIMER2_5, 50, 5),
EIC7700_RESET(EIC7700_RESET_TIMER2_6, 50, 6),
EIC7700_RESET(EIC7700_RESET_TIMER2_7, 50, 7),
EIC7700_RESET(EIC7700_RESET_TIMER2_N, 50, 8),
EIC7700_RESET(EIC7700_RESET_TIMER3_0, 51, 0),
EIC7700_RESET(EIC7700_RESET_TIMER3_1, 51, 1),
EIC7700_RESET(EIC7700_RESET_TIMER3_2, 51, 2),
EIC7700_RESET(EIC7700_RESET_TIMER3_3, 51, 3),
EIC7700_RESET(EIC7700_RESET_TIMER3_4, 51, 4),
EIC7700_RESET(EIC7700_RESET_TIMER3_5, 51, 5),
EIC7700_RESET(EIC7700_RESET_TIMER3_6, 51, 6),
EIC7700_RESET(EIC7700_RESET_TIMER3_7, 51, 7),
EIC7700_RESET(EIC7700_RESET_TIMER3_N, 51, 8),
EIC7700_RESET(EIC7700_RESET_RTC, 52, 0),
EIC7700_RESET(EIC7700_RESET_MNOC_SNOC_NSP, 53, 0),
EIC7700_RESET(EIC7700_RESET_MNOC_VC, 53, 1),
EIC7700_RESET(EIC7700_RESET_MNOC_CFG, 53, 2),
EIC7700_RESET(EIC7700_RESET_MNOC_HSP, 53, 3),
EIC7700_RESET(EIC7700_RESET_MNOC_GPU, 53, 4),
EIC7700_RESET(EIC7700_RESET_MNOC_DDRC1_P3, 53, 5),
EIC7700_RESET(EIC7700_RESET_MNOC_DDRC0_P3, 53, 6),
EIC7700_RESET(EIC7700_RESET_RNOC_VO, 54, 0),
EIC7700_RESET(EIC7700_RESET_RNOC_VI, 54, 1),
EIC7700_RESET(EIC7700_RESET_RNOC_SNOC_NSP, 54, 2),
EIC7700_RESET(EIC7700_RESET_RNOC_CFG, 54, 3),
EIC7700_RESET(EIC7700_RESET_MNOC_DDRC1_P4, 54, 4),
EIC7700_RESET(EIC7700_RESET_MNOC_DDRC0_P4, 54, 5),
EIC7700_RESET(EIC7700_RESET_CNOC_VO_CFG, 55, 0),
EIC7700_RESET(EIC7700_RESET_CNOC_VI_CFG, 55, 1),
EIC7700_RESET(EIC7700_RESET_CNOC_VC_CFG, 55, 2),
EIC7700_RESET(EIC7700_RESET_CNOC_TCU_CFG, 55, 3),
EIC7700_RESET(EIC7700_RESET_CNOC_PCIE_CFG, 55, 4),
EIC7700_RESET(EIC7700_RESET_CNOC_NPU_CFG, 55, 5),
EIC7700_RESET(EIC7700_RESET_CNOC_LSP_CFG, 55, 6),
EIC7700_RESET(EIC7700_RESET_CNOC_HSP_CFG, 55, 7),
EIC7700_RESET(EIC7700_RESET_CNOC_GPU_CFG, 55, 8),
EIC7700_RESET(EIC7700_RESET_CNOC_DSPT_CFG, 55, 9),
EIC7700_RESET(EIC7700_RESET_CNOC_DDRT1_CFG, 55, 10),
EIC7700_RESET(EIC7700_RESET_CNOC_DDRT0_CFG, 55, 11),
EIC7700_RESET(EIC7700_RESET_CNOC_D2D_CFG, 55, 12),
EIC7700_RESET(EIC7700_RESET_CNOC_CFG, 55, 13),
EIC7700_RESET(EIC7700_RESET_CNOC_CLMM_CFG, 55, 14),
EIC7700_RESET(EIC7700_RESET_CNOC_AON_CFG, 55, 15),
EIC7700_RESET(EIC7700_RESET_LNOC_CFG, 56, 0),
EIC7700_RESET(EIC7700_RESET_LNOC_NPU_LLC, 56, 1),
EIC7700_RESET(EIC7700_RESET_LNOC_DDRC1_P0, 56, 2),
EIC7700_RESET(EIC7700_RESET_LNOC_DDRC0_P0, 56, 3),
};
static int eic7700_reset_assert(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct eic7700_reset_data *data = to_eic7700_reset_data(rcdev);
return regmap_clear_bits(data->regmap, eic7700_reset[id].reg,
eic7700_reset[id].bit);
}
static int eic7700_reset_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct eic7700_reset_data *data = to_eic7700_reset_data(rcdev);
return regmap_set_bits(data->regmap, eic7700_reset[id].reg,
eic7700_reset[id].bit);
}
static int eic7700_reset_reset(struct reset_controller_dev *rcdev,
unsigned long id)
{
int ret;
ret = eic7700_reset_assert(rcdev, id);
if (ret)
return ret;
usleep_range(10, 15);
return eic7700_reset_deassert(rcdev, id);
}
static const struct reset_control_ops eic7700_reset_ops = {
.reset = eic7700_reset_reset,
.assert = eic7700_reset_assert,
.deassert = eic7700_reset_deassert,
};
static const struct of_device_id eic7700_reset_dt_ids[] = {
{ .compatible = "eswin,eic7700-reset", },
{ /* sentinel */ }
};
static int eic7700_reset_probe(struct platform_device *pdev)
{
struct eic7700_reset_data *data;
struct device *dev = &pdev->dev;
void __iomem *base;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
data->regmap = devm_regmap_init_mmio(dev, base, &eic7700_regmap_config);
if (IS_ERR(data->regmap))
return dev_err_probe(dev, PTR_ERR(data->regmap),
"failed to get regmap!\n");
data->rcdev.owner = THIS_MODULE;
data->rcdev.ops = &eic7700_reset_ops;
data->rcdev.of_node = dev->of_node;
data->rcdev.of_reset_n_cells = 1;
data->rcdev.dev = dev;
data->rcdev.nr_resets = ARRAY_SIZE(eic7700_reset);
/* clear boot flag so u84 and scpu could be reseted by software */
regmap_set_bits(data->regmap, SYSCRG_CLEAR_BOOT_INFO_OFFSET,
CLEAR_BOOT_FLAG_BIT);
msleep(50);
return devm_reset_controller_register(dev, &data->rcdev);
}
static struct platform_driver eic7700_reset_driver = {
.probe = eic7700_reset_probe,
.driver = {
.name = "eic7700-reset",
.of_match_table = eic7700_reset_dt_ids,
},
};
builtin_platform_driver(eic7700_reset_driver);

60
drivers/reset/reset-rzg2l-usbphy-ctrl.c
View File

@@ -13,6 +13,7 @@
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/reset-controller.h>
#include <linux/mfd/syscon.h>
#define RESET 0x000
#define VBENCTL 0x03c
@@ -91,8 +92,14 @@ static int rzg2l_usbphy_ctrl_status(struct reset_controller_dev *rcdev,
return !!(readl(priv->base + RESET) & port_mask);
}
#define RZG2L_USBPHY_CTRL_PWRRDY 1
static const struct of_device_id rzg2l_usbphy_ctrl_match_table[] = {
{ .compatible = "renesas,rzg2l-usbphy-ctrl" },
{
.compatible = "renesas,r9a08g045-usbphy-ctrl",
.data = (void *)RZG2L_USBPHY_CTRL_PWRRDY
},
{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, rzg2l_usbphy_ctrl_match_table);
@@ -110,6 +117,55 @@ static const struct regmap_config rzg2l_usb_regconf = {
.max_register = 1,
};
static void rzg2l_usbphy_ctrl_set_pwrrdy(struct regmap_field *pwrrdy,
bool power_on)
{
u32 val = power_on ? 0 : 1;
/* The initialization path guarantees that the mask is 1 bit long. */
regmap_field_update_bits(pwrrdy, 1, val);
}
static void rzg2l_usbphy_ctrl_pwrrdy_off(void *data)
{
rzg2l_usbphy_ctrl_set_pwrrdy(data, false);
}
static int rzg2l_usbphy_ctrl_pwrrdy_init(struct device *dev)
{
struct regmap_field *pwrrdy;
struct reg_field field;
struct regmap *regmap;
const int *data;
u32 args[2];
data = device_get_match_data(dev);
if ((uintptr_t)data != RZG2L_USBPHY_CTRL_PWRRDY)
return 0;
regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node,
"renesas,sysc-pwrrdy",
ARRAY_SIZE(args), args);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* Don't allow more than one bit in mask. */
if (hweight32(args[1]) != 1)
return -EINVAL;
field.reg = args[0];
field.lsb = __ffs(args[1]);
field.msb = __fls(args[1]);
pwrrdy = devm_regmap_field_alloc(dev, regmap, field);
if (IS_ERR(pwrrdy))
return PTR_ERR(pwrrdy);
rzg2l_usbphy_ctrl_set_pwrrdy(pwrrdy, true);
return devm_add_action_or_reset(dev, rzg2l_usbphy_ctrl_pwrrdy_off, pwrrdy);
}
static int rzg2l_usbphy_ctrl_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -132,6 +188,10 @@ static int rzg2l_usbphy_ctrl_probe(struct platform_device *pdev)
if (IS_ERR(regmap))
return PTR_ERR(regmap);
error = rzg2l_usbphy_ctrl_pwrrdy_init(dev);
if (error)
return error;
priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
if (IS_ERR(priv->rstc))
return dev_err_probe(dev, PTR_ERR(priv->rstc),

837
drivers/reset/reset-th1520.c
View File

@@ -11,6 +11,85 @@
#include <dt-bindings/reset/thead,th1520-reset.h>
/* register offset in RSTGEN_R */
#define TH1520_BROM_RST_CFG 0x0
#define TH1520_C910_RST_CFG 0x4
#define TH1520_CHIP_DBG_RST_CFG 0xc
#define TH1520_AXI4_CPUSYS2_RST_CFG 0x10
#define TH1520_X2H_CPUSYS_RST_CFG 0x18
#define TH1520_AHB2_CPUSYS_RST_CFG 0x1c
#define TH1520_APB3_CPUSYS_RST_CFG 0x20
#define TH1520_MBOX0_RST_CFG 0x24
#define TH1520_MBOX1_RST_CFG 0x28
#define TH1520_MBOX2_RST_CFG 0x2c
#define TH1520_MBOX3_RST_CFG 0x30
#define TH1520_WDT0_RST_CFG 0x34
#define TH1520_WDT1_RST_CFG 0x38
#define TH1520_TIMER0_RST_CFG 0x3c
#define TH1520_TIMER1_RST_CFG 0x40
#define TH1520_PERISYS_AHB_RST_CFG 0x44
#define TH1520_PERISYS_APB1_RST_CFG 0x48
#define TH1520_PERISYS_APB2_RST_CFG 0x4c
#define TH1520_GMAC0_RST_CFG 0x68
#define TH1520_UART0_RST_CFG 0x70
#define TH1520_UART1_RST_CFG 0x74
#define TH1520_UART2_RST_CFG 0x78
#define TH1520_UART3_RST_CFG 0x7c
#define TH1520_UART4_RST_CFG 0x80
#define TH1520_UART5_RST_CFG 0x84
#define TH1520_QSPI0_RST_CFG 0x8c
#define TH1520_QSPI1_RST_CFG 0x90
#define TH1520_SPI_RST_CFG 0x94
#define TH1520_I2C0_RST_CFG 0x98
#define TH1520_I2C1_RST_CFG 0x9c
#define TH1520_I2C2_RST_CFG 0xa0
#define TH1520_I2C3_RST_CFG 0xa4
#define TH1520_I2C4_RST_CFG 0xa8
#define TH1520_I2C5_RST_CFG 0xac
#define TH1520_GPIO0_RST_CFG 0xb0
#define TH1520_GPIO1_RST_CFG 0xb4
#define TH1520_GPIO2_RST_CFG 0xb8
#define TH1520_PWM_RST_CFG 0xc0
#define TH1520_PADCTRL0_APSYS_RST_CFG 0xc4
#define TH1520_CPU2PERI_X2H_RST_CFG 0xcc
#define TH1520_CPU2AON_X2H_RST_CFG 0xe4
#define TH1520_AON2CPU_A2X_RST_CFG 0xfc
#define TH1520_NPUSYS_AXI_RST_CFG 0x128
#define TH1520_CPU2VP_X2P_RST_CFG 0x12c
#define TH1520_CPU2VI_X2H_RST_CFG 0x138
#define TH1520_BMU_C910_RST_CFG 0x148
#define TH1520_DMAC_CPUSYS_RST_CFG 0x14c
#define TH1520_SPINLOCK_RST_CFG 0x178
#define TH1520_CFG2TEE_X2H_RST_CFG 0x188
#define TH1520_DSMART_RST_CFG 0x18c
#define TH1520_GPIO3_RST_CFG 0x1a8
#define TH1520_I2S_RST_CFG 0x1ac
#define TH1520_IMG_NNA_RST_CFG 0x1b0
#define TH1520_PERI_APB3_RST_CFG 0x1dc
#define TH1520_VP_SUBSYS_RST_CFG 0x1ec
#define TH1520_PERISYS_APB4_RST_CFG 0x1f8
#define TH1520_GMAC1_RST_CFG 0x204
#define TH1520_GMAC_AXI_RST_CFG 0x208
#define TH1520_PADCTRL1_APSYS_RST_CFG 0x20c
#define TH1520_VOSYS_AXI_RST_CFG 0x210
#define TH1520_VOSYS_X2X_RST_CFG 0x214
#define TH1520_MISC2VP_X2X_RST_CFG 0x218
#define TH1520_SUBSYS_RST_CFG 0x220
/* register offset in DSP_REGMAP */
#define TH1520_DSPSYS_RST_CFG 0x0
/* register offset in MISCSYS_REGMAP */
#define TH1520_EMMC_RST_CFG 0x0
#define TH1520_MISCSYS_AXI_RST_CFG 0x8
#define TH1520_SDIO0_RST_CFG 0xc
#define TH1520_SDIO1_RST_CFG 0x10
#define TH1520_USB3_DRD_RST_CFG 0x14
/* register offset in VISYS_REGMAP */
#define TH1520_VISYS_RST_CFG 0x0
#define TH1520_VISYS_2_RST_CFG 0x4
/* register offset in VOSYS_REGMAP */
#define TH1520_GPU_RST_CFG 0x0
#define TH1520_GPU_RST_CFG_MASK GENMASK(1, 0)
@@ -18,6 +97,8 @@
#define TH1520_DSI0_RST_CFG 0x8
#define TH1520_DSI1_RST_CFG 0xc
#define TH1520_HDMI_RST_CFG 0x14
#define TH1520_AXI4_VO_DW_AXI_RST_CFG 0x18
#define TH1520_X2H_X4_VOSYS_DW_RST_CFG 0x20
/* register values */
#define TH1520_GPU_SW_GPU_RST BIT(0)
@@ -29,16 +110,29 @@
#define TH1520_HDMI_SW_MAIN_RST BIT(0)
#define TH1520_HDMI_SW_PRST BIT(1)
struct th1520_reset_priv {
struct reset_controller_dev rcdev;
struct regmap *map;
};
/* register offset in VPSYS_REGMAP */
#define TH1520_AXIBUS_RST_CFG 0x0
#define TH1520_FCE_RST_CFG 0x4
#define TH1520_G2D_RST_CFG 0x8
#define TH1520_VDEC_RST_CFG 0xc
#define TH1520_VENC_RST_CFG 0x10
struct th1520_reset_map {
u32 bit;
u32 reg;
};
struct th1520_reset_priv {
struct reset_controller_dev rcdev;
struct regmap *map;
const struct th1520_reset_map *resets;
};
struct th1520_reset_data {
const struct th1520_reset_map *resets;
size_t num;
};
static const struct th1520_reset_map th1520_resets[] = {
[TH1520_RESET_ID_GPU] = {
.bit = TH1520_GPU_SW_GPU_RST,
@@ -76,6 +170,681 @@ static const struct th1520_reset_map th1520_resets[] = {
.bit = TH1520_HDMI_SW_PRST,
.reg = TH1520_HDMI_RST_CFG,
},
[TH1520_RESET_ID_VOAXI] = {
.bit = BIT(0),
.reg = TH1520_AXI4_VO_DW_AXI_RST_CFG,
},
[TH1520_RESET_ID_VOAXI_APB] = {
.bit = BIT(1),
.reg = TH1520_AXI4_VO_DW_AXI_RST_CFG,
},
[TH1520_RESET_ID_X2H_DPU_AXI] = {
.bit = BIT(0),
.reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG,
},
[TH1520_RESET_ID_X2H_DPU_AHB] = {
.bit = BIT(1),
.reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG,
},
[TH1520_RESET_ID_X2H_DPU1_AXI] = {
.bit = BIT(2),
.reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG,
},
[TH1520_RESET_ID_X2H_DPU1_AHB] = {
.bit = BIT(3),
.reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG,
},
};
static const struct th1520_reset_map th1520_ap_resets[] = {
[TH1520_RESET_ID_BROM] = {
.bit = BIT(0),
.reg = TH1520_BROM_RST_CFG,
},
[TH1520_RESET_ID_C910_TOP] = {
.bit = BIT(0),
.reg = TH1520_C910_RST_CFG,
},
[TH1520_RESET_ID_NPU] = {
.bit = BIT(0),
.reg = TH1520_IMG_NNA_RST_CFG,
},
[TH1520_RESET_ID_WDT0] = {
.bit = BIT(0),
.reg = TH1520_WDT0_RST_CFG,
},
[TH1520_RESET_ID_WDT1] = {
.bit = BIT(0),
.reg = TH1520_WDT1_RST_CFG,
},
[TH1520_RESET_ID_C910_C0] = {
.bit = BIT(1),
.reg = TH1520_C910_RST_CFG,
},
[TH1520_RESET_ID_C910_C1] = {
.bit = BIT(2),
.reg = TH1520_C910_RST_CFG,
},
[TH1520_RESET_ID_C910_C2] = {
.bit = BIT(3),
.reg = TH1520_C910_RST_CFG,
},
[TH1520_RESET_ID_C910_C3] = {
.bit = BIT(4),
.reg = TH1520_C910_RST_CFG,
},
[TH1520_RESET_ID_CHIP_DBG_CORE] = {
.bit = BIT(0),
.reg = TH1520_CHIP_DBG_RST_CFG,
},
[TH1520_RESET_ID_CHIP_DBG_AXI] = {
.bit = BIT(1),
.reg = TH1520_CHIP_DBG_RST_CFG,
},
[TH1520_RESET_ID_AXI4_CPUSYS2_AXI] = {
.bit = BIT(0),
.reg = TH1520_AXI4_CPUSYS2_RST_CFG,
},
[TH1520_RESET_ID_AXI4_CPUSYS2_APB] = {
.bit = BIT(1),
.reg = TH1520_AXI4_CPUSYS2_RST_CFG,
},
[TH1520_RESET_ID_X2H_CPUSYS] = {
.bit = BIT(0),
.reg = TH1520_X2H_CPUSYS_RST_CFG,
},
[TH1520_RESET_ID_AHB2_CPUSYS] = {
.bit = BIT(0),
.reg = TH1520_AHB2_CPUSYS_RST_CFG,
},
[TH1520_RESET_ID_APB3_CPUSYS] = {
.bit = BIT(0),
.reg = TH1520_APB3_CPUSYS_RST_CFG,
},
[TH1520_RESET_ID_MBOX0_APB] = {
.bit = BIT(0),
.reg = TH1520_MBOX0_RST_CFG,
},
[TH1520_RESET_ID_MBOX1_APB] = {
.bit = BIT(0),
.reg = TH1520_MBOX1_RST_CFG,
},
[TH1520_RESET_ID_MBOX2_APB] = {
.bit = BIT(0),
.reg = TH1520_MBOX2_RST_CFG,
},
[TH1520_RESET_ID_MBOX3_APB] = {
.bit = BIT(0),
.reg = TH1520_MBOX3_RST_CFG,
},
[TH1520_RESET_ID_TIMER0_APB] = {
.bit = BIT(0),
.reg = TH1520_TIMER0_RST_CFG,
},
[TH1520_RESET_ID_TIMER0_CORE] = {
.bit = BIT(1),
.reg = TH1520_TIMER0_RST_CFG,
},
[TH1520_RESET_ID_TIMER1_APB] = {
.bit = BIT(0),
.reg = TH1520_TIMER1_RST_CFG,
},
[TH1520_RESET_ID_TIMER1_CORE] = {
.bit = BIT(1),
.reg = TH1520_TIMER1_RST_CFG,
},
[TH1520_RESET_ID_PERISYS_AHB] = {
.bit = BIT(0),
.reg = TH1520_PERISYS_AHB_RST_CFG,
},
[TH1520_RESET_ID_PERISYS_APB1] = {
.bit = BIT(0),
.reg = TH1520_PERISYS_APB1_RST_CFG,
},
[TH1520_RESET_ID_PERISYS_APB2] = {
.bit = BIT(0),
.reg = TH1520_PERISYS_APB2_RST_CFG,
},
[TH1520_RESET_ID_GMAC0_APB] = {
.bit = BIT(0),
.reg = TH1520_GMAC0_RST_CFG,
},
[TH1520_RESET_ID_GMAC0_AHB] = {
.bit = BIT(1),
.reg = TH1520_GMAC0_RST_CFG,
},
[TH1520_RESET_ID_GMAC0_CLKGEN] = {
.bit = BIT(2),
.reg = TH1520_GMAC0_RST_CFG,
},
[TH1520_RESET_ID_GMAC0_AXI] = {
.bit = BIT(3),
.reg = TH1520_GMAC0_RST_CFG,
},
[TH1520_RESET_ID_UART0_APB] = {
.bit = BIT(0),
.reg = TH1520_UART0_RST_CFG,
},
[TH1520_RESET_ID_UART0_IF] = {
.bit = BIT(1),
.reg = TH1520_UART0_RST_CFG,
},
[TH1520_RESET_ID_UART1_APB] = {
.bit = BIT(0),
.reg = TH1520_UART1_RST_CFG,
},
[TH1520_RESET_ID_UART1_IF] = {
.bit = BIT(1),
.reg = TH1520_UART1_RST_CFG,
},
[TH1520_RESET_ID_UART2_APB] = {
.bit = BIT(0),
.reg = TH1520_UART2_RST_CFG,
},
[TH1520_RESET_ID_UART2_IF] = {
.bit = BIT(1),
.reg = TH1520_UART2_RST_CFG,
},
[TH1520_RESET_ID_UART3_APB] = {
.bit = BIT(0),
.reg = TH1520_UART3_RST_CFG,
},
[TH1520_RESET_ID_UART3_IF] = {
.bit = BIT(1),
.reg = TH1520_UART3_RST_CFG,
},
[TH1520_RESET_ID_UART4_APB] = {
.bit = BIT(0),
.reg = TH1520_UART4_RST_CFG,
},
[TH1520_RESET_ID_UART4_IF] = {
.bit = BIT(1),
.reg = TH1520_UART4_RST_CFG,
},
[TH1520_RESET_ID_UART5_APB] = {
.bit = BIT(0),
.reg = TH1520_UART5_RST_CFG,
},
[TH1520_RESET_ID_UART5_IF] = {
.bit = BIT(1),
.reg = TH1520_UART5_RST_CFG,
},
[TH1520_RESET_ID_QSPI0_IF] = {
.bit = BIT(0),
.reg = TH1520_QSPI0_RST_CFG,
},
[TH1520_RESET_ID_QSPI0_APB] = {
.bit = BIT(1),
.reg = TH1520_QSPI0_RST_CFG,
},
[TH1520_RESET_ID_QSPI1_IF] = {
.bit = BIT(0),
.reg = TH1520_QSPI1_RST_CFG,
},
[TH1520_RESET_ID_QSPI1_APB] = {
.bit = BIT(1),
.reg = TH1520_QSPI1_RST_CFG,
},
[TH1520_RESET_ID_SPI_IF] = {
.bit = BIT(0),
.reg = TH1520_SPI_RST_CFG,
},
[TH1520_RESET_ID_SPI_APB] = {
.bit = BIT(1),
.reg = TH1520_SPI_RST_CFG,
},
[TH1520_RESET_ID_I2C0_APB] = {
.bit = BIT(0),
.reg = TH1520_I2C0_RST_CFG,
},
[TH1520_RESET_ID_I2C0_CORE] = {
.bit = BIT(1),
.reg = TH1520_I2C0_RST_CFG,
},
[TH1520_RESET_ID_I2C1_APB] = {
.bit = BIT(0),
.reg = TH1520_I2C1_RST_CFG,
},
[TH1520_RESET_ID_I2C1_CORE] = {
.bit = BIT(1),
.reg = TH1520_I2C1_RST_CFG,
},
[TH1520_RESET_ID_I2C2_APB] = {
.bit = BIT(0),
.reg = TH1520_I2C2_RST_CFG,
},
[TH1520_RESET_ID_I2C2_CORE] = {
.bit = BIT(1),
.reg = TH1520_I2C2_RST_CFG,
},
[TH1520_RESET_ID_I2C3_APB] = {
.bit = BIT(0),
.reg = TH1520_I2C3_RST_CFG,
},
[TH1520_RESET_ID_I2C3_CORE] = {
.bit = BIT(1),
.reg = TH1520_I2C3_RST_CFG,
},
[TH1520_RESET_ID_I2C4_APB] = {
.bit = BIT(0),
.reg = TH1520_I2C4_RST_CFG,
},
[TH1520_RESET_ID_I2C4_CORE] = {
.bit = BIT(1),
.reg = TH1520_I2C4_RST_CFG,
},
[TH1520_RESET_ID_I2C5_APB] = {
.bit = BIT(0),
.reg = TH1520_I2C5_RST_CFG,
},
[TH1520_RESET_ID_I2C5_CORE] = {
.bit = BIT(1),
.reg = TH1520_I2C5_RST_CFG,
},
[TH1520_RESET_ID_GPIO0_DB] = {
.bit = BIT(0),
.reg = TH1520_GPIO0_RST_CFG,
},
[TH1520_RESET_ID_GPIO0_APB] = {
.bit = BIT(1),
.reg = TH1520_GPIO0_RST_CFG,
},
[TH1520_RESET_ID_GPIO1_DB] = {
.bit = BIT(0),
.reg = TH1520_GPIO1_RST_CFG,
},
[TH1520_RESET_ID_GPIO1_APB] = {
.bit = BIT(1),
.reg = TH1520_GPIO1_RST_CFG,
},
[TH1520_RESET_ID_GPIO2_DB] = {
.bit = BIT(0),
.reg = TH1520_GPIO2_RST_CFG,
},
[TH1520_RESET_ID_GPIO2_APB] = {
.bit = BIT(1),
.reg = TH1520_GPIO2_RST_CFG,
},
[TH1520_RESET_ID_PWM_COUNTER] = {
.bit = BIT(0),
.reg = TH1520_PWM_RST_CFG,
},
[TH1520_RESET_ID_PWM_APB] = {
.bit = BIT(1),
.reg = TH1520_PWM_RST_CFG,
},
[TH1520_RESET_ID_PADCTRL0_APB] = {
.bit = BIT(0),
.reg = TH1520_PADCTRL0_APSYS_RST_CFG,
},
[TH1520_RESET_ID_CPU2PERI_X2H] = {
.bit = BIT(1),
.reg = TH1520_CPU2PERI_X2H_RST_CFG,
},
[TH1520_RESET_ID_CPU2AON_X2H] = {
.bit = BIT(0),
.reg = TH1520_CPU2AON_X2H_RST_CFG,
},
[TH1520_RESET_ID_AON2CPU_A2X] = {
.bit = BIT(0),
.reg = TH1520_AON2CPU_A2X_RST_CFG,
},
[TH1520_RESET_ID_NPUSYS_AXI] = {
.bit = BIT(0),
.reg = TH1520_NPUSYS_AXI_RST_CFG,
},
[TH1520_RESET_ID_NPUSYS_AXI_APB] = {
.bit = BIT(1),
.reg = TH1520_NPUSYS_AXI_RST_CFG,
},
[TH1520_RESET_ID_CPU2VP_X2P] = {
.bit = BIT(0),
.reg = TH1520_CPU2VP_X2P_RST_CFG,
},
[TH1520_RESET_ID_CPU2VI_X2H] = {
.bit = BIT(0),
.reg = TH1520_CPU2VI_X2H_RST_CFG,
},
[TH1520_RESET_ID_BMU_AXI] = {
.bit = BIT(0),
.reg = TH1520_BMU_C910_RST_CFG,
},
[TH1520_RESET_ID_BMU_APB] = {
.bit = BIT(1),
.reg = TH1520_BMU_C910_RST_CFG,
},
[TH1520_RESET_ID_DMAC_CPUSYS_AXI] = {
.bit = BIT(0),
.reg = TH1520_DMAC_CPUSYS_RST_CFG,
},
[TH1520_RESET_ID_DMAC_CPUSYS_AHB] = {
.bit = BIT(1),
.reg = TH1520_DMAC_CPUSYS_RST_CFG,
},
[TH1520_RESET_ID_SPINLOCK] = {
.bit = BIT(0),
.reg = TH1520_SPINLOCK_RST_CFG,
},
[TH1520_RESET_ID_CFG2TEE] = {
.bit = BIT(0),
.reg = TH1520_CFG2TEE_X2H_RST_CFG,
},
[TH1520_RESET_ID_DSMART] = {
.bit = BIT(0),
.reg = TH1520_DSMART_RST_CFG,
},
[TH1520_RESET_ID_GPIO3_DB] = {
.bit = BIT(0),
.reg = TH1520_GPIO3_RST_CFG,
},
[TH1520_RESET_ID_GPIO3_APB] = {
.bit = BIT(1),
.reg = TH1520_GPIO3_RST_CFG,
},
[TH1520_RESET_ID_PERI_I2S] = {
.bit = BIT(0),
.reg = TH1520_I2S_RST_CFG,
},
[TH1520_RESET_ID_PERI_APB3] = {
.bit = BIT(0),
.reg = TH1520_PERI_APB3_RST_CFG,
},
[TH1520_RESET_ID_PERI2PERI1_APB] = {
.bit = BIT(1),
.reg = TH1520_PERI_APB3_RST_CFG,
},
[TH1520_RESET_ID_VPSYS_APB] = {
.bit = BIT(0),
.reg = TH1520_VP_SUBSYS_RST_CFG,
},
[TH1520_RESET_ID_PERISYS_APB4] = {
.bit = BIT(0),
.reg = TH1520_PERISYS_APB4_RST_CFG,
},
[TH1520_RESET_ID_GMAC1_APB] = {
.bit = BIT(0),
.reg = TH1520_GMAC1_RST_CFG,
},
[TH1520_RESET_ID_GMAC1_AHB] = {
.bit = BIT(1),
.reg = TH1520_GMAC1_RST_CFG,
},
[TH1520_RESET_ID_GMAC1_CLKGEN] = {
.bit = BIT(2),
.reg = TH1520_GMAC1_RST_CFG,
},
[TH1520_RESET_ID_GMAC1_AXI] = {
.bit = BIT(3),
.reg = TH1520_GMAC1_RST_CFG,
},
[TH1520_RESET_ID_GMAC_AXI] = {
.bit = BIT(0),
.reg = TH1520_GMAC_AXI_RST_CFG,
},
[TH1520_RESET_ID_GMAC_AXI_APB] = {
.bit = BIT(1),
.reg = TH1520_GMAC_AXI_RST_CFG,
},
[TH1520_RESET_ID_PADCTRL1_APB] = {
.bit = BIT(0),
.reg = TH1520_PADCTRL1_APSYS_RST_CFG,
},
[TH1520_RESET_ID_VOSYS_AXI] = {
.bit = BIT(0),
.reg = TH1520_VOSYS_AXI_RST_CFG,
},
[TH1520_RESET_ID_VOSYS_AXI_APB] = {
.bit = BIT(1),
.reg = TH1520_VOSYS_AXI_RST_CFG,
},
[TH1520_RESET_ID_VOSYS_AXI_X2X] = {
.bit = BIT(0),
.reg = TH1520_VOSYS_X2X_RST_CFG,
},
[TH1520_RESET_ID_MISC2VP_X2X] = {
.bit = BIT(0),
.reg = TH1520_MISC2VP_X2X_RST_CFG,
},
[TH1520_RESET_ID_DSPSYS] = {
.bit = BIT(0),
.reg = TH1520_SUBSYS_RST_CFG,
},
[TH1520_RESET_ID_VISYS] = {
.bit = BIT(1),
.reg = TH1520_SUBSYS_RST_CFG,
},
[TH1520_RESET_ID_VOSYS] = {
.bit = BIT(2),
.reg = TH1520_SUBSYS_RST_CFG,
},
[TH1520_RESET_ID_VPSYS] = {
.bit = BIT(3),
.reg = TH1520_SUBSYS_RST_CFG,
},
};
static const struct th1520_reset_map th1520_dsp_resets[] = {
[TH1520_RESET_ID_X2X_DSP1] = {
.bit = BIT(0),
.reg = TH1520_DSPSYS_RST_CFG,
},
[TH1520_RESET_ID_X2X_DSP0] = {
.bit = BIT(1),
.reg = TH1520_DSPSYS_RST_CFG,
},
[TH1520_RESET_ID_X2X_SLAVE_DSP1] = {
.bit = BIT(2),
.reg = TH1520_DSPSYS_RST_CFG,
},
[TH1520_RESET_ID_X2X_SLAVE_DSP0] = {
.bit = BIT(3),
.reg = TH1520_DSPSYS_RST_CFG,
},
[TH1520_RESET_ID_DSP0_CORE] = {
.bit = BIT(8),
.reg = TH1520_DSPSYS_RST_CFG,
},
[TH1520_RESET_ID_DSP0_DEBUG] = {
.bit = BIT(9),
.reg = TH1520_DSPSYS_RST_CFG,
},
[TH1520_RESET_ID_DSP0_APB] = {
.bit = BIT(10),
.reg = TH1520_DSPSYS_RST_CFG,
},
[TH1520_RESET_ID_DSP1_CORE] = {
.bit = BIT(12),
.reg = TH1520_DSPSYS_RST_CFG,
},
[TH1520_RESET_ID_DSP1_DEBUG] = {
.bit = BIT(13),
.reg = TH1520_DSPSYS_RST_CFG,
},
[TH1520_RESET_ID_DSP1_APB] = {
.bit = BIT(14),
.reg = TH1520_DSPSYS_RST_CFG,
},
[TH1520_RESET_ID_DSPSYS_APB] = {
.bit = BIT(16),
.reg = TH1520_DSPSYS_RST_CFG,
},
[TH1520_RESET_ID_AXI4_DSPSYS_SLV] = {
.bit = BIT(20),
.reg = TH1520_DSPSYS_RST_CFG,
},
[TH1520_RESET_ID_AXI4_DSPSYS] = {
.bit = BIT(24),
.reg = TH1520_DSPSYS_RST_CFG,
},
[TH1520_RESET_ID_AXI4_DSP_RS] = {
.bit = BIT(26),
.reg = TH1520_DSPSYS_RST_CFG,
},
};
static const struct th1520_reset_map th1520_misc_resets[] = {
[TH1520_RESET_ID_EMMC_SDIO_CLKGEN] = {
.bit = BIT(0),
.reg = TH1520_EMMC_RST_CFG,
},
[TH1520_RESET_ID_EMMC] = {
.bit = BIT(1),
.reg = TH1520_EMMC_RST_CFG,
},
[TH1520_RESET_ID_MISCSYS_AXI] = {
.bit = BIT(0),
.reg = TH1520_MISCSYS_AXI_RST_CFG,
},
[TH1520_RESET_ID_MISCSYS_AXI_APB] = {
.bit = BIT(1),
.reg = TH1520_MISCSYS_AXI_RST_CFG,
},
[TH1520_RESET_ID_SDIO0] = {
.bit = BIT(0),
.reg = TH1520_SDIO0_RST_CFG,
},
[TH1520_RESET_ID_SDIO1] = {
.bit = BIT(1),
.reg = TH1520_SDIO1_RST_CFG,
},
[TH1520_RESET_ID_USB3_APB] = {
.bit = BIT(0),
.reg = TH1520_USB3_DRD_RST_CFG,
},
[TH1520_RESET_ID_USB3_PHY] = {
.bit = BIT(1),
.reg = TH1520_USB3_DRD_RST_CFG,
},
[TH1520_RESET_ID_USB3_VCC] = {
.bit = BIT(2),
.reg = TH1520_USB3_DRD_RST_CFG,
},
};
static const struct th1520_reset_map th1520_vi_resets[] = {
[TH1520_RESET_ID_ISP0] = {
.bit = BIT(0),
.reg = TH1520_VISYS_RST_CFG,
},
[TH1520_RESET_ID_ISP1] = {
.bit = BIT(4),
.reg = TH1520_VISYS_RST_CFG,
},
[TH1520_RESET_ID_CSI0_APB] = {
.bit = BIT(16),
.reg = TH1520_VISYS_RST_CFG,
},
[TH1520_RESET_ID_CSI1_APB] = {
.bit = BIT(17),
.reg = TH1520_VISYS_RST_CFG,
},
[TH1520_RESET_ID_CSI2_APB] = {
.bit = BIT(18),
.reg = TH1520_VISYS_RST_CFG,
},
[TH1520_RESET_ID_MIPI_FIFO] = {
.bit = BIT(20),
.reg = TH1520_VISYS_RST_CFG,
},
[TH1520_RESET_ID_ISP_VENC_APB] = {
.bit = BIT(24),
.reg = TH1520_VISYS_RST_CFG,
},
[TH1520_RESET_ID_VIPRE_APB] = {
.bit = BIT(28),
.reg = TH1520_VISYS_RST_CFG,
},
[TH1520_RESET_ID_VIPRE_AXI] = {
.bit = BIT(29),
.reg = TH1520_VISYS_RST_CFG,
},
[TH1520_RESET_ID_DW200_APB] = {
.bit = BIT(31),
.reg = TH1520_VISYS_RST_CFG,
},
[TH1520_RESET_ID_VISYS3_AXI] = {
.bit = BIT(8),
.reg = TH1520_VISYS_2_RST_CFG,
},
[TH1520_RESET_ID_VISYS2_AXI] = {
.bit = BIT(9),
.reg = TH1520_VISYS_2_RST_CFG,
},
[TH1520_RESET_ID_VISYS1_AXI] = {
.bit = BIT(10),
.reg = TH1520_VISYS_2_RST_CFG,
},
[TH1520_RESET_ID_VISYS_AXI] = {
.bit = BIT(12),
.reg = TH1520_VISYS_2_RST_CFG,
},
[TH1520_RESET_ID_VISYS_APB] = {
.bit = BIT(16),
.reg = TH1520_VISYS_2_RST_CFG,
},
[TH1520_RESET_ID_ISP_VENC_AXI] = {
.bit = BIT(20),
.reg = TH1520_VISYS_2_RST_CFG,
},
};
static const struct th1520_reset_map th1520_vp_resets[] = {
[TH1520_RESET_ID_VPSYS_AXI_APB] = {
.bit = BIT(0),
.reg = TH1520_AXIBUS_RST_CFG,
},
[TH1520_RESET_ID_VPSYS_AXI] = {
.bit = BIT(1),
.reg = TH1520_AXIBUS_RST_CFG,
},
[TH1520_RESET_ID_FCE_APB] = {
.bit = BIT(0),
.reg = TH1520_FCE_RST_CFG,
},
[TH1520_RESET_ID_FCE_CORE] = {
.bit = BIT(1),
.reg = TH1520_FCE_RST_CFG,
},
[TH1520_RESET_ID_FCE_X2X_MASTER] = {
.bit = BIT(4),
.reg = TH1520_FCE_RST_CFG,
},
[TH1520_RESET_ID_FCE_X2X_SLAVE] = {
.bit = BIT(5),
.reg = TH1520_FCE_RST_CFG,
},
[TH1520_RESET_ID_G2D_APB] = {
.bit = BIT(0),
.reg = TH1520_G2D_RST_CFG,
},
[TH1520_RESET_ID_G2D_ACLK] = {
.bit = BIT(1),
.reg = TH1520_G2D_RST_CFG,
},
[TH1520_RESET_ID_G2D_CORE] = {
.bit = BIT(2),
.reg = TH1520_G2D_RST_CFG,
},
[TH1520_RESET_ID_VDEC_APB] = {
.bit = BIT(0),
.reg = TH1520_VDEC_RST_CFG,
},
[TH1520_RESET_ID_VDEC_ACLK] = {
.bit = BIT(1),
.reg = TH1520_VDEC_RST_CFG,
},
[TH1520_RESET_ID_VDEC_CORE] = {
.bit = BIT(2),
.reg = TH1520_VDEC_RST_CFG,
},
[TH1520_RESET_ID_VENC_APB] = {
.bit = BIT(0),
.reg = TH1520_VENC_RST_CFG,
},
[TH1520_RESET_ID_VENC_CORE] = {
.bit = BIT(1),
.reg = TH1520_VENC_RST_CFG,
},
};
static inline struct th1520_reset_priv *
@@ -90,7 +859,7 @@ static int th1520_reset_assert(struct reset_controller_dev *rcdev,
struct th1520_reset_priv *priv = to_th1520_reset(rcdev);
const struct th1520_reset_map *reset;
reset = &th1520_resets[id];
reset = &priv->resets[id];
return regmap_update_bits(priv->map, reset->reg, reset->bit, 0);
}
@@ -101,7 +870,7 @@ static int th1520_reset_deassert(struct reset_controller_dev *rcdev,
struct th1520_reset_priv *priv = to_th1520_reset(rcdev);
const struct th1520_reset_map *reset;
reset = &th1520_resets[id];
reset = &priv->resets[id];
return regmap_update_bits(priv->map, reset->reg, reset->bit,
reset->bit);
@@ -120,11 +889,14 @@ static const struct regmap_config th1520_reset_regmap_config = {
static int th1520_reset_probe(struct platform_device *pdev)
{
const struct th1520_reset_data *data;
struct device *dev = &pdev->dev;
struct th1520_reset_priv *priv;
void __iomem *base;
int ret;
data = device_get_match_data(dev);
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
@@ -138,22 +910,61 @@ static int th1520_reset_probe(struct platform_device *pdev)
if (IS_ERR(priv->map))
return PTR_ERR(priv->map);
/* Initialize GPU resets to asserted state */
ret = regmap_update_bits(priv->map, TH1520_GPU_RST_CFG,
TH1520_GPU_RST_CFG_MASK, 0);
if (ret)
return ret;
if (of_device_is_compatible(dev->of_node, "thead,th1520-reset")) {
/* Initialize GPU resets to asserted state */
ret = regmap_update_bits(priv->map, TH1520_GPU_RST_CFG,
TH1520_GPU_RST_CFG_MASK, 0);
if (ret)
return ret;
}
priv->rcdev.owner = THIS_MODULE;
priv->rcdev.nr_resets = ARRAY_SIZE(th1520_resets);
priv->rcdev.nr_resets = data->num;
priv->rcdev.ops = &th1520_reset_ops;
priv->rcdev.of_node = dev->of_node;
priv->resets = data->resets;
return devm_reset_controller_register(dev, &priv->rcdev);
}
static const struct th1520_reset_data th1520_reset_data = {
.resets = th1520_resets,
.num = ARRAY_SIZE(th1520_resets),
};
static const struct th1520_reset_data th1520_ap_reset_data = {
.resets = th1520_ap_resets,
.num = ARRAY_SIZE(th1520_ap_resets),
};
static const struct th1520_reset_data th1520_dsp_reset_data = {
.resets = th1520_dsp_resets,
.num = ARRAY_SIZE(th1520_dsp_resets),
};
static const struct th1520_reset_data th1520_misc_reset_data = {
.resets = th1520_misc_resets,
.num = ARRAY_SIZE(th1520_misc_resets),
};
static const struct th1520_reset_data th1520_vi_reset_data = {
.resets = th1520_vi_resets,
.num = ARRAY_SIZE(th1520_vi_resets),
};
static const struct th1520_reset_data th1520_vp_reset_data = {
.resets = th1520_vp_resets,
.num = ARRAY_SIZE(th1520_vp_resets),
};
static const struct of_device_id th1520_reset_match[] = {
{ .compatible = "thead,th1520-reset" },
{ .compatible = "thead,th1520-reset", .data = &th1520_reset_data },
{ .compatible = "thead,th1520-reset-ap", .data = &th1520_ap_reset_data },
{ .compatible = "thead,th1520-reset-dsp", .data = &th1520_dsp_reset_data },
{ .compatible = "thead,th1520-reset-misc", .data = &th1520_misc_reset_data },
{ .compatible = "thead,th1520-reset-vi", .data = &th1520_vi_reset_data },
{ .compatible = "thead,th1520-reset-vp", .data = &th1520_vp_reset_data },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, th1520_reset_match);

298
include/dt-bindings/reset/eswin,eic7700-reset.h Normal file
View File

@@ -0,0 +1,298 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright 2025, Beijing ESWIN Computing Technology Co., Ltd..
* All rights reserved.
*
* Device Tree binding constants for EIC7700 reset controller.
*
* Authors:
* Yifeng Huang <huangyifeng@eswincomputing.com>
* Xuyang Dong <dongxuyang@eswincomputing.com>
*/
#ifndef __DT_ESWIN_EIC7700_RESET_H__
#define __DT_ESWIN_EIC7700_RESET_H__
#define EIC7700_RESET_NOC_NSP 0
#define EIC7700_RESET_NOC_CFG 1
#define EIC7700_RESET_RNOC_NSP 2
#define EIC7700_RESET_SNOC_TCU 3
#define EIC7700_RESET_SNOC_U84 4
#define EIC7700_RESET_SNOC_PCIE_XSR 5
#define EIC7700_RESET_SNOC_PCIE_XMR 6
#define EIC7700_RESET_SNOC_PCIE_PR 7
#define EIC7700_RESET_SNOC_NPU 8
#define EIC7700_RESET_SNOC_JTAG 9
#define EIC7700_RESET_SNOC_DSP 10
#define EIC7700_RESET_SNOC_DDRC1_P2 11
#define EIC7700_RESET_SNOC_DDRC1_P1 12
#define EIC7700_RESET_SNOC_DDRC0_P2 13
#define EIC7700_RESET_SNOC_DDRC0_P1 14
#define EIC7700_RESET_SNOC_D2D 15
#define EIC7700_RESET_SNOC_AON 16
#define EIC7700_RESET_GPU_AXI 17
#define EIC7700_RESET_GPU_CFG 18
#define EIC7700_RESET_GPU_GRAY 19
#define EIC7700_RESET_GPU_JONES 20
#define EIC7700_RESET_GPU_SPU 21
#define EIC7700_RESET_DSP_AXI 22
#define EIC7700_RESET_DSP_CFG 23
#define EIC7700_RESET_DSP_DIV4 24
#define EIC7700_RESET_DSP_DIV0 25
#define EIC7700_RESET_DSP_DIV1 26
#define EIC7700_RESET_DSP_DIV2 27
#define EIC7700_RESET_DSP_DIV3 28
#define EIC7700_RESET_D2D_AXI 29
#define EIC7700_RESET_D2D_CFG 30
#define EIC7700_RESET_D2D_PRST 31
#define EIC7700_RESET_D2D_RAW_PCS 32
#define EIC7700_RESET_D2D_RX 33
#define EIC7700_RESET_D2D_TX 34
#define EIC7700_RESET_D2D_CORE 35
#define EIC7700_RESET_DDR1_ARST 36
#define EIC7700_RESET_DDR1_TRACE 37
#define EIC7700_RESET_DDR0_ARST 38
#define EIC7700_RESET_DDR_CFG 39
#define EIC7700_RESET_DDR0_TRACE 40
#define EIC7700_RESET_DDR_CORE 41
#define EIC7700_RESET_DDR_PRST 42
#define EIC7700_RESET_TCU_AXI 43
#define EIC7700_RESET_TCU_CFG 44
#define EIC7700_RESET_TCU_TBU0 45
#define EIC7700_RESET_TCU_TBU1 46
#define EIC7700_RESET_TCU_TBU2 47
#define EIC7700_RESET_TCU_TBU3 48
#define EIC7700_RESET_TCU_TBU4 49
#define EIC7700_RESET_TCU_TBU5 50
#define EIC7700_RESET_TCU_TBU6 51
#define EIC7700_RESET_TCU_TBU7 52
#define EIC7700_RESET_TCU_TBU8 53
#define EIC7700_RESET_TCU_TBU9 54
#define EIC7700_RESET_TCU_TBU10 55
#define EIC7700_RESET_TCU_TBU11 56
#define EIC7700_RESET_TCU_TBU12 57
#define EIC7700_RESET_TCU_TBU13 58
#define EIC7700_RESET_TCU_TBU14 59
#define EIC7700_RESET_TCU_TBU15 60
#define EIC7700_RESET_TCU_TBU16 61
#define EIC7700_RESET_NPU_AXI 62
#define EIC7700_RESET_NPU_CFG 63
#define EIC7700_RESET_NPU_CORE 64
#define EIC7700_RESET_NPU_E31CORE 65
#define EIC7700_RESET_NPU_E31BUS 66
#define EIC7700_RESET_NPU_E31DBG 67
#define EIC7700_RESET_NPU_LLC 68
#define EIC7700_RESET_HSP_AXI 69
#define EIC7700_RESET_HSP_CFG 70
#define EIC7700_RESET_HSP_POR 71
#define EIC7700_RESET_MSHC0_PHY 72
#define EIC7700_RESET_MSHC1_PHY 73
#define EIC7700_RESET_MSHC2_PHY 74
#define EIC7700_RESET_MSHC0_TXRX 75
#define EIC7700_RESET_MSHC1_TXRX 76
#define EIC7700_RESET_MSHC2_TXRX 77
#define EIC7700_RESET_SATA_ASIC0 78
#define EIC7700_RESET_SATA_OOB 79
#define EIC7700_RESET_SATA_PMALIVE 80
#define EIC7700_RESET_SATA_RBC 81
#define EIC7700_RESET_DMA0 82
#define EIC7700_RESET_HSP_DMA 83
#define EIC7700_RESET_USB0_VAUX 84
#define EIC7700_RESET_USB1_VAUX 85
#define EIC7700_RESET_HSP_SD1_PRST 86
#define EIC7700_RESET_HSP_SD0_PRST 87
#define EIC7700_RESET_HSP_EMMC_PRST 88
#define EIC7700_RESET_HSP_DMA_PRST 89
#define EIC7700_RESET_HSP_SD1_ARST 90
#define EIC7700_RESET_HSP_SD0_ARST 91
#define EIC7700_RESET_HSP_EMMC_ARST 92
#define EIC7700_RESET_HSP_DMA_ARST 93
#define EIC7700_RESET_HSP_ETH1_ARST 94
#define EIC7700_RESET_HSP_ETH0_ARST 95
#define EIC7700_RESET_SATA_ARST 96
#define EIC7700_RESET_PCIE_CFG 97
#define EIC7700_RESET_PCIE_POWEUP 98
#define EIC7700_RESET_PCIE_PERST 99
#define EIC7700_RESET_I2C0 100
#define EIC7700_RESET_I2C1 101
#define EIC7700_RESET_I2C2 102
#define EIC7700_RESET_I2C3 103
#define EIC7700_RESET_I2C4 104
#define EIC7700_RESET_I2C5 105
#define EIC7700_RESET_I2C6 106
#define EIC7700_RESET_I2C7 107
#define EIC7700_RESET_I2C8 108
#define EIC7700_RESET_I2C9 109
#define EIC7700_RESET_FAN 110
#define EIC7700_RESET_PVT0 111
#define EIC7700_RESET_PVT1 112
#define EIC7700_RESET_MBOX0 113
#define EIC7700_RESET_MBOX1 114
#define EIC7700_RESET_MBOX2 115
#define EIC7700_RESET_MBOX3 116
#define EIC7700_RESET_MBOX4 117
#define EIC7700_RESET_MBOX5 118
#define EIC7700_RESET_MBOX6 119
#define EIC7700_RESET_MBOX7 120
#define EIC7700_RESET_MBOX8 121
#define EIC7700_RESET_MBOX9 122
#define EIC7700_RESET_MBOX10 123
#define EIC7700_RESET_MBOX11 124
#define EIC7700_RESET_MBOX12 125
#define EIC7700_RESET_MBOX13 126
#define EIC7700_RESET_MBOX14 127
#define EIC7700_RESET_MBOX15 128
#define EIC7700_RESET_UART0 129
#define EIC7700_RESET_UART1 130
#define EIC7700_RESET_UART2 131
#define EIC7700_RESET_UART3 132
#define EIC7700_RESET_UART4 133
#define EIC7700_RESET_GPIO0 134
#define EIC7700_RESET_GPIO1 135
#define EIC7700_RESET_TIMER 136
#define EIC7700_RESET_SSI0 137
#define EIC7700_RESET_SSI1 138
#define EIC7700_RESET_WDT0 139
#define EIC7700_RESET_WDT1 140
#define EIC7700_RESET_WDT2 141
#define EIC7700_RESET_WDT3 142
#define EIC7700_RESET_LSP_CFG 143
#define EIC7700_RESET_U84_CORE0 144
#define EIC7700_RESET_U84_CORE1 145
#define EIC7700_RESET_U84_CORE2 146
#define EIC7700_RESET_U84_CORE3 147
#define EIC7700_RESET_U84_BUS 148
#define EIC7700_RESET_U84_DBG 149
#define EIC7700_RESET_U84_TRACECOM 150
#define EIC7700_RESET_U84_TRACE0 151
#define EIC7700_RESET_U84_TRACE1 152
#define EIC7700_RESET_U84_TRACE2 153
#define EIC7700_RESET_U84_TRACE3 154
#define EIC7700_RESET_SCPU_CORE 155
#define EIC7700_RESET_SCPU_BUS 156
#define EIC7700_RESET_SCPU_DBG 157
#define EIC7700_RESET_LPCPU_CORE 158
#define EIC7700_RESET_LPCPU_BUS 159
#define EIC7700_RESET_LPCPU_DBG 160
#define EIC7700_RESET_VC_CFG 161
#define EIC7700_RESET_VC_AXI 162
#define EIC7700_RESET_VC_MONCFG 163
#define EIC7700_RESET_JD_CFG 164
#define EIC7700_RESET_JD_AXI 165
#define EIC7700_RESET_JE_CFG 166
#define EIC7700_RESET_JE_AXI 167
#define EIC7700_RESET_VD_CFG 168
#define EIC7700_RESET_VD_AXI 169
#define EIC7700_RESET_VE_AXI 170
#define EIC7700_RESET_VE_CFG 171
#define EIC7700_RESET_G2D_CORE 172
#define EIC7700_RESET_G2D_CFG 173
#define EIC7700_RESET_G2D_AXI 174
#define EIC7700_RESET_VI_AXI 175
#define EIC7700_RESET_VI_CFG 176
#define EIC7700_RESET_VI_DWE 177
#define EIC7700_RESET_DVP 178
#define EIC7700_RESET_ISP0 179
#define EIC7700_RESET_ISP1 180
#define EIC7700_RESET_SHUTTR0 181
#define EIC7700_RESET_SHUTTR1 182
#define EIC7700_RESET_SHUTTR2 183
#define EIC7700_RESET_SHUTTR3 184
#define EIC7700_RESET_SHUTTR4 185
#define EIC7700_RESET_SHUTTR5 186
#define EIC7700_RESET_VO_MIPI 187
#define EIC7700_RESET_VO_PRST 188
#define EIC7700_RESET_VO_HDMI_PRST 189
#define EIC7700_RESET_VO_HDMI_PHY 190
#define EIC7700_RESET_VO_HDMI 191
#define EIC7700_RESET_VO_I2S 192
#define EIC7700_RESET_VO_I2S_PRST 193
#define EIC7700_RESET_VO_AXI 194
#define EIC7700_RESET_VO_CFG 195
#define EIC7700_RESET_VO_DC 196
#define EIC7700_RESET_VO_DC_PRST 197
#define EIC7700_RESET_BOOTSPI_HRST 198
#define EIC7700_RESET_BOOTSPI 199
#define EIC7700_RESET_ANO1 200
#define EIC7700_RESET_ANO0 201
#define EIC7700_RESET_DMA1_ARST 202
#define EIC7700_RESET_DMA1_HRST 203
#define EIC7700_RESET_FPRT 204
#define EIC7700_RESET_HBLOCK 205
#define EIC7700_RESET_SECSR 206
#define EIC7700_RESET_OTP 207
#define EIC7700_RESET_PKA 208
#define EIC7700_RESET_SPACC 209
#define EIC7700_RESET_TRNG 210
#define EIC7700_RESET_TIMER0_0 211
#define EIC7700_RESET_TIMER0_1 212
#define EIC7700_RESET_TIMER0_2 213
#define EIC7700_RESET_TIMER0_3 214
#define EIC7700_RESET_TIMER0_4 215
#define EIC7700_RESET_TIMER0_5 216
#define EIC7700_RESET_TIMER0_6 217
#define EIC7700_RESET_TIMER0_7 218
#define EIC7700_RESET_TIMER0_N 219
#define EIC7700_RESET_TIMER1_0 220
#define EIC7700_RESET_TIMER1_1 221
#define EIC7700_RESET_TIMER1_2 222
#define EIC7700_RESET_TIMER1_3 223
#define EIC7700_RESET_TIMER1_4 224
#define EIC7700_RESET_TIMER1_5 225
#define EIC7700_RESET_TIMER1_6 226
#define EIC7700_RESET_TIMER1_7 227
#define EIC7700_RESET_TIMER1_N 228
#define EIC7700_RESET_TIMER2_0 229
#define EIC7700_RESET_TIMER2_1 230
#define EIC7700_RESET_TIMER2_2 231
#define EIC7700_RESET_TIMER2_3 232
#define EIC7700_RESET_TIMER2_4 233
#define EIC7700_RESET_TIMER2_5 234
#define EIC7700_RESET_TIMER2_6 235
#define EIC7700_RESET_TIMER2_7 236
#define EIC7700_RESET_TIMER2_N 237
#define EIC7700_RESET_TIMER3_0 238
#define EIC7700_RESET_TIMER3_1 239
#define EIC7700_RESET_TIMER3_2 240
#define EIC7700_RESET_TIMER3_3 241
#define EIC7700_RESET_TIMER3_4 242
#define EIC7700_RESET_TIMER3_5 243
#define EIC7700_RESET_TIMER3_6 244
#define EIC7700_RESET_TIMER3_7 245
#define EIC7700_RESET_TIMER3_N 246
#define EIC7700_RESET_RTC 247
#define EIC7700_RESET_MNOC_SNOC_NSP 248
#define EIC7700_RESET_MNOC_VC 249
#define EIC7700_RESET_MNOC_CFG 250
#define EIC7700_RESET_MNOC_HSP 251
#define EIC7700_RESET_MNOC_GPU 252
#define EIC7700_RESET_MNOC_DDRC1_P3 253
#define EIC7700_RESET_MNOC_DDRC0_P3 254
#define EIC7700_RESET_RNOC_VO 255
#define EIC7700_RESET_RNOC_VI 256
#define EIC7700_RESET_RNOC_SNOC_NSP 257
#define EIC7700_RESET_RNOC_CFG 258
#define EIC7700_RESET_MNOC_DDRC1_P4 259
#define EIC7700_RESET_MNOC_DDRC0_P4 260
#define EIC7700_RESET_CNOC_VO_CFG 261
#define EIC7700_RESET_CNOC_VI_CFG 262
#define EIC7700_RESET_CNOC_VC_CFG 263
#define EIC7700_RESET_CNOC_TCU_CFG 264
#define EIC7700_RESET_CNOC_PCIE_CFG 265
#define EIC7700_RESET_CNOC_NPU_CFG 266
#define EIC7700_RESET_CNOC_LSP_CFG 267
#define EIC7700_RESET_CNOC_HSP_CFG 268
#define EIC7700_RESET_CNOC_GPU_CFG 269
#define EIC7700_RESET_CNOC_DSPT_CFG 270
#define EIC7700_RESET_CNOC_DDRT1_CFG 271
#define EIC7700_RESET_CNOC_DDRT0_CFG 272
#define EIC7700_RESET_CNOC_D2D_CFG 273
#define EIC7700_RESET_CNOC_CFG 274
#define EIC7700_RESET_CNOC_CLMM_CFG 275
#define EIC7700_RESET_CNOC_AON_CFG 276
#define EIC7700_RESET_LNOC_CFG 277
#define EIC7700_RESET_LNOC_NPU_LLC 278
#define EIC7700_RESET_LNOC_DDRC1_P0 279
#define EIC7700_RESET_LNOC_DDRC0_P0 280
#endif /* __DT_ESWIN_EIC7700_RESET_H__ */

219
include/dt-bindings/reset/thead,th1520-reset.h
View File

@@ -7,11 +7,202 @@
#ifndef _DT_BINDINGS_TH1520_RESET_H
#define _DT_BINDINGS_TH1520_RESET_H
/* AO Subsystem */
#define TH1520_RESET_ID_SYSTEM 0
#define TH1520_RESET_ID_RTC_APB 1
#define TH1520_RESET_ID_RTC_REF 2
#define TH1520_RESET_ID_AOGPIO_DB 3
#define TH1520_RESET_ID_AOGPIO_APB 4
#define TH1520_RESET_ID_AOI2C_APB 5
#define TH1520_RESET_ID_PVT_APB 6
#define TH1520_RESET_ID_E902_CORE 7
#define TH1520_RESET_ID_E902_HAD 8
#define TH1520_RESET_ID_AOTIMER_APB 9
#define TH1520_RESET_ID_AOTIMER_CORE 10
#define TH1520_RESET_ID_AOWDT_APB 11
#define TH1520_RESET_ID_APSYS 12
#define TH1520_RESET_ID_NPUSYS 13
#define TH1520_RESET_ID_DDRSYS 14
#define TH1520_RESET_ID_AXI_AP2CP 15
#define TH1520_RESET_ID_AXI_CP2AP 16
#define TH1520_RESET_ID_AXI_CP2SRAM 17
#define TH1520_RESET_ID_AUDSYS_CORE 18
#define TH1520_RESET_ID_AUDSYS_IOPMP 19
#define TH1520_RESET_ID_AUDSYS 20
#define TH1520_RESET_ID_DSP0 21
#define TH1520_RESET_ID_DSP1 22
#define TH1520_RESET_ID_GPU_MODULE 23
#define TH1520_RESET_ID_VDEC 24
#define TH1520_RESET_ID_VENC 25
#define TH1520_RESET_ID_ADC_APB 26
#define TH1520_RESET_ID_AUDGPIO_DB 27
#define TH1520_RESET_ID_AUDGPIO_APB 28
#define TH1520_RESET_ID_AOUART_IF 29
#define TH1520_RESET_ID_AOUART_APB 30
#define TH1520_RESET_ID_SRAM_AXI_P0 31
#define TH1520_RESET_ID_SRAM_AXI_P1 32
#define TH1520_RESET_ID_SRAM_AXI_P2 33
#define TH1520_RESET_ID_SRAM_AXI_P3 34
#define TH1520_RESET_ID_SRAM_AXI_P4 35
#define TH1520_RESET_ID_SRAM_AXI_CORE 36
#define TH1520_RESET_ID_SE 37
/* AP Subsystem */
#define TH1520_RESET_ID_BROM 0
#define TH1520_RESET_ID_C910_TOP 1
#define TH1520_RESET_ID_NPU 2
#define TH1520_RESET_ID_WDT0 3
#define TH1520_RESET_ID_WDT1 4
#define TH1520_RESET_ID_C910_C0 5
#define TH1520_RESET_ID_C910_C1 6
#define TH1520_RESET_ID_C910_C2 7
#define TH1520_RESET_ID_C910_C3 8
#define TH1520_RESET_ID_CHIP_DBG_CORE 9
#define TH1520_RESET_ID_CHIP_DBG_AXI 10
#define TH1520_RESET_ID_AXI4_CPUSYS2_AXI 11
#define TH1520_RESET_ID_AXI4_CPUSYS2_APB 12
#define TH1520_RESET_ID_X2H_CPUSYS 13
#define TH1520_RESET_ID_AHB2_CPUSYS 14
#define TH1520_RESET_ID_APB3_CPUSYS 15
#define TH1520_RESET_ID_MBOX0_APB 16
#define TH1520_RESET_ID_MBOX1_APB 17
#define TH1520_RESET_ID_MBOX2_APB 18
#define TH1520_RESET_ID_MBOX3_APB 19
#define TH1520_RESET_ID_TIMER0_APB 20
#define TH1520_RESET_ID_TIMER0_CORE 21
#define TH1520_RESET_ID_TIMER1_APB 22
#define TH1520_RESET_ID_TIMER1_CORE 23
#define TH1520_RESET_ID_PERISYS_AHB 24
#define TH1520_RESET_ID_PERISYS_APB1 25
#define TH1520_RESET_ID_PERISYS_APB2 26
#define TH1520_RESET_ID_GMAC0_APB 27
#define TH1520_RESET_ID_GMAC0_AHB 28
#define TH1520_RESET_ID_GMAC0_CLKGEN 29
#define TH1520_RESET_ID_GMAC0_AXI 30
#define TH1520_RESET_ID_UART0_APB 31
#define TH1520_RESET_ID_UART0_IF 32
#define TH1520_RESET_ID_UART1_APB 33
#define TH1520_RESET_ID_UART1_IF 34
#define TH1520_RESET_ID_UART2_APB 35
#define TH1520_RESET_ID_UART2_IF 36
#define TH1520_RESET_ID_UART3_APB 37
#define TH1520_RESET_ID_UART3_IF 38
#define TH1520_RESET_ID_UART4_APB 39
#define TH1520_RESET_ID_UART4_IF 40
#define TH1520_RESET_ID_UART5_APB 41
#define TH1520_RESET_ID_UART5_IF 42
#define TH1520_RESET_ID_QSPI0_IF 43
#define TH1520_RESET_ID_QSPI0_APB 44
#define TH1520_RESET_ID_QSPI1_IF 45
#define TH1520_RESET_ID_QSPI1_APB 46
#define TH1520_RESET_ID_SPI_IF 47
#define TH1520_RESET_ID_SPI_APB 48
#define TH1520_RESET_ID_I2C0_APB 49
#define TH1520_RESET_ID_I2C0_CORE 50
#define TH1520_RESET_ID_I2C1_APB 51
#define TH1520_RESET_ID_I2C1_CORE 52
#define TH1520_RESET_ID_I2C2_APB 53
#define TH1520_RESET_ID_I2C2_CORE 54
#define TH1520_RESET_ID_I2C3_APB 55
#define TH1520_RESET_ID_I2C3_CORE 56
#define TH1520_RESET_ID_I2C4_APB 57
#define TH1520_RESET_ID_I2C4_CORE 58
#define TH1520_RESET_ID_I2C5_APB 59
#define TH1520_RESET_ID_I2C5_CORE 60
#define TH1520_RESET_ID_GPIO0_DB 61
#define TH1520_RESET_ID_GPIO0_APB 62
#define TH1520_RESET_ID_GPIO1_DB 63
#define TH1520_RESET_ID_GPIO1_APB 64
#define TH1520_RESET_ID_GPIO2_DB 65
#define TH1520_RESET_ID_GPIO2_APB 66
#define TH1520_RESET_ID_PWM_COUNTER 67
#define TH1520_RESET_ID_PWM_APB 68
#define TH1520_RESET_ID_PADCTRL0_APB 69
#define TH1520_RESET_ID_CPU2PERI_X2H 70
#define TH1520_RESET_ID_CPU2AON_X2H 71
#define TH1520_RESET_ID_AON2CPU_A2X 72
#define TH1520_RESET_ID_NPUSYS_AXI 73
#define TH1520_RESET_ID_NPUSYS_AXI_APB 74
#define TH1520_RESET_ID_CPU2VP_X2P 75
#define TH1520_RESET_ID_CPU2VI_X2H 76
#define TH1520_RESET_ID_BMU_AXI 77
#define TH1520_RESET_ID_BMU_APB 78
#define TH1520_RESET_ID_DMAC_CPUSYS_AXI 79
#define TH1520_RESET_ID_DMAC_CPUSYS_AHB 80
#define TH1520_RESET_ID_SPINLOCK 81
#define TH1520_RESET_ID_CFG2TEE 82
#define TH1520_RESET_ID_DSMART 83
#define TH1520_RESET_ID_GPIO3_DB 84
#define TH1520_RESET_ID_GPIO3_APB 85
#define TH1520_RESET_ID_PERI_I2S 86
#define TH1520_RESET_ID_PERI_APB3 87
#define TH1520_RESET_ID_PERI2PERI1_APB 88
#define TH1520_RESET_ID_VPSYS_APB 89
#define TH1520_RESET_ID_PERISYS_APB4 90
#define TH1520_RESET_ID_GMAC1_APB 91
#define TH1520_RESET_ID_GMAC1_AHB 92
#define TH1520_RESET_ID_GMAC1_CLKGEN 93
#define TH1520_RESET_ID_GMAC1_AXI 94
#define TH1520_RESET_ID_GMAC_AXI 95
#define TH1520_RESET_ID_GMAC_AXI_APB 96
#define TH1520_RESET_ID_PADCTRL1_APB 97
#define TH1520_RESET_ID_VOSYS_AXI 98
#define TH1520_RESET_ID_VOSYS_AXI_APB 99
#define TH1520_RESET_ID_VOSYS_AXI_X2X 100
#define TH1520_RESET_ID_MISC2VP_X2X 101
#define TH1520_RESET_ID_DSPSYS 102
#define TH1520_RESET_ID_VISYS 103
#define TH1520_RESET_ID_VOSYS 104
#define TH1520_RESET_ID_VPSYS 105
/* DSP Subsystem */
#define TH1520_RESET_ID_X2X_DSP1 0
#define TH1520_RESET_ID_X2X_DSP0 1
#define TH1520_RESET_ID_X2X_SLAVE_DSP1 2
#define TH1520_RESET_ID_X2X_SLAVE_DSP0 3
#define TH1520_RESET_ID_DSP0_CORE 4
#define TH1520_RESET_ID_DSP0_DEBUG 5
#define TH1520_RESET_ID_DSP0_APB 6
#define TH1520_RESET_ID_DSP1_CORE 7
#define TH1520_RESET_ID_DSP1_DEBUG 8
#define TH1520_RESET_ID_DSP1_APB 9
#define TH1520_RESET_ID_DSPSYS_APB 10
#define TH1520_RESET_ID_AXI4_DSPSYS_SLV 11
#define TH1520_RESET_ID_AXI4_DSPSYS 12
#define TH1520_RESET_ID_AXI4_DSP_RS 13
/* MISC Subsystem */
#define TH1520_RESET_ID_EMMC_SDIO_CLKGEN 0
#define TH1520_RESET_ID_EMMC 1
#define TH1520_RESET_ID_MISCSYS_AXI 2
#define TH1520_RESET_ID_MISCSYS_AXI_APB 3
#define TH1520_RESET_ID_SDIO0 4
#define TH1520_RESET_ID_SDIO1 5
#define TH1520_RESET_ID_USB3_APB 6
#define TH1520_RESET_ID_USB3_PHY 7
#define TH1520_RESET_ID_USB3_VCC 8
/* VI Subsystem */
#define TH1520_RESET_ID_ISP0 0
#define TH1520_RESET_ID_ISP1 1
#define TH1520_RESET_ID_CSI0_APB 2
#define TH1520_RESET_ID_CSI1_APB 3
#define TH1520_RESET_ID_CSI2_APB 4
#define TH1520_RESET_ID_MIPI_FIFO 5
#define TH1520_RESET_ID_ISP_VENC_APB 6
#define TH1520_RESET_ID_VIPRE_APB 7
#define TH1520_RESET_ID_VIPRE_AXI 8
#define TH1520_RESET_ID_DW200_APB 9
#define TH1520_RESET_ID_VISYS3_AXI 10
#define TH1520_RESET_ID_VISYS2_AXI 11
#define TH1520_RESET_ID_VISYS1_AXI 12
#define TH1520_RESET_ID_VISYS_AXI 13
#define TH1520_RESET_ID_VISYS_APB 14
#define TH1520_RESET_ID_ISP_VENC_AXI 15
/* VO Subsystem */
#define TH1520_RESET_ID_GPU 0
#define TH1520_RESET_ID_GPU_CLKGEN 1
#define TH1520_RESET_ID_NPU 2
#define TH1520_RESET_ID_WDT0 3
#define TH1520_RESET_ID_WDT1 4
#define TH1520_RESET_ID_DPU_AHB 5
#define TH1520_RESET_ID_DPU_AXI 6
#define TH1520_RESET_ID_DPU_CORE 7
@@ -19,5 +210,27 @@
#define TH1520_RESET_ID_DSI1_APB 9
#define TH1520_RESET_ID_HDMI 10
#define TH1520_RESET_ID_HDMI_APB 11
#define TH1520_RESET_ID_VOAXI 12
#define TH1520_RESET_ID_VOAXI_APB 13
#define TH1520_RESET_ID_X2H_DPU_AXI 14
#define TH1520_RESET_ID_X2H_DPU_AHB 15
#define TH1520_RESET_ID_X2H_DPU1_AXI 16
#define TH1520_RESET_ID_X2H_DPU1_AHB 17
/* VP Subsystem */
#define TH1520_RESET_ID_VPSYS_AXI_APB 0
#define TH1520_RESET_ID_VPSYS_AXI 1
#define TH1520_RESET_ID_FCE_APB 2
#define TH1520_RESET_ID_FCE_CORE 3
#define TH1520_RESET_ID_FCE_X2X_MASTER 4
#define TH1520_RESET_ID_FCE_X2X_SLAVE 5
#define TH1520_RESET_ID_G2D_APB 6
#define TH1520_RESET_ID_G2D_ACLK 7
#define TH1520_RESET_ID_G2D_CORE 8
#define TH1520_RESET_ID_VDEC_APB 9
#define TH1520_RESET_ID_VDEC_ACLK 10
#define TH1520_RESET_ID_VDEC_CORE 11
#define TH1520_RESET_ID_VENC_APB 12
#define TH1520_RESET_ID_VENC_CORE 13
#endif /* _DT_BINDINGS_TH1520_RESET_H */

33
include/linux/reset-controller.h
View File

@@ -26,31 +26,6 @@ struct module;
struct device_node;
struct of_phandle_args;
/**
* struct reset_control_lookup - represents a single lookup entry
*
* @list: internal list of all reset lookup entries
* @provider: name of the reset controller device controlling this reset line
* @index: ID of the reset controller in the reset controller device
* @dev_id: name of the device associated with this reset line
* @con_id: name of the reset line (can be NULL)
*/
struct reset_control_lookup {
struct list_head list;
const char *provider;
unsigned int index;
const char *dev_id;
const char *con_id;
};
#define RESET_LOOKUP(_provider, _index, _dev_id, _con_id) \
{ \
.provider = _provider, \
.index = _index, \
.dev_id = _dev_id, \
.con_id = _con_id, \
}
/**
* struct reset_controller_dev - reset controller entity that might
* provide multiple reset controls
@@ -90,9 +65,6 @@ void reset_controller_unregister(struct reset_controller_dev *rcdev);
struct device;
int devm_reset_controller_register(struct device *dev,
struct reset_controller_dev *rcdev);
void reset_controller_add_lookup(struct reset_control_lookup *lookup,
unsigned int num_entries);
#else
static inline int reset_controller_register(struct reset_controller_dev *rcdev)
{
@@ -108,11 +80,6 @@ static inline int devm_reset_controller_register(struct device *dev,
{
return 0;
}
static inline void reset_controller_add_lookup(struct reset_control_lookup *lookup,
unsigned int num_entries)
{
}
#endif
#endif

1
include/linux/reset.h
View File

@@ -2,6 +2,7 @@
#ifndef _LINUX_RESET_H_
#define _LINUX_RESET_H_
#include <linux/bits.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/types.h>