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drm/amd/display: Initialize DP ref clk with the correct clock

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Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rodrigo Siqueira
2024-03-21 14:30:45 -06:00
committed by Alex Deucher
parent 7315a4fb15
commit a96e384cbb
1 changed files with 2 additions and 2 deletions
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4
drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
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@@ -131,8 +131,8 @@ int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
int dprefclk_wdivider;
int dprefclk_src_sel;
int dp_ref_clk_khz;
int target_div = 600000;
int dp_ref_clk_khz = 600000;
int target_div;
/* ASSERT DP Reference Clock source is from DFS*/
REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel);