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wifi: rtw89: Add rtw8852c_dle_mem_usb{2,3}
Add rtw8852c_dle_mem_usb2 and rtw8852c_dle_mem_usb3 and their various quotas and sizes in struct rtw89_mac_size_set. "dle" could be "Data Link Engine" or "Double Link Engine". These are some parameters needed for RTL8852CU. Signed-off-by: Bitterblue Smith <rtl8821cerfe2@gmail.com> Acked-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/40a58644-13ce-48a4-85e2-ba4f3cbb975b@gmail.com
This commit is contained in:
committed by
Ping-Ke Shih
parent
97259766b1
commit
a865899084
@@ -1663,6 +1663,8 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
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.wde_size7 = {RTW89_WDE_PG_64, 510, 2,},
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/* DLFW */
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.wde_size9 = {RTW89_WDE_PG_64, 0, 1024,},
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/* 8852C USB3.0 */
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.wde_size17 = {RTW89_WDE_PG_64, 354, 30,},
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/* 8852C DLFW */
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.wde_size18 = {RTW89_WDE_PG_64, 0, 2048,},
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/* 8852C PCIE SCC */
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@@ -1670,6 +1672,8 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
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.wde_size23 = {RTW89_WDE_PG_64, 1022, 2,},
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/* 8852B USB2.0/USB3.0 SCC */
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.wde_size25 = {RTW89_WDE_PG_64, 162, 94,},
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/* 8852C USB2.0 */
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.wde_size31 = {RTW89_WDE_PG_64, 384, 0,},
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/* PCIE */
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.ple_size0 = {RTW89_PLE_PG_128, 1520, 16,},
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.ple_size0_v1 = {RTW89_PLE_PG_128, 2688, 240, 212992,},
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@@ -1681,6 +1685,8 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
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/* DLFW */
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.ple_size8 = {RTW89_PLE_PG_128, 64, 960,},
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.ple_size9 = {RTW89_PLE_PG_128, 2288, 16,},
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/* 8852C USB */
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.ple_size17 = {RTW89_PLE_PG_128, 3368, 24,},
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/* 8852C DLFW */
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.ple_size18 = {RTW89_PLE_PG_128, 2544, 16,},
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/* 8852C PCIE SCC */
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@@ -1689,6 +1695,8 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
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.ple_size32 = {RTW89_PLE_PG_128, 620, 20,},
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/* 8852B USB3.0 SCC */
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.ple_size33 = {RTW89_PLE_PG_128, 632, 8,},
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/* 8852C USB2.0 */
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.ple_size34 = {RTW89_PLE_PG_128, 3374, 18,},
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/* PCIE 64 */
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.wde_qt0 = {3792, 196, 0, 107,},
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.wde_qt0_v1 = {3302, 6, 0, 20,},
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@@ -1698,6 +1706,8 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
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.wde_qt6 = {448, 48, 0, 16,},
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/* 8852B PCIE SCC */
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.wde_qt7 = {446, 48, 0, 16,},
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/* 8852C USB3.0 */
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.wde_qt16 = {344, 2, 0, 8,},
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/* 8852C DLFW */
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.wde_qt17 = {0, 0, 0, 0,},
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/* 8852C PCIE SCC */
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@@ -1705,6 +1715,8 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
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.wde_qt23 = {958, 48, 0, 16,},
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/* 8852B USB2.0/USB3.0 SCC */
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.wde_qt25 = {152, 2, 0, 8,},
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/* 8852C USB2.0 */
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.wde_qt31 = {338, 6, 0, 40,},
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.ple_qt0 = {320, 320, 32, 16, 13, 13, 292, 292, 64, 18, 1, 4, 0,},
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.ple_qt1 = {320, 320, 32, 16, 1316, 1316, 1595, 1595, 1367, 1321, 1, 1307, 0,},
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/* PCIE SCC */
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@@ -1716,6 +1728,10 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
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.ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,},
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/* PCIE 64 */
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.ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,},
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/* USB 52C USB3.0 */
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.ple_qt42 = {1068, 0, 16, 48, 4, 13, 178, 0, 16, 1, 8, 16, 0,},
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/* USB 52C USB3.0 */
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.ple_qt43 = {3068, 0, 32, 48, 4, 13, 178, 0, 16, 1, 8, 16, 0,},
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/* DLFW 52C */
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.ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,},
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/* DLFW 52C */
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@@ -1735,6 +1751,10 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
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/* USB3.0 52B 92K */
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.ple_qt74 = {286, 0, 16, 48, 4, 13, 178, 0, 32, 14, 8, 0, 0,},
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.ple_qt75 = {286, 0, 32, 48, 37, 13, 211, 0, 65, 14, 24, 0, 0,},
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/* USB2.0 52C */
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.ple_qt78 = {1560, 0, 16, 48, 13, 13, 390, 0, 32, 38, 8, 16, 0,},
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/* USB2.0 52C */
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.ple_qt79 = {1560, 0, 32, 48, 1253, 13, 1630, 0, 1272, 38, 120, 1256, 0,},
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/* 8852A PCIE WOW */
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.ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,},
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/* 8852B PCIE WOW */
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@@ -923,10 +923,12 @@ struct rtw89_mac_size_set {
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const struct rtw89_dle_size wde_size6;
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const struct rtw89_dle_size wde_size7;
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const struct rtw89_dle_size wde_size9;
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const struct rtw89_dle_size wde_size17;
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const struct rtw89_dle_size wde_size18;
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const struct rtw89_dle_size wde_size19;
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const struct rtw89_dle_size wde_size23;
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const struct rtw89_dle_size wde_size25;
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const struct rtw89_dle_size wde_size31;
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const struct rtw89_dle_size ple_size0;
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const struct rtw89_dle_size ple_size0_v1;
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const struct rtw89_dle_size ple_size3_v1;
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@@ -934,19 +936,23 @@ struct rtw89_mac_size_set {
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const struct rtw89_dle_size ple_size6;
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const struct rtw89_dle_size ple_size8;
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const struct rtw89_dle_size ple_size9;
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const struct rtw89_dle_size ple_size17;
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const struct rtw89_dle_size ple_size18;
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const struct rtw89_dle_size ple_size19;
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const struct rtw89_dle_size ple_size32;
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const struct rtw89_dle_size ple_size33;
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const struct rtw89_dle_size ple_size34;
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const struct rtw89_wde_quota wde_qt0;
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const struct rtw89_wde_quota wde_qt0_v1;
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const struct rtw89_wde_quota wde_qt4;
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const struct rtw89_wde_quota wde_qt6;
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const struct rtw89_wde_quota wde_qt7;
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const struct rtw89_wde_quota wde_qt16;
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const struct rtw89_wde_quota wde_qt17;
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const struct rtw89_wde_quota wde_qt18;
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const struct rtw89_wde_quota wde_qt23;
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const struct rtw89_wde_quota wde_qt25;
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const struct rtw89_wde_quota wde_qt31;
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const struct rtw89_ple_quota ple_qt0;
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const struct rtw89_ple_quota ple_qt1;
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const struct rtw89_ple_quota ple_qt4;
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@@ -954,6 +960,8 @@ struct rtw89_mac_size_set {
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const struct rtw89_ple_quota ple_qt9;
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const struct rtw89_ple_quota ple_qt13;
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const struct rtw89_ple_quota ple_qt18;
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const struct rtw89_ple_quota ple_qt42;
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const struct rtw89_ple_quota ple_qt43;
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const struct rtw89_ple_quota ple_qt44;
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const struct rtw89_ple_quota ple_qt45;
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const struct rtw89_ple_quota ple_qt46;
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@@ -965,6 +973,8 @@ struct rtw89_mac_size_set {
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const struct rtw89_ple_quota ple_qt73;
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const struct rtw89_ple_quota ple_qt74;
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const struct rtw89_ple_quota ple_qt75;
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const struct rtw89_ple_quota ple_qt78;
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const struct rtw89_ple_quota ple_qt79;
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const struct rtw89_ple_quota ple_qt_52a_wow;
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const struct rtw89_ple_quota ple_qt_52b_wow;
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const struct rtw89_ple_quota ple_qt_52bt_wow;
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@@ -64,6 +64,32 @@ static const struct rtw89_dle_mem rtw8852c_dle_mem_pcie[] = {
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NULL},
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};
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static const struct rtw89_dle_mem rtw8852c_dle_mem_usb2[] = {
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[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size31,
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&rtw89_mac_size.ple_size34, &rtw89_mac_size.wde_qt31,
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&rtw89_mac_size.wde_qt31, &rtw89_mac_size.ple_qt78,
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&rtw89_mac_size.ple_qt79},
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[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size18,
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&rtw89_mac_size.ple_size18, &rtw89_mac_size.wde_qt17,
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&rtw89_mac_size.wde_qt17, &rtw89_mac_size.ple_qt44,
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&rtw89_mac_size.ple_qt45},
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[RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
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NULL},
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};
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static const struct rtw89_dle_mem rtw8852c_dle_mem_usb3[] = {
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[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size17,
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&rtw89_mac_size.ple_size17, &rtw89_mac_size.wde_qt16,
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&rtw89_mac_size.wde_qt16, &rtw89_mac_size.ple_qt42,
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&rtw89_mac_size.ple_qt43},
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[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size18,
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&rtw89_mac_size.ple_size18, &rtw89_mac_size.wde_qt17,
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&rtw89_mac_size.wde_qt17, &rtw89_mac_size.ple_qt44,
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&rtw89_mac_size.ple_qt45},
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[RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
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NULL},
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};
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static const u32 rtw8852c_h2c_regs[RTW89_H2CREG_MAX] = {
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R_AX_H2CREG_DATA0_V1, R_AX_H2CREG_DATA1_V1, R_AX_H2CREG_DATA2_V1,
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R_AX_H2CREG_DATA3_V1
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@@ -3026,7 +3052,10 @@ const struct rtw89_chip_info rtw8852c_chip_info = {
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.dis_2g_40m_ul_ofdma = false,
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.rsvd_ple_ofst = 0x6f800,
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.hfc_param_ini = {rtw8852c_hfc_param_ini_pcie, NULL, NULL},
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.dle_mem = {rtw8852c_dle_mem_pcie, NULL, NULL, NULL},
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.dle_mem = {rtw8852c_dle_mem_pcie,
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rtw8852c_dle_mem_usb2,
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rtw8852c_dle_mem_usb3,
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NULL},
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.wde_qempty_acq_grpnum = 16,
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.wde_qempty_mgq_grpsel = 16,
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.rf_base_addr = {0xe000, 0xf000},
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