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dt-bindings: display: tegra: document EPP, ISP, MPE and TSEC for Tegra114+

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The current EPP, ISP and MPE schemas are largely compatible with Tegra114+,
requiring only minor adjustments. Additionally, the TSEC schema for the
Security engine, which is available from Tegra114 onwards, is included.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Svyatoslav Ryhel
2025-10-16 10:41:49 +03:00
committed by Thierry Reding
parent ccec106924
commit a0c70244e5
4 changed files with 102 additions and 13 deletions
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68
Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-tsec.yaml Normal file
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@@ -0,0 +1,68 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra114-tsec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra Security co-processor
maintainers:
- Svyatoslav Ryhel <clamor95@gmail.com>
- Thierry Reding <thierry.reding@gmail.com>
description: Tegra Security co-processor, an embedded security processor used
mainly to manage the HDCP encryption and keys on the HDMI link.
properties:
compatible:
oneOf:
- enum:
- nvidia,tegra114-tsec
- nvidia,tegra124-tsec
- nvidia,tegra210-tsec
- items:
- const: nvidia,tegra132-tsec
- const: nvidia,tegra124-tsec
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
iommus:
maxItems: 1
operating-points-v2: true
power-domains:
maxItems: 1
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- resets
examples:
- |
#include <dt-bindings/clock/tegra114-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
tsec@54500000 {
compatible = "nvidia,tegra114-tsec";
reg = <0x54500000 0x00040000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_TSEC>;
resets = <&tegra_car TEGRA114_CLK_TSEC>;
};

14
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml
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@@ -15,10 +15,16 @@ properties:
pattern: "^epp@[0-9a-f]+$"
compatible:
enum:
- nvidia,tegra20-epp
- nvidia,tegra30-epp
- nvidia,tegra114-epp
oneOf:
- enum:
- nvidia,tegra20-epp
- nvidia,tegra30-epp
- nvidia,tegra114-epp
- nvidia,tegra124-epp
- items:
- const: nvidia,tegra132-epp
- const: nvidia,tegra124-epp
reg:
maxItems: 1

15
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml
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@@ -12,10 +12,17 @@ maintainers:
properties:
compatible:
enum:
- nvidia,tegra20-isp
- nvidia,tegra30-isp
- nvidia,tegra210-isp
oneOf:
- enum:
- nvidia,tegra20-isp
- nvidia,tegra30-isp
- nvidia,tegra114-isp
- nvidia,tegra124-isp
- nvidia,tegra210-isp
- items:
- const: nvidia,tegra132-isp
- const: nvidia,tegra124-isp
reg:
maxItems: 1

18
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml
View File

@@ -12,13 +12,21 @@ maintainers:
properties:
$nodename:
pattern: "^mpe@[0-9a-f]+$"
oneOf:
- pattern: "^mpe@[0-9a-f]+$"
- pattern: "^msenc@[0-9a-f]+$"
compatible:
enum:
- nvidia,tegra20-mpe
- nvidia,tegra30-mpe
- nvidia,tegra114-mpe
oneOf:
- enum:
- nvidia,tegra20-mpe
- nvidia,tegra30-mpe
- nvidia,tegra114-msenc
- nvidia,tegra124-msenc
- items:
- const: nvidia,tegra132-msenc
- const: nvidia,tegra124-msenc
reg:
maxItems: 1