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drm/amd/display: Remove dc param from check_update

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[Why]
dc_check_update_surfaces_for_stream should not have access to entire
DC, especially not a mutable one. Concurrent checks should be able
to run independently of one another, without risk of changing state.

[How]
* Replace dc and stream_status structs with new dc_check_config.
* Move required fields from dc_debug and dc_caps to dc_check_config.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Dominik Kaszewski <dominik.kaszewski@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dominik Kaszewski
2025-10-16 08:44:08 +02:00
committed by Alex Deucher
parent 11cc0bdc5b
commit 9ec11bb842
26 changed files with 152 additions and 65 deletions
Download Patch File Download Diff File Expand all files Collapse all files

51
drivers/gpu/drm/amd/display/dc/core/dc.c
View File

@@ -1148,8 +1148,8 @@ static bool dc_construct(struct dc *dc,
/* set i2c speed if not done by the respective dcnxxx__resource.c */
if (dc->caps.i2c_speed_in_khz_hdcp == 0)
dc->caps.i2c_speed_in_khz_hdcp = dc->caps.i2c_speed_in_khz;
if (dc->caps.max_optimizable_video_width == 0)
dc->caps.max_optimizable_video_width = 5120;
if (dc->check_config.max_optimizable_video_width == 0)
dc->check_config.max_optimizable_video_width = 5120;
dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);
if (!dc->clk_mgr)
goto fail;
@@ -2656,7 +2656,7 @@ static bool is_surface_in_context(
return false;
}
static enum surface_update_type get_plane_info_update_type(const struct dc *dc, const struct dc_surface_update *u)
static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u)
{
union surface_update_flags *update_flags = &u->surface->update_flags;
enum surface_update_type update_type = UPDATE_TYPE_FAST;
@@ -2760,7 +2760,7 @@ static enum surface_update_type get_plane_info_update_type(const struct dc *dc,
}
static enum surface_update_type get_scaling_info_update_type(
const struct dc *dc,
const struct dc_check_config *check_config,
const struct dc_surface_update *u)
{
union surface_update_flags *update_flags = &u->surface->update_flags;
@@ -2790,7 +2790,7 @@ static enum surface_update_type get_scaling_info_update_type(
/* Making dst rect smaller requires a bandwidth change */
update_flags->bits.bandwidth_change = 1;
if (u->scaling_info->src_rect.width > dc->caps.max_optimizable_video_width &&
if (u->scaling_info->src_rect.width > check_config->max_optimizable_video_width &&
(u->scaling_info->clip_rect.width > u->surface->clip_rect.width ||
u->scaling_info->clip_rect.height > u->surface->clip_rect.height))
/* Changing clip size of a large surface may result in MPC slice count change */
@@ -2817,7 +2817,8 @@ static enum surface_update_type get_scaling_info_update_type(
return UPDATE_TYPE_FAST;
}
static enum surface_update_type det_surface_update(const struct dc *dc,
static enum surface_update_type det_surface_update(
const struct dc_check_config *check_config,
const struct dc_surface_update *u)
{
enum surface_update_type type;
@@ -2831,10 +2832,10 @@ static enum surface_update_type det_surface_update(const struct dc *dc,
update_flags->raw = 0; // Reset all flags
type = get_plane_info_update_type(dc, u);
type = get_plane_info_update_type(u);
elevate_update_type(&overall_type, type);
type = get_scaling_info_update_type(dc, u);
type = get_scaling_info_update_type(check_config, u);
elevate_update_type(&overall_type, type);
if (u->flip_addr) {
@@ -2911,7 +2912,7 @@ static enum surface_update_type det_surface_update(const struct dc *dc,
elevate_update_type(&overall_type, type);
}
if (dc->debug.enable_legacy_fast_update &&
if (check_config->enable_legacy_fast_update &&
(update_flags->bits.gamma_change ||
update_flags->bits.gamut_remap_change ||
update_flags->bits.input_csc_change ||
@@ -2946,11 +2947,11 @@ static void force_immediate_gsl_plane_flip(struct dc *dc, struct dc_surface_upda
}
static enum surface_update_type check_update_surfaces_for_stream(
struct dc *dc,
const struct dc_check_config *check_config,
struct dc_surface_update *updates,
int surface_count,
struct dc_stream_update *stream_update,
const struct dc_stream_status *stream_status)
struct dc_stream_update *stream_update
)
{
int i;
enum surface_update_type overall_type = UPDATE_TYPE_FAST;
@@ -2972,7 +2973,7 @@ static enum surface_update_type check_update_surfaces_for_stream(
stream_update->integer_scaling_update)
su_flags->bits.scaling = 1;
if (dc->debug.enable_legacy_fast_update && stream_update->out_transfer_func)
if (check_config->enable_legacy_fast_update && stream_update->out_transfer_func)
su_flags->bits.out_tf = 1;
if (stream_update->abm_level)
@@ -3016,13 +3017,13 @@ static enum surface_update_type check_update_surfaces_for_stream(
/* Output transfer function changes do not require bandwidth recalculation,
* so don't trigger a full update
*/
if (!dc->debug.enable_legacy_fast_update && stream_update->out_transfer_func)
if (!check_config->enable_legacy_fast_update && stream_update->out_transfer_func)
su_flags->bits.out_tf = 1;
}
for (i = 0 ; i < surface_count; i++) {
enum surface_update_type type =
det_surface_update(dc, &updates[i]);
det_surface_update(check_config, &updates[i]);
elevate_update_type(&overall_type, type);
}
@@ -3036,22 +3037,17 @@ static enum surface_update_type check_update_surfaces_for_stream(
* See :c:type:`enum surface_update_type <surface_update_type>` for explanation of update types
*/
enum surface_update_type dc_check_update_surfaces_for_stream(
struct dc *dc,
const struct dc_check_config *check_config,
struct dc_surface_update *updates,
int surface_count,
struct dc_stream_update *stream_update,
const struct dc_stream_status *stream_status)
struct dc_stream_update *stream_update)
{
int i;
enum surface_update_type type;
if (stream_update)
stream_update->stream->update_flags.raw = 0;
for (i = 0; i < surface_count; i++)
for (size_t i = 0; i < surface_count; i++)
updates[i].surface->update_flags.raw = 0;
type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
return type;
return check_update_surfaces_for_stream(check_config, updates, surface_count, stream_update);
}
static struct dc_stream_status *stream_get_status(
@@ -3472,8 +3468,7 @@ static bool update_planes_and_stream_state(struct dc *dc,
context = dc->current_state;
update_type = dc_check_update_surfaces_for_stream(
dc, srf_updates, surface_count, stream_update, stream_status);
&dc->check_config, srf_updates, surface_count, stream_update);
if (full_update_required_weak(dc, srf_updates, surface_count, stream_update, stream))
update_type = UPDATE_TYPE_FULL;
@@ -5208,7 +5203,7 @@ static bool update_planes_and_stream_v2(struct dc *dc,
commit_minimal_transition_state_in_dc_update(dc, context, stream,
srf_updates, surface_count);
if (is_fast_update_only && !dc->debug.enable_legacy_fast_update) {
if (is_fast_update_only && !dc->check_config.enable_legacy_fast_update) {
commit_planes_for_stream_fast(dc,
srf_updates,
surface_count,
@@ -5251,7 +5246,7 @@ static void commit_planes_and_stream_update_on_current_context(struct dc *dc,
stream_update);
if (fast_update_only(dc, fast_update, srf_updates, surface_count,
stream_update, stream) &&
!dc->debug.enable_legacy_fast_update)
!dc->check_config.enable_legacy_fast_update)
commit_planes_for_stream_fast(dc,
srf_updates,
surface_count,

17
drivers/gpu/drm/amd/display/dc/dc.h
View File

@@ -286,6 +286,15 @@ struct dc_scl_caps {
bool sharpener_support;
};
struct dc_check_config {
/**
* max video plane width that can be safely assumed to be always
* supported by single DPP pipe.
*/
unsigned int max_optimizable_video_width;
bool enable_legacy_fast_update;
};
struct dc_caps {
uint32_t max_streams;
uint32_t max_links;
@@ -301,11 +310,6 @@ struct dc_caps {
unsigned int max_cursor_size;
unsigned int max_buffered_cursor_size;
unsigned int max_video_width;
/*
* max video plane width that can be safely assumed to be always
* supported by single DPP pipe.
*/
unsigned int max_optimizable_video_width;
unsigned int min_horizontal_blanking_period;
int linear_pitch_alignment;
bool dcc_const_color;
@@ -1128,7 +1132,6 @@ struct dc_debug_options {
uint32_t fpo_vactive_min_active_margin_us;
uint32_t fpo_vactive_max_blank_us;
bool enable_hpo_pg_support;
bool enable_legacy_fast_update;
bool disable_dc_mode_overwrite;
bool replay_skip_crtc_disabled;
bool ignore_pg;/*do nothing, let pmfw control it*/
@@ -1160,7 +1163,6 @@ struct dc_debug_options {
bool enable_ips_visual_confirm;
unsigned int sharpen_policy;
unsigned int scale_to_sharpness_policy;
bool skip_full_updated_if_possible;
unsigned int enable_oled_edp_power_up_opt;
bool enable_hblank_borrow;
bool force_subvp_df_throttle;
@@ -1711,6 +1713,7 @@ struct dc {
struct dc_debug_options debug;
struct dc_versions versions;
struct dc_caps caps;
struct dc_check_config check_config;
struct dc_cap_funcs cap_funcs;
struct dc_config config;
struct dc_bounding_box_overrides bb_overrides;

5
drivers/gpu/drm/amd/display/dc/dc_stream.h
View File

@@ -474,11 +474,10 @@ void dc_enable_stereo(
void dc_trigger_sync(struct dc *dc, struct dc_state *context);
enum surface_update_type dc_check_update_surfaces_for_stream(
struct dc *dc,
const struct dc_check_config *check_config,
struct dc_surface_update *updates,
int surface_count,
struct dc_stream_update *stream_update,
const struct dc_stream_status *stream_status);
struct dc_stream_update *stream_update);
/**
* Create a new default stream for the requested sink

7
drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
View File

@@ -402,8 +402,10 @@ static const struct dc_plane_cap plane_cap = {
}
};
static const struct dc_debug_options debug_defaults = {
.enable_legacy_fast_update = true,
static const struct dc_debug_options debug_defaults = { 0 };
static const struct dc_check_config config_defaults = {
.enable_legacy_fast_update = true,
};
#define CTX ctx
@@ -1093,6 +1095,7 @@ static bool dce100_resource_construct(
dc->caps.disable_dp_clk_share = true;
dc->caps.extended_aux_timeout_support = false;
dc->debug = debug_defaults;
dc->check_config = config_defaults;
for (i = 0; i < pool->base.pipe_count; i++) {
pool->base.timing_generators[i] =

5
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
View File

@@ -424,7 +424,9 @@ static const struct dc_plane_cap plane_cap = {
64
};
static const struct dc_debug_options debug_defaults = {
static const struct dc_debug_options debug_defaults = { 0 };
static const struct dc_check_config config_defaults = {
.enable_legacy_fast_update = true,
};
@@ -1376,6 +1378,7 @@ static bool dce110_resource_construct(
dc->caps.is_apu = true;
dc->caps.extended_aux_timeout_support = false;
dc->debug = debug_defaults;
dc->check_config = config_defaults;
/*************************************************
* Create resources *

7
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
View File

@@ -429,8 +429,10 @@ static const struct dc_plane_cap plane_cap = {
64
};
static const struct dc_debug_options debug_defaults = {
.enable_legacy_fast_update = true,
static const struct dc_debug_options debug_defaults = { 0 };
static const struct dc_check_config config_defaults = {
.enable_legacy_fast_update = true,
};
#define CTX ctx
@@ -1247,6 +1249,7 @@ static bool dce112_resource_construct(
dc->caps.dual_link_dvi = true;
dc->caps.extended_aux_timeout_support = false;
dc->debug = debug_defaults;
dc->check_config = config_defaults;
/*************************************************
* Create resources *

8
drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
View File

@@ -526,8 +526,11 @@ static const struct dc_plane_cap plane_cap = {
};
static const struct dc_debug_options debug_defaults = {
.disable_clock_gate = true,
.enable_legacy_fast_update = true,
.disable_clock_gate = true,
};
static const struct dc_check_config config_defaults = {
.enable_legacy_fast_update = true,
};
static struct clock_source *dce120_clock_source_create(
@@ -1089,6 +1092,7 @@ static bool dce120_resource_construct(
dc->caps.psp_setup_panel_mode = true;
dc->caps.extended_aux_timeout_support = false;
dc->debug = debug_defaults;
dc->check_config = config_defaults;
/*************************************************
* Create resources *

8
drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
View File

@@ -418,8 +418,10 @@ static const struct dc_plane_cap plane_cap = {
}
};
static const struct dc_debug_options debug_defaults = {
.enable_legacy_fast_update = true,
static const struct dc_debug_options debug_defaults = { 0 };
static const struct dc_check_config config_defaults = {
.enable_legacy_fast_update = true,
};
static const struct dce_dmcu_registers dmcu_regs = {
@@ -919,6 +921,7 @@ static bool dce80_construct(
dc->caps.dual_link_dvi = true;
dc->caps.extended_aux_timeout_support = false;
dc->debug = debug_defaults;
dc->check_config = config_defaults;
/*************************************************
* Create resources *
@@ -1320,6 +1323,7 @@ static bool dce83_construct(
dc->caps.min_horizontal_blanking_period = 80;
dc->caps.is_apu = true;
dc->debug = debug_defaults;
dc->check_config = config_defaults;
/*************************************************
* Create resources *

7
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
View File

@@ -556,10 +556,13 @@ static const struct dc_debug_options debug_defaults_drv = {
.recovery_enabled = false, /*enable this by default after testing.*/
.max_downscale_src_width = 3840,
.underflow_assert_delay_us = 0xFFFFFFFF,
.enable_legacy_fast_update = true,
.using_dml2 = false,
};
static const struct dc_check_config config_defaults = {
.enable_legacy_fast_update = true,
};
static void dcn10_dpp_destroy(struct dpp **dpp)
{
kfree(TO_DCN10_DPP(*dpp));
@@ -1395,6 +1398,8 @@ static bool dcn10_resource_construct(
dc->caps.color.mpc.ogam_rom_caps.pq = 0;
dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
dc->caps.color.mpc.ocsc = 0;
dc->debug = debug_defaults_drv;
dc->check_config = config_defaults;
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;

6
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
View File

@@ -718,10 +718,13 @@ static const struct dc_debug_options debug_defaults_drv = {
.scl_reset_length10 = true,
.sanity_checks = false,
.underflow_assert_delay_us = 0xFFFFFFFF,
.enable_legacy_fast_update = true,
.using_dml2 = false,
};
static const struct dc_check_config config_defaults = {
.enable_legacy_fast_update = true,
};
void dcn20_dpp_destroy(struct dpp **dpp)
{
kfree(TO_DCN20_DPP(*dpp));
@@ -2471,6 +2474,7 @@ static bool dcn20_resource_construct(
dc->caps.color.mpc.ocsc = 1;
dc->caps.dp_hdmi21_pcon_support = true;
dc->check_config = config_defaults;
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;

6
drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
View File

@@ -614,10 +614,13 @@ static const struct dc_debug_options debug_defaults_drv = {
.sanity_checks = false,
.underflow_assert_delay_us = 0xFFFFFFFF,
.enable_tri_buf = true,
.enable_legacy_fast_update = true,
.using_dml2 = false,
};
static const struct dc_check_config config_defaults = {
.enable_legacy_fast_update = true,
};
static void dcn201_dpp_destroy(struct dpp **dpp)
{
kfree(TO_DCN201_DPP(*dpp));
@@ -1151,6 +1154,7 @@ static bool dcn201_resource_construct(
dc->caps.color.mpc.ocsc = 1;
dc->debug = debug_defaults_drv;
dc->check_config = config_defaults;
/*a0 only, remove later*/
dc->work_arounds.no_connect_phy_config = true;

6
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
View File

@@ -626,10 +626,13 @@ static const struct dc_debug_options debug_defaults_drv = {
.usbc_combo_phy_reset_wa = true,
.dmub_command_table = true,
.use_max_lb = true,
.enable_legacy_fast_update = true,
.using_dml2 = false,
};
static const struct dc_check_config config_defaults = {
.enable_legacy_fast_update = true,
};
static const struct dc_panel_config panel_config_defaults = {
.psr = {
.disable_psr = false,
@@ -1458,6 +1461,7 @@ static bool dcn21_resource_construct(
dc->caps.color.mpc.ocsc = 1;
dc->caps.dp_hdmi21_pcon_support = true;
dc->check_config = config_defaults;
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;

6
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
View File

@@ -727,10 +727,13 @@ static const struct dc_debug_options debug_defaults_drv = {
.dmub_command_table = true,
.use_max_lb = true,
.exit_idle_opt_for_cursor_updates = true,
.enable_legacy_fast_update = false,
.using_dml2 = false,
};
static const struct dc_check_config config_defaults = {
.enable_legacy_fast_update = false,
};
static const struct dc_panel_config panel_config_defaults = {
.psr = {
.disable_psr = false,
@@ -2374,6 +2377,7 @@ static bool dcn30_resource_construct(
dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
}
}
dc->check_config = config_defaults;
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;

6
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
View File

@@ -701,10 +701,13 @@ static const struct dc_debug_options debug_defaults_drv = {
.dmub_command_table = true,
.use_max_lb = false,
.exit_idle_opt_for_cursor_updates = true,
.enable_legacy_fast_update = true,
.using_dml2 = false,
};
static const struct dc_check_config config_defaults = {
.enable_legacy_fast_update = true,
};
static void dcn301_dpp_destroy(struct dpp **dpp)
{
kfree(TO_DCN20_DPP(*dpp));
@@ -1498,6 +1501,7 @@ static bool dcn301_resource_construct(
bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, &is_vbios_interop_enabled);
dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
}
dc->check_config = config_defaults;
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;

6
drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
View File

@@ -98,10 +98,13 @@ static const struct dc_debug_options debug_defaults_drv = {
.dmub_command_table = true,
.use_max_lb = true,
.exit_idle_opt_for_cursor_updates = true,
.enable_legacy_fast_update = false,
.using_dml2 = false,
};
static const struct dc_check_config config_defaults = {
.enable_legacy_fast_update = false,
};
static const struct dc_panel_config panel_config_defaults = {
.psr = {
.disable_psr = false,
@@ -1290,6 +1293,7 @@ static bool dcn302_resource_construct(
&is_vbios_interop_enabled);
dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
}
dc->check_config = config_defaults;
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;

6
drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
View File

@@ -98,10 +98,13 @@ static const struct dc_debug_options debug_defaults_drv = {
.dmub_command_table = true,
.use_max_lb = true,
.exit_idle_opt_for_cursor_updates = true,
.enable_legacy_fast_update = false,
.using_dml2 = false,
};
static const struct dc_check_config config_defaults = {
.enable_legacy_fast_update = false,
};
static const struct dc_panel_config panel_config_defaults = {
.psr = {
.disable_psr = false,
@@ -1234,6 +1237,7 @@ static bool dcn303_resource_construct(
bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, &is_vbios_interop_enabled);
dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
}
dc->check_config = config_defaults;
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;

6
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
View File

@@ -888,12 +888,15 @@ static const struct dc_debug_options debug_defaults_drv = {
}
},
.disable_z10 = true,
.enable_legacy_fast_update = true,
.enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
.dml_hostvm_override = DML_HOSTVM_OVERRIDE_FALSE,
.using_dml2 = false,
};
static const struct dc_check_config config_defaults = {
.enable_legacy_fast_update = true,
};
static const struct dc_panel_config panel_config_defaults = {
.psr = {
.disable_psr = false,
@@ -1978,6 +1981,7 @@ static bool dcn31_resource_construct(
dc->caps.vbios_lttpr_aware = true;
}
}
dc->check_config = config_defaults;
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;

6
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
View File

@@ -924,12 +924,15 @@ static const struct dc_debug_options debug_defaults_drv = {
},
.seamless_boot_odm_combine = true,
.enable_legacy_fast_update = true,
.using_dml2 = false,
.disable_dsc_power_gate = true,
.min_disp_clk_khz = 100000,
};
static const struct dc_check_config config_defaults = {
.enable_legacy_fast_update = true,
};
static const struct dc_panel_config panel_config_defaults = {
.psr = {
.disable_psr = false,
@@ -1910,6 +1913,7 @@ static bool dcn314_resource_construct(
dc->caps.vbios_lttpr_aware = true;
}
}
dc->check_config = config_defaults;
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;

6
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
View File

@@ -887,11 +887,14 @@ static const struct dc_debug_options debug_defaults_drv = {
.afmt = true,
}
},
.enable_legacy_fast_update = true,
.psr_power_use_phy_fsm = 0,
.using_dml2 = false,
};
static const struct dc_check_config config_defaults = {
.enable_legacy_fast_update = true,
};
static const struct dc_panel_config panel_config_defaults = {
.psr = {
.disable_psr = false,
@@ -1939,6 +1942,7 @@ static bool dcn315_resource_construct(
dc->caps.vbios_lttpr_aware = true;
}
}
dc->check_config = config_defaults;
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;

6
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
View File

@@ -882,10 +882,13 @@ static const struct dc_debug_options debug_defaults_drv = {
.afmt = true,
}
},
.enable_legacy_fast_update = true,
.using_dml2 = false,
};
static const struct dc_check_config config_defaults = {
.enable_legacy_fast_update = true,
};
static const struct dc_panel_config panel_config_defaults = {
.psr = {
.disable_psr = false,
@@ -1815,6 +1818,7 @@ static bool dcn316_resource_construct(
dc->caps.vbios_lttpr_aware = true;
}
}
dc->check_config = config_defaults;
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;

6
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
View File

@@ -738,10 +738,13 @@ static const struct dc_debug_options debug_defaults_drv = {
.disable_dp_plus_plus_wa = true,
.fpo_vactive_min_active_margin_us = 200,
.fpo_vactive_max_blank_us = 1000,
.enable_legacy_fast_update = false,
.disable_stutter_for_wm_program = true
};
static const struct dc_check_config config_defaults = {
.enable_legacy_fast_update = false,
};
static struct dce_aux *dcn32_aux_engine_create(
struct dc_context *ctx,
uint32_t inst)
@@ -2294,6 +2297,7 @@ static bool dcn32_resource_construct(
dc->caps.vbios_lttpr_aware = true;
}
}
dc->check_config = config_defaults;
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;

6
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
View File

@@ -731,11 +731,14 @@ static const struct dc_debug_options debug_defaults_drv = {
.disable_subvp_high_refresh = false,
.fpo_vactive_min_active_margin_us = 200,
.fpo_vactive_max_blank_us = 1000,
.enable_legacy_fast_update = false,
.disable_dc_mode_overwrite = true,
.using_dml2 = false,
};
static const struct dc_check_config config_defaults = {
.enable_legacy_fast_update = false,
};
static struct dce_aux *dcn321_aux_engine_create(
struct dc_context *ctx,
uint32_t inst)
@@ -1797,6 +1800,7 @@ static bool dcn321_resource_construct(
dc->caps.vbios_lttpr_aware = true;
}
}
dc->check_config = config_defaults;
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;

6
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
View File

@@ -767,7 +767,6 @@ static const struct dc_debug_options debug_defaults_drv = {
.using_dml2 = true,
.support_eDP1_5 = true,
.enable_hpo_pg_support = false,
.enable_legacy_fast_update = true,
.enable_single_display_2to1_odm_policy = true,
.disable_idle_power_optimizations = false,
.dmcub_emulation = false,
@@ -788,6 +787,10 @@ static const struct dc_debug_options debug_defaults_drv = {
.min_disp_clk_khz = 50000,
};
static const struct dc_check_config config_defaults = {
.enable_legacy_fast_update = true,
};
static const struct dc_panel_config panel_config_defaults = {
.psr = {
.disable_psr = false,
@@ -1946,6 +1949,7 @@ static bool dcn35_resource_construct(
dc->caps.vbios_lttpr_aware = true;
}
}
dc->check_config = config_defaults;
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;

6
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
View File

@@ -747,7 +747,6 @@ static const struct dc_debug_options debug_defaults_drv = {
.using_dml2 = true,
.support_eDP1_5 = true,
.enable_hpo_pg_support = false,
.enable_legacy_fast_update = true,
.enable_single_display_2to1_odm_policy = true,
.disable_idle_power_optimizations = false,
.dmcub_emulation = false,
@@ -768,6 +767,10 @@ static const struct dc_debug_options debug_defaults_drv = {
.min_disp_clk_khz = 50000,
};
static const struct dc_check_config config_defaults = {
.enable_legacy_fast_update = true,
};
static const struct dc_panel_config panel_config_defaults = {
.psr = {
.disable_psr = false,
@@ -1917,6 +1920,7 @@ static bool dcn351_resource_construct(
dc->caps.vbios_lttpr_aware = true;
}
}
dc->check_config = config_defaults;
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;

6
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
View File

@@ -748,7 +748,6 @@ static const struct dc_debug_options debug_defaults_drv = {
.using_dml2 = true,
.support_eDP1_5 = true,
.enable_hpo_pg_support = false,
.enable_legacy_fast_update = true,
.enable_single_display_2to1_odm_policy = true,
.disable_idle_power_optimizations = false,
.dmcub_emulation = false,
@@ -769,6 +768,10 @@ static const struct dc_debug_options debug_defaults_drv = {
.min_disp_clk_khz = 50000,
};
static const struct dc_check_config config_defaults = {
.enable_legacy_fast_update = true,
};
static const struct dc_panel_config panel_config_defaults = {
.psr = {
.disable_psr = false,
@@ -1918,6 +1921,7 @@ static bool dcn36_resource_construct(
dc->caps.vbios_lttpr_aware = true;
}
}
dc->check_config = config_defaults;
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;

6
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
View File

@@ -721,7 +721,6 @@ static const struct dc_debug_options debug_defaults_drv = {
.alloc_extra_way_for_cursor = true,
.min_prefetch_in_strobe_ns = 60000, // 60us
.disable_unbounded_requesting = false,
.enable_legacy_fast_update = false,
.dcc_meta_propagation_delay_us = 10,
.fams_version = {
.minor = 1,
@@ -737,6 +736,10 @@ static const struct dc_debug_options debug_defaults_drv = {
.force_cositing = CHROMA_COSITING_NONE + 1,
};
static const struct dc_check_config config_defaults = {
.enable_legacy_fast_update = false,
};
static struct dce_aux *dcn401_aux_engine_create(
struct dc_context *ctx,
uint32_t inst)
@@ -1995,6 +1998,7 @@ static bool dcn401_resource_construct(
dc->caps.vbios_lttpr_aware = true;
}
}
dc->check_config = config_defaults;
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
dc->debug = debug_defaults_drv;