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drm/rcar-du: dsi: Clean up handling of DRM mode flags

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Introduce TXVMVPRMSET0R_BPP_MASK macro and use FIELD_PREP() to generate
appropriate bitfield from mask and value without bitshift, assign this
value into vprmset0r. Remove TXVMVPRMSET0R_CSPC_RGB which is never used,
replace it with code comment next to TXVMVPRMSET0R_CSPC_YCbCr.

Replace (mode->flags & DRM_MODE_FLAG_P.SYNC) test with inverted conditional
(mode->flags & DRM_MODE_FLAG_N.SYNC) and bitwise orr vprmset0r with either
or both TXVMVPRMSET0R_HSPOL_LOW and TXVMVPRMSET0R_VSPOL_LOW if conditional
matches.

Do not convert bits and bitfields to BIT() and GENMASK() yet, to be
consisten with the current style. Conversion to BIT() and GENMASK()
macros is done at the very end of this series in the last two patches.

Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Link: https://patch.msgid.link/20251028232959.109936-10-marek.vasut+renesas@mailbox.org
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
This commit is contained in:
Marek Vasut
2025-10-29 00:28:19 +01:00
committed by Tomi Valkeinen
parent dd3957e026
commit 94fe479fae
2 changed files with 13 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c
View File

@@ -490,12 +490,12 @@ static void rcar_mipi_dsi_set_display_timing(struct rcar_mipi_dsi *dsi,
rcar_mipi_dsi_write(dsi, TXVMSETR, setr);
/* Configuration for Video Parameters */
vprmset0r = (mode->flags & DRM_MODE_FLAG_PVSYNC ?
TXVMVPRMSET0R_VSPOL_HIG : TXVMVPRMSET0R_VSPOL_LOW)
| (mode->flags & DRM_MODE_FLAG_PHSYNC ?
TXVMVPRMSET0R_HSPOL_HIG : TXVMVPRMSET0R_HSPOL_LOW)
| TXVMVPRMSET0R_CSPC_RGB | TXVMVPRMSET0R_BPP_24;
/* Configuration for Video Parameters, input is always RGB888 */
vprmset0r = TXVMVPRMSET0R_BPP_24;
if (mode->flags & DRM_MODE_FLAG_NVSYNC)
vprmset0r |= TXVMVPRMSET0R_VSPOL_LOW;
if (mode->flags & DRM_MODE_FLAG_NHSYNC)
vprmset0r |= TXVMVPRMSET0R_HSPOL_LOW;
vprmset1r = TXVMVPRMSET1R_VACTIVE(mode->vdisplay)
| TXVMVPRMSET1R_VSA(mode->vsync_end - mode->vsync_start);

16
drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h
View File

@@ -171,15 +171,13 @@
#define TXVMPSPHSETR_DT_YCBCR16 FIELD_PREP(TXVMPSPHSETR_DT_MASK, 0x2c)
#define TXVMVPRMSET0R 0x1d0
#define TXVMVPRMSET0R_HSPOL_HIG (0 << 17)
#define TXVMVPRMSET0R_HSPOL_LOW (1 << 17)
#define TXVMVPRMSET0R_VSPOL_HIG (0 << 16)
#define TXVMVPRMSET0R_VSPOL_LOW (1 << 16)
#define TXVMVPRMSET0R_CSPC_RGB (0 << 4)
#define TXVMVPRMSET0R_CSPC_YCbCr (1 << 4)
#define TXVMVPRMSET0R_BPP_16 (0 << 0)
#define TXVMVPRMSET0R_BPP_18 (1 << 0)
#define TXVMVPRMSET0R_BPP_24 (2 << 0)
#define TXVMVPRMSET0R_HSPOL_LOW (1 << 17) /* 0:High 1:Low */
#define TXVMVPRMSET0R_VSPOL_LOW (1 << 16) /* 0:High 1:Low */
#define TXVMVPRMSET0R_CSPC_YCbCr (1 << 4) /* 0:RGB 1:YCbCr */
#define TXVMVPRMSET0R_BPP_MASK (7 << 0)
#define TXVMVPRMSET0R_BPP_16 FIELD_PREP(TXVMVPRMSET0R_BPP_MASK, 0)
#define TXVMVPRMSET0R_BPP_18 FIELD_PREP(TXVMVPRMSET0R_BPP_MASK, 1)
#define TXVMVPRMSET0R_BPP_24 FIELD_PREP(TXVMVPRMSET0R_BPP_MASK, 2)
#define TXVMVPRMSET1R 0x1d4
#define TXVMVPRMSET1R_VACTIVE(x) (((x) & 0x7fff) << 16)