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cache: sifive_ccache: Optimize cache flushes

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Fence instructions are required only at the beginning and the end of
a flush operation, not separately for each cache line being flushed.
Speed up cache flushes by about 15% by removing the extra fences.

Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Samuel Holland
2025-09-09 15:41:27 -07:00
committed by Conor Dooley
parent 4fab69dd1f
commit 941327ca5d
1 changed files with 4 additions and 4 deletions
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8
drivers/cache/sifive_ccache.c vendored
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@@ -151,16 +151,16 @@ static void ccache_flush_range(phys_addr_t start, size_t len)
if (!len)
return;
mb();
mb(); /* complete earlier memory accesses before the cache flush */
for (line = ALIGN_DOWN(start, SIFIVE_CCACHE_LINE_SIZE); line < end;
line += SIFIVE_CCACHE_LINE_SIZE) {
#ifdef CONFIG_32BIT
writel(line >> 4, ccache_base + SIFIVE_CCACHE_FLUSH32);
writel_relaxed(line >> 4, ccache_base + SIFIVE_CCACHE_FLUSH32);
#else
writeq(line, ccache_base + SIFIVE_CCACHE_FLUSH64);
writeq_relaxed(line, ccache_base + SIFIVE_CCACHE_FLUSH64);
#endif
mb();
}
mb(); /* issue later memory accesses after the cache flush */
}
static const struct riscv_nonstd_cache_ops ccache_mgmt_ops __initconst = {