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ARM: dts: socfpga: add Enclustra SoM dts files

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Add the approach to set up a combination of Enclustra's SoM on a carrier
board and corresponding boot-mode as single device-tree target.

Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
This commit is contained in:
Lothar Rubusch
2025-10-18 12:11:55 +00:00
committed by Dinh Nguyen
parent 558417387b
commit 91b97ca3d4
25 changed files with 408 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
arch/arm/boot/dts/intel/socfpga/Makefile
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@@ -2,6 +2,30 @@
dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
socfpga_arria10_chameleonv3.dtb \
socfpga_arria10_mercury_aa1_pe1_emmc.dtb \
socfpga_arria10_mercury_aa1_pe1_qspi.dtb \
socfpga_arria10_mercury_aa1_pe1_sdmmc.dtb \
socfpga_arria10_mercury_aa1_pe3_emmc.dtb \
socfpga_arria10_mercury_aa1_pe3_qspi.dtb \
socfpga_arria10_mercury_aa1_pe3_sdmmc.dtb \
socfpga_arria10_mercury_aa1_st1_emmc.dtb \
socfpga_arria10_mercury_aa1_st1_qspi.dtb \
socfpga_arria10_mercury_aa1_st1_sdmmc.dtb \
socfpga_cyclone5_mercury_sa1_pe1_emmc.dtb \
socfpga_cyclone5_mercury_sa1_pe1_qspi.dtb \
socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dtb \
socfpga_cyclone5_mercury_sa1_pe3_emmc.dtb \
socfpga_cyclone5_mercury_sa1_pe3_qspi.dtb \
socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dtb \
socfpga_cyclone5_mercury_sa1_st1_emmc.dtb \
socfpga_cyclone5_mercury_sa1_st1_qspi.dtb \
socfpga_cyclone5_mercury_sa1_st1_sdmmc.dtb \
socfpga_cyclone5_mercury_sa2_pe1_qspi.dtb \
socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dtb \
socfpga_cyclone5_mercury_sa2_pe3_qspi.dtb \
socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dtb \
socfpga_cyclone5_mercury_sa2_st1_qspi.dtb \
socfpga_cyclone5_mercury_sa2_st1_sdmmc.dtb \
socfpga_arria10_socdk_nand.dtb \
socfpga_arria10_socdk_qspi.dtb \
socfpga_arria10_socdk_sdmmc.dtb \

16
arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_emmc.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
*/
/dts-v1/;
#include "socfpga_arria10_mercury_aa1.dtsi"
#include "socfpga_enclustra_mercury_pe1.dtsi"
#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi"
/ {
model = "Enclustra Mercury SA1 on Mercury+ PE1 Base Board";
compatible = "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1",
"altr,socfpga-cyclone5", "altr,socfpga";
};

16
arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_qspi.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
*/
/dts-v1/;
#include "socfpga_arria10_mercury_aa1.dtsi"
#include "socfpga_enclustra_mercury_pe1.dtsi"
#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi"
/ {
model = "Enclustra Mercury+ AA1 on Mercury+ PE1 Base Board";
compatible = "enclustra,mercury-aa1-pe1", "enclustra,mercury-aa1",
"altr,socfpga-arria10", "altr,socfpga";
};

16
arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_sdmmc.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
*/
/dts-v1/;
#include "socfpga_arria10_mercury_aa1.dtsi"
#include "socfpga_enclustra_mercury_pe1.dtsi"
#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi"
/ {
model = "Enclustra Mercury+ AA1 on Mercury+ PE1 Base Board";
compatible = "enclustra,mercury-aa1-pe1", "enclustra,mercury-aa1",
"altr,socfpga-arria10", "altr,socfpga";
};

16
arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_emmc.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
*/
/dts-v1/;
#include "socfpga_arria10_mercury_aa1.dtsi"
#include "socfpga_enclustra_mercury_pe3.dtsi"
#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi"
/ {
model = "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board";
compatible = "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1",
"altr,socfpga-arria10", "altr,socfpga";
};

16
arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_qspi.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
*/
/dts-v1/;
#include "socfpga_arria10_mercury_aa1.dtsi"
#include "socfpga_enclustra_mercury_pe3.dtsi"
#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi"
/ {
model = "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board";
compatible = "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1",
"altr,socfpga-arria10", "altr,socfpga";
};

16
arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_sdmmc.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
*/
/dts-v1/;
#include "socfpga_arria10_mercury_aa1.dtsi"
#include "socfpga_enclustra_mercury_pe3.dtsi"
#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi"
/ {
model = "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board";
compatible = "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1",
"altr,socfpga-arria10", "altr,socfpga";
};

16
arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_emmc.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
*/
/dts-v1/;
#include "socfpga_arria10_mercury_aa1.dtsi"
#include "socfpga_enclustra_mercury_st1.dtsi"
#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi"
/ {
model = "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board";
compatible = "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1",
"altr,socfpga-arria10", "altr,socfpga";
};

16
arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_qspi.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
*/
/dts-v1/;
#include "socfpga_arria10_mercury_aa1.dtsi"
#include "socfpga_enclustra_mercury_st1.dtsi"
#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi"
/ {
model = "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board";
compatible = "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1",
"altr,socfpga-arria10", "altr,socfpga";
};

16
arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_sdmmc.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
*/
/dts-v1/;
#include "socfpga_arria10_mercury_aa1.dtsi"
#include "socfpga_enclustra_mercury_st1.dtsi"
#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi"
/ {
model = "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board";
compatible = "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1",
"altr,socfpga-arria10", "altr,socfpga";
};

16
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_emmc.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
*/
/dts-v1/;
#include "socfpga_cyclone5_mercury_sa1.dtsi"
#include "socfpga_enclustra_mercury_pe1.dtsi"
#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi"
/ {
model = "Enclustra Mercury SA1 on Mercury+ PE1 Base Board";
compatible = "enclustra,mercury-sa1-pe1", "enclustra,mercury-aa1",
"altr,socfpga-arria10", "altr,socfpga";
};

16
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_qspi.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
*/
/dts-v1/;
#include "socfpga_cyclone5_mercury_sa1.dtsi"
#include "socfpga_enclustra_mercury_pe1.dtsi"
#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi"
/ {
model = "Enclustra Mercury SA1 on Mercury+ PE1 Base Board";
compatible = "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1",
"altr,socfpga-cyclone5", "altr,socfpga";
};

16
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
*/
/dts-v1/;
#include "socfpga_cyclone5_mercury_sa1.dtsi"
#include "socfpga_enclustra_mercury_pe1.dtsi"
#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi"
/ {
model = "Enclustra Mercury SA1 on Mercury+ PE1 Base Board";
compatible = "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1",
"altr,socfpga-cyclone5", "altr,socfpga";
};

16
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_emmc.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
*/
/dts-v1/;
#include "socfpga_cyclone5_mercury_sa1.dtsi"
#include "socfpga_enclustra_mercury_pe3.dtsi"
#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi"
/ {
model = "Enclustra Mercury SA1 on Mercury+ PE3 Base Board";
compatible = "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1",
"altr,socfpga-cyclone5", "altr,socfpga";
};

16
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_qspi.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
*/
/dts-v1/;
#include "socfpga_cyclone5_mercury_sa1.dtsi"
#include "socfpga_enclustra_mercury_pe3.dtsi"
#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi"
/ {
model = "Enclustra Mercury SA1 on Mercury+ PE3 Base Board";
compatible = "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1",
"altr,socfpga-cyclone5", "altr,socfpga";
};

16
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
*/
/dts-v1/;
#include "socfpga_cyclone5_mercury_sa1.dtsi"
#include "socfpga_enclustra_mercury_pe3.dtsi"
#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi"
/ {
model = "Enclustra Mercury SA1 on Mercury+ PE3 Base Board";
compatible = "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1",
"altr,socfpga-cyclone5", "altr,socfpga";
};

16
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_emmc.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
*/
/dts-v1/;
#include "socfpga_cyclone5_mercury_sa1.dtsi"
#include "socfpga_enclustra_mercury_st1.dtsi"
#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi"
/ {
model = "Enclustra Mercury SA1 on Mercury+ ST1 Base Board";
compatible = "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1",
"altr,socfpga-cyclone5", "altr,socfpga";
};

16
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_qspi.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
*/
/dts-v1/;
#include "socfpga_cyclone5_mercury_sa1.dtsi"
#include "socfpga_enclustra_mercury_st1.dtsi"
#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi"
/ {
model = "Enclustra Mercury SA1 on Mercury+ ST1 Base Board";
compatible = "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1",
"altr,socfpga-cyclone5", "altr,socfpga";
};

16
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_sdmmc.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
*/
/dts-v1/;
#include "socfpga_cyclone5_mercury_sa1.dtsi"
#include "socfpga_enclustra_mercury_st1.dtsi"
#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi"
/ {
model = "Enclustra Mercury SA1 on Mercury+ ST1 Base Board";
compatible = "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1",
"altr,socfpga-cyclone5", "altr,socfpga";
};

16
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_qspi.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
*/
/dts-v1/;
#include "socfpga_cyclone5_mercury_sa2.dtsi"
#include "socfpga_enclustra_mercury_pe1.dtsi"
#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi"
/ {
model = "Enclustra Mercury+ SA2 on Mercury+ PE1 Base Board";
compatible = "enclustra,mercury-sa2-pe1", "enclustra,mercury-sa2",
"altr,socfpga-cyclone5", "altr,socfpga";
};

16
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
*/
/dts-v1/;
#include "socfpga_cyclone5_mercury_sa2.dtsi"
#include "socfpga_enclustra_mercury_pe1.dtsi"
#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi"
/ {
model = "Enclustra Mercury+ SA2 on Mercury+ PE1 Base Board";
compatible = "enclustra,mercury-sa2-pe1", "enclustra,mercury-sa2",
"altr,socfpga-cyclone5", "altr,socfpga";
};

16
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_qspi.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
*/
/dts-v1/;
#include "socfpga_cyclone5_mercury_sa2.dtsi"
#include "socfpga_enclustra_mercury_pe3.dtsi"
#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi"
/ {
model = "Enclustra Mercury+ SA2 on Mercury+ PE3 Base Board";
compatible = "enclustra,mercury-sa2-pe3", "enclustra,mercury-sa2",
"altr,socfpga-cyclone5", "altr,socfpga";
};

16
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
*/
/dts-v1/;
#include "socfpga_cyclone5_mercury_sa2.dtsi"
#include "socfpga_enclustra_mercury_pe3.dtsi"
#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi"
/ {
model = "Enclustra Mercury+ SA2 on Mercury+ PE3 Base Board";
compatible = "enclustra,mercury-sa2-pe3", "enclustra,mercury-sa2",
"altr,socfpga-cyclone5", "altr,socfpga";
};

16
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_qspi.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
*/
/dts-v1/;
#include "socfpga_cyclone5_mercury_sa2.dtsi"
#include "socfpga_enclustra_mercury_st1.dtsi"
#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi"
/ {
model = "Enclustra Mercury+ SA2 on Mercury+ ST1 Base Board";
compatible = "enclustra,mercury-sa2-st1", "enclustra,mercury-sa2",
"altr,socfpga-cyclone5", "altr,socfpga";
};

16
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_sdmmc.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
*/
/dts-v1/;
#include "socfpga_cyclone5_mercury_sa2.dtsi"
#include "socfpga_enclustra_mercury_st1.dtsi"
#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi"
/ {
model = "Enclustra Mercury+ SA2 on Mercury+ ST1 Base Board";
compatible = "enclustra,mercury-sa2-st1", "enclustra,mercury-sa2",
"altr,socfpga-cyclone5", "altr,socfpga";
};