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net: stmmac: move common DMA AXI register bits to common.h
Move the common DMA AXI register bits to common.h so they can be shared and we can provide a common function to convert the axi->dma_blen[] array to the format needed for this register. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Link: https://patch.msgid.link/E1vLfLL-0000000FMap-49gf@rmk-PC.armlinux.org.uk Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
committed by
Jakub Kicinski
parent
f7ac9a0bbe
commit
8c696659f4
@@ -548,6 +548,16 @@ struct dma_features {
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#define LPI_CTRL_STATUS_TLPIEX BIT(1) /* Transmit LPI Exit */
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#define LPI_CTRL_STATUS_TLPIEN BIT(0) /* Transmit LPI Entry */
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/* Common definitions for AXI Master Bus Mode */
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#define DMA_AXI_AAL BIT(12)
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#define DMA_AXI_BLEN256 BIT(7)
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#define DMA_AXI_BLEN128 BIT(6)
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#define DMA_AXI_BLEN64 BIT(5)
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#define DMA_AXI_BLEN32 BIT(4)
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#define DMA_AXI_BLEN16 BIT(3)
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#define DMA_AXI_BLEN8 BIT(2)
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#define DMA_AXI_BLEN4 BIT(1)
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#define STMMAC_CHAIN_MODE 0x1
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#define STMMAC_RING_MODE 0x2
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@@ -69,15 +69,8 @@
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#define DMA_SYS_BUS_MB BIT(14)
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#define DMA_AXI_1KBBE BIT(13)
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#define DMA_SYS_BUS_AAL BIT(12)
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#define DMA_SYS_BUS_AAL DMA_AXI_AAL
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#define DMA_SYS_BUS_EAME BIT(11)
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#define DMA_AXI_BLEN256 BIT(7)
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#define DMA_AXI_BLEN128 BIT(6)
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#define DMA_AXI_BLEN64 BIT(5)
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#define DMA_AXI_BLEN32 BIT(4)
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#define DMA_AXI_BLEN16 BIT(3)
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#define DMA_AXI_BLEN8 BIT(2)
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#define DMA_AXI_BLEN4 BIT(1)
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#define DMA_SYS_BUS_FB BIT(0)
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#define DMA_BURST_LEN_DEFAULT (DMA_AXI_BLEN256 | DMA_AXI_BLEN128 | \
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@@ -68,20 +68,13 @@ static inline u32 dma_chan_base_addr(u32 base, u32 chan)
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#define DMA_AXI_OSR_MAX 0xf
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#define DMA_AXI_MAX_OSR_LIMIT ((DMA_AXI_OSR_MAX << DMA_AXI_WR_OSR_LMT_SHIFT) | \
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(DMA_AXI_OSR_MAX << DMA_AXI_RD_OSR_LMT_SHIFT))
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#define DMA_AXI_1KBBE BIT(13)
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#define DMA_AXI_AAL BIT(12)
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#define DMA_AXI_BLEN256 BIT(7)
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#define DMA_AXI_BLEN128 BIT(6)
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#define DMA_AXI_BLEN64 BIT(5)
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#define DMA_AXI_BLEN32 BIT(4)
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#define DMA_AXI_BLEN16 BIT(3)
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#define DMA_AXI_BLEN8 BIT(2)
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#define DMA_AXI_BLEN4 BIT(1)
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#define DMA_BURST_LEN_DEFAULT (DMA_AXI_BLEN256 | DMA_AXI_BLEN128 | \
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DMA_AXI_BLEN64 | DMA_AXI_BLEN32 | \
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DMA_AXI_BLEN16 | DMA_AXI_BLEN8 | \
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DMA_AXI_BLEN4)
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#define DMA_AXI_1KBBE BIT(13)
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#define DMA_AXI_UNDEF BIT(0)
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#define DMA_AXI_BURST_LEN_MASK 0x000000FE
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@@ -338,16 +338,16 @@
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#define XGMAC_RD_OSR_LMT_SHIFT 16
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#define XGMAC_EN_LPI BIT(15)
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#define XGMAC_LPI_XIT_PKT BIT(14)
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#define XGMAC_AAL BIT(12)
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#define XGMAC_AAL DMA_AXI_AAL
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#define XGMAC_EAME BIT(11)
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#define XGMAC_BLEN GENMASK(7, 1)
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#define XGMAC_BLEN256 BIT(7)
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#define XGMAC_BLEN128 BIT(6)
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#define XGMAC_BLEN64 BIT(5)
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#define XGMAC_BLEN32 BIT(4)
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#define XGMAC_BLEN16 BIT(3)
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#define XGMAC_BLEN8 BIT(2)
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#define XGMAC_BLEN4 BIT(1)
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#define XGMAC_BLEN256 DMA_AXI_BLEN256
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#define XGMAC_BLEN128 DMA_AXI_BLEN128
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#define XGMAC_BLEN64 DMA_AXI_BLEN64
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#define XGMAC_BLEN32 DMA_AXI_BLEN32
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#define XGMAC_BLEN16 DMA_AXI_BLEN16
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#define XGMAC_BLEN8 DMA_AXI_BLEN8
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#define XGMAC_BLEN4 DMA_AXI_BLEN4
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#define XGMAC_UNDEF BIT(0)
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#define XGMAC_TX_EDMA_CTRL 0x00003040
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#define XGMAC_TDPS GENMASK(29, 0)
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