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drm/i915/ltphy: Define function to readout LT Phy PLL state

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Define a function to readout hw state for LT Phy PLL which
can be used in get_config function call.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-23-suraj.kandpal@intel.com
This commit is contained in:
Suraj Kandpal
2025-11-01 08:55:10 +05:30
parent 3a6f155ce0
commit 89e0a91e89
3 changed files with 50 additions and 0 deletions
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14
drivers/gpu/drm/i915/display/intel_ddi.c
View File

@@ -4246,6 +4246,19 @@ void intel_ddi_get_clock(struct intel_encoder *encoder,
&crtc_state->dpll_hw_state);
}
static void xe3plpd_ddi_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state)
{
intel_lt_phy_pll_readout_hw_state(encoder, crtc_state, &crtc_state->dpll_hw_state.ltpll);
if (crtc_state->dpll_hw_state.ltpll.tbt_mode)
crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
else
crtc_state->port_clock =
intel_lt_phy_calc_port_clock(encoder, crtc_state);
intel_ddi_get_config(encoder, crtc_state);
}
static void mtl_ddi_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state)
{
@@ -5241,6 +5254,7 @@ void intel_ddi_init(struct intel_display *display,
encoder->enable_clock = intel_xe3plpd_pll_enable;
encoder->disable_clock = intel_xe3plpd_pll_disable;
encoder->port_pll_type = intel_mtl_port_pll_type;
encoder->get_config = xe3plpd_ddi_get_config;
} else if (DISPLAY_VER(display) >= 14) {
encoder->enable_clock = intel_mtl_pll_enable;
encoder->disable_clock = intel_mtl_pll_disable;

33
drivers/gpu/drm/i915/display/intel_lt_phy.c
View File

@@ -1886,6 +1886,39 @@ intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a,
return true;
}
void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
struct intel_lt_phy_pll_state *pll_state)
{
u8 owned_lane_mask;
u8 lane;
intel_wakeref_t wakeref;
int i, j, k;
pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder));
if (pll_state->tbt_mode)
return;
owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
lane = owned_lane_mask & INTEL_LT_PHY_LANE0 ? : INTEL_LT_PHY_LANE1;
wakeref = intel_lt_phy_transaction_begin(encoder);
pll_state->config[0] = intel_lt_phy_read(encoder, lane, LT_PHY_VDR_0_CONFIG);
pll_state->config[1] = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_1_CONFIG);
pll_state->config[2] = intel_lt_phy_read(encoder, lane, LT_PHY_VDR_2_CONFIG);
for (i = 0; i <= 12; i++) {
for (j = 3, k = 0; j >= 0; j--, k++)
pll_state->data[i][k] =
intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0,
LT_PHY_VDR_X_DATAY(i, j));
}
pll_state->clock =
intel_lt_phy_calc_port_clock(encoder, crtc_state);
intel_lt_phy_transaction_end(encoder, wakeref);
}
void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{

3
drivers/gpu/drm/i915/display/intel_lt_phy.h
View File

@@ -28,6 +28,9 @@ void intel_lt_phy_dump_hw_state(struct intel_display *display,
bool
intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a,
const struct intel_lt_phy_pll_state *b);
void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
struct intel_lt_phy_pll_state *pll_state);
void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);