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spi: rzv2h-rspi: avoid recomputing transfer frequency

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Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have a more
complicated algorithm for calculating the optimal SPI transfer frequency
compared to RZ/V2H, as the clock from which the SPI frequency is
generated supports multiple dividers.

Cache the requested transfer frequency and skip calling
rzv2h_rspi_setup_clock() if it matches the last used one to prepare for
adding support for variable clock frequency handling.

Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Link: https://patch.msgid.link/20251119161434.595677-6-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Cosmin Tanislav
2025-11-19 18:14:26 +02:00
committed by Mark Brown
parent 1b7ce968ab
commit 8878249320
1 changed files with 8 additions and 3 deletions
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11
drivers/spi/spi-rzv2h-rspi.c
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@@ -81,6 +81,7 @@ struct rzv2h_rspi_priv {
struct clk *tclk;
wait_queue_head_t wait;
unsigned int bytes_per_word;
u32 last_speed_hz;
u32 freq;
u16 status;
u8 spr;
@@ -298,9 +299,13 @@ static int rzv2h_rspi_prepare_message(struct spi_controller *ctlr,
rspi->bytes_per_word = roundup_pow_of_two(BITS_TO_BYTES(bits_per_word));
rspi->freq = rzv2h_rspi_setup_clock(rspi, speed_hz);
if (!rspi->freq)
return -EINVAL;
if (speed_hz != rspi->last_speed_hz) {
rspi->freq = rzv2h_rspi_setup_clock(rspi, speed_hz);
if (!rspi->freq)
return -EINVAL;
rspi->last_speed_hz = speed_hz;
}
writeb(rspi->spr, rspi->base + RSPI_SPBR);