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riscv: hweight: Use riscv_has_extension_likely
Use riscv_has_extension_likely() to check for RISCV_ISA_EXT_ZBB,
replacing the use of asm goto with ALTERNATIVE.
The "likely" variant is used to match the behavior of the original
implementation using ALTERNATIVE("j %l[legacy]", "nop", ...).
Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>
Link: https://patch.msgid.link/20251020-riscv-altn-helper-wip-v4-3-ef941c87669a@iscas.ac.cn
Signed-off-by: Paul Walmsley <pjw@kernel.org>
This commit is contained in:
committed by
Paul Walmsley
parent
1c7d491d86
commit
8261a9d167
@@ -19,10 +19,10 @@
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static __always_inline unsigned int __arch_hweight32(unsigned int w)
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{
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#if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB)
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asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0,
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RISCV_ISA_EXT_ZBB, 1)
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: : : : legacy);
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if (!(IS_ENABLED(CONFIG_RISCV_ISA_ZBB) &&
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IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB) &&
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riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)))
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return __sw_hweight32(w);
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asm (".option push\n"
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".option arch,+zbb\n"
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@@ -31,10 +31,6 @@ static __always_inline unsigned int __arch_hweight32(unsigned int w)
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: "=r" (w) : "r" (w) :);
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return w;
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legacy:
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#endif
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return __sw_hweight32(w);
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}
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static inline unsigned int __arch_hweight16(unsigned int w)
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@@ -50,10 +46,10 @@ static inline unsigned int __arch_hweight8(unsigned int w)
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#if BITS_PER_LONG == 64
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static __always_inline unsigned long __arch_hweight64(__u64 w)
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{
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#if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB)
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asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0,
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RISCV_ISA_EXT_ZBB, 1)
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: : : : legacy);
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if (!(IS_ENABLED(CONFIG_RISCV_ISA_ZBB) &&
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IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB) &&
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riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)))
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return __sw_hweight64(w);
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asm (".option push\n"
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".option arch,+zbb\n"
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@@ -62,10 +58,6 @@ static __always_inline unsigned long __arch_hweight64(__u64 w)
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: "=r" (w) : "r" (w) :);
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return w;
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legacy:
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#endif
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return __sw_hweight64(w);
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}
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#else /* BITS_PER_LONG == 64 */
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static inline unsigned long __arch_hweight64(__u64 w)
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