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drm/i915/cx0: Move the HDMI FRL function to intel_hdmi

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Move the is_hdmi_frl to intel_hdmi.c. Rename it appropriately and
make it non static.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-5-suraj.kandpal@intel.com
This commit is contained in:
Suraj Kandpal
2025-11-01 08:54:52 +05:30
parent 154ebdb77a
commit 809adb87da
3 changed files with 18 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
drivers/gpu/drm/i915/display/intel_cx0_phy.c
View File

@@ -2590,20 +2590,6 @@ static bool is_dp2(u32 clock)
return false; return false;
} }
static bool is_hdmi_frl(u32 clock)
{
switch (clock) {
case 300000: /* 3 Gbps */
case 600000: /* 6 Gbps */
case 800000: /* 8 Gbps */
case 1000000: /* 10 Gbps */
case 1200000: /* 12 Gbps */
return true;
default:
return false;
}
}
static bool intel_c20_protocol_switch_valid(struct intel_encoder *encoder) static bool intel_c20_protocol_switch_valid(struct intel_encoder *encoder)
{ {
struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
@@ -2617,7 +2603,7 @@ static int intel_get_c20_custom_width(u32 clock, bool dp)
{ {
if (dp && is_dp2(clock)) if (dp && is_dp2(clock))
return 2; return 2;
else if (is_hdmi_frl(clock)) else if (intel_hdmi_is_frl(clock))
return 1; return 1;
else else
return 0; return 0;
@@ -2706,11 +2692,10 @@ static void intel_c20_pll_program(struct intel_display *display,
/* 5. For DP or 6. For HDMI */ /* 5. For DP or 6. For HDMI */
serdes = 0; serdes = 0;
if (is_dp) if (is_dp)
serdes = PHY_C20_IS_DP | serdes = PHY_C20_IS_DP |
PHY_C20_DP_RATE(intel_c20_get_dp_rate(port_clock)); PHY_C20_DP_RATE(intel_c20_get_dp_rate(port_clock));
else if (is_hdmi_frl(port_clock)) else if (intel_hdmi_is_frl(port_clock))
serdes = PHY_C20_IS_HDMI_FRL; serdes = PHY_C20_IS_HDMI_FRL;
intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE, intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
@@ -2777,7 +2762,7 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
val |= XELPDP_FORWARD_CLOCK_UNGATE; val |= XELPDP_FORWARD_CLOCK_UNGATE;
if (!is_dp && is_hdmi_frl(port_clock)) if (!is_dp && intel_hdmi_is_frl(port_clock))
val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_DIV18CLK); val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
else else
val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK); val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK);

14
drivers/gpu/drm/i915/display/intel_hdmi.c
View File

@@ -68,6 +68,20 @@
#include "intel_snps_phy.h" #include "intel_snps_phy.h"
#include "intel_vrr.h" #include "intel_vrr.h"
bool intel_hdmi_is_frl(u32 clock)
{
switch (clock) {
case 300000: /* 3 Gbps */
case 600000: /* 6 Gbps */
case 800000: /* 8 Gbps */
case 1000000: /* 10 Gbps */
case 1200000: /* 12 Gbps */
return true;
default:
return false;
}
}
static void static void
assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
{ {

1
drivers/gpu/drm/i915/display/intel_hdmi.h
View File

@@ -60,6 +60,7 @@ int intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,
int src_max_slices, int src_max_slice_width, int src_max_slices, int src_max_slice_width,
int hdmi_max_slices, int hdmi_throughput); int hdmi_max_slices, int hdmi_throughput);
int intel_hdmi_dsc_get_slice_height(int vactive); int intel_hdmi_dsc_get_slice_height(int vactive);
bool intel_hdmi_is_frl(u32 clock);
void hsw_write_infoframe(struct intel_encoder *encoder, void hsw_write_infoframe(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state, const struct intel_crtc_state *crtc_state,