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drm/amd/display: Support possibly NULL link for should_use_dmub_lock

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[Why]
It's possible to have a stream enabled without a link or link encoder.

There are cases where we'd still like to interlock the driver
programming from firmware programming to ensure that we don't put the
hardware in an undefined (or error) state if two programming sequences
are simultaneously executed on the same hardware blocks.

[How]
Add an explicit DC parameter to should_use_dmub_lock().

Make pointers to should_use_dmub_lock() const since it's a checker
function that shouldn't modify state.

Update the callsites to pass in DC explicitly.

Check that the link is non-NULL before deferencing and performing link
based checks.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Nicholas Kazlauskas
2025-09-16 13:57:17 -04:00
committed by Alex Deucher
parent eeab74ee69
commit 7f74931c9c
6 changed files with 25 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/amd/display/dc/core/dc.c
View File

@@ -4149,7 +4149,7 @@ static void commit_planes_for_stream(struct dc *dc,
if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
if (top_pipe_to_program &&
top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
if (should_use_dmub_lock(stream->link)) {
if (should_use_dmub_lock(dc, stream->link)) {
union dmub_hw_lock_flags hw_locks = { 0 };
struct dmub_hw_lock_inst_flags inst_flags = { 0 };
@@ -4419,7 +4419,7 @@ static void commit_planes_for_stream(struct dc *dc,
top_pipe_to_program->stream_res.tg,
CRTC_STATE_VACTIVE);
if (should_use_dmub_lock(stream->link)) {
if (should_use_dmub_lock(dc, stream->link)) {
union dmub_hw_lock_flags hw_locks = { 0 };
struct dmub_hw_lock_inst_flags inst_flags = { 0 };

33
drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
View File

@@ -61,27 +61,30 @@ void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv,
dc_dmub_srv_wait_for_inbox0_ack(dmub_srv);
}
bool should_use_dmub_lock(struct dc_link *link)
bool should_use_dmub_lock(const struct dc *dc, const struct dc_link *link)
{
/* ASIC doesn't support DMUB */
if (!link->ctx->dmub_srv)
if (!dc->ctx->dmub_srv)
return false;
if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)
return true;
if (link) {
if (link->replay_settings.replay_feature_enabled)
return true;
/* only use HW lock for PSR1 on single eDP */
if (link->psr_settings.psr_version == DC_PSR_VERSION_1) {
struct dc_link *edp_links[MAX_NUM_EDP];
int edp_num;
dc_get_edp_links(link->dc, edp_links, &edp_num);
if (edp_num == 1)
if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)
return true;
if (link->replay_settings.replay_feature_enabled)
return true;
/* only use HW lock for PSR1 on single eDP */
if (link->psr_settings.psr_version == DC_PSR_VERSION_1) {
struct dc_link *edp_links[MAX_NUM_EDP];
int edp_num;
dc_get_edp_links(dc, edp_links, &edp_num);
if (edp_num == 1)
return true;
}
}
return false;

2
drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h
View File

@@ -37,6 +37,6 @@ void dmub_hw_lock_mgr_cmd(struct dc_dmub_srv *dmub_srv,
void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv,
union dmub_inbox0_cmd_lock_hw hw_lock_cmd);
bool should_use_dmub_lock(struct dc_link *link);
bool should_use_dmub_lock(const struct dc *dc, const struct dc_link *link);
#endif /*_DMUB_HW_LOCK_MGR_H_ */

2
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
View File

@@ -2245,7 +2245,7 @@ void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock)
if (lock)
delay_cursor_until_vupdate(dc, pipe);
if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) {
if (pipe->stream && should_use_dmub_lock(dc, pipe->stream->link)) {
union dmub_hw_lock_flags hw_locks = { 0 };
struct dmub_hw_lock_inst_flags inst_flags = { 0 };

2
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
View File

@@ -1449,7 +1449,7 @@ void dcn20_pipe_control_lock(
!flip_immediate)
dcn20_setup_gsl_group_as_lock(dc, pipe, false);
if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) {
if (pipe->stream && should_use_dmub_lock(dc, pipe->stream->link)) {
union dmub_hw_lock_flags hw_locks = { 0 };
struct dmub_hw_lock_inst_flags inst_flags = { 0 };

4
drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
View File

@@ -876,7 +876,7 @@ bool dp_set_test_pattern(
return false;
if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) {
if (should_use_dmub_lock(pipe_ctx->stream->link)) {
if (should_use_dmub_lock(pipe_ctx->stream->link->dc, pipe_ctx->stream->link)) {
union dmub_hw_lock_flags hw_locks = { 0 };
struct dmub_hw_lock_inst_flags inst_flags = { 0 };
@@ -924,7 +924,7 @@ bool dp_set_test_pattern(
CRTC_STATE_VACTIVE);
if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) {
if (should_use_dmub_lock(pipe_ctx->stream->link)) {
if (should_use_dmub_lock(pipe_ctx->stream->link->dc, pipe_ctx->stream->link)) {
union dmub_hw_lock_flags hw_locks = { 0 };
struct dmub_hw_lock_inst_flags inst_flags = { 0 };