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Merge tag 'thead-dt-for-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux into soc/dt

Browse Source 
T-HEAD Devicetrees for v6.19

Add PWM controlled fan and it's associated thermal management for the
Lichee Pi 4A board.

Enable additional ISA extenstions supported by the T-Head C910 cores:
Zfh, Ziccrse, XTheadvector.

Add reset controllers of more TH1520 subsystems: AP, AO, DSP, MISC, VI.

Signed-off-by: Drew Fustini <fustini@kernel.org>

* tag 'thead-dt-for-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux:
  riscv: dts: thead: Add reset controllers of more subsystems for TH1520
  riscv: dts: thead: Add PWM fan and thermal control
  riscv: dts: thead: Add PWM controller node
  riscv: dts: thead: add zfh for th1520
  riscv: dts: thead: add ziccrse for th1520
  riscv: dts: thead: add xtheadvector to the th1520 devicetree

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2025-11-21 16:35:57 +01:00
parent 156c42c7fc d8a174babf
commit 7e90eede6b
2 changed files with 131 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

67
arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
View File

@@ -28,9 +28,76 @@
chosen {
stdout-path = "serial0:115200n8";
};
thermal-zones {
cpu-thermal {
polling-delay = <1000>;
polling-delay-passive = <1000>;
thermal-sensors = <&pvt 0>;
trips {
fan_config0: fan-trip0 {
temperature = <39000>;
hysteresis = <5000>;
type = "active";
};
fan_config1: fan-trip1 {
temperature = <50000>;
hysteresis = <5000>;
type = "active";
};
fan_config2: fan-trip2 {
temperature = <60000>;
hysteresis = <5000>;
type = "active";
};
};
cooling-maps {
map-active-0 {
cooling-device = <&fan 1 1>;
trip = <&fan_config0>;
};
map-active-1 {
cooling-device = <&fan 2 2>;
trip = <&fan_config1>;
};
map-active-2 {
cooling-device = <&fan 3 3>;
trip = <&fan_config2>;
};
};
};
};
fan: pwm-fan {
pinctrl-names = "default";
pinctrl-0 = <&fan_pins>;
compatible = "pwm-fan";
#cooling-cells = <2>;
pwms = <&pwm 1 10000000 0>;
cooling-levels = <0 66 196 255>;
};
};
&padctrl0_apsys {
fan_pins: fan-0 {
pwm1-pins {
pins = "GPIO3_3"; /* PWM1 */
function = "pwm";
bias-disable;
drive-strength = <25>;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
};
uart0_pins: uart0-0 {
tx-pins {
pins = "UART0_TXD";

72
arch/riscv/boot/dts/thead/th1520.dtsi
View File

@@ -24,8 +24,11 @@
device_type = "cpu";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <0>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -48,8 +51,11 @@
device_type = "cpu";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <1>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -72,8 +78,11 @@
device_type = "cpu";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <2>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -96,8 +105,11 @@
device_type = "cpu";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
"zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <3>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -277,6 +289,12 @@
<&cpu3_intc 3>, <&cpu3_intc 7>;
};
rst_vi: reset-controller@ffe4040100 {
compatible = "thead,th1520-reset-vi";
reg = <0xff 0xe4040100 0x0 0x8>;
#reset-cells = <1>;
};
spi0: spi@ffe700c000 {
compatible = "thead,th1520-spi", "snps,dw-apb-ssi";
reg = <0xff 0xe700c000 0x0 0x1000>;
@@ -502,6 +520,25 @@
status = "disabled";
};
pwm: pwm@ffec01c000 {
compatible = "thead,th1520-pwm";
reg = <0xff 0xec01c000 0x0 0x4000>;
clocks = <&clk CLK_PWM>;
#pwm-cells = <3>;
};
rst_misc: reset-controller@ffec02c000 {
compatible = "thead,th1520-reset-misc";
reg = <0xff 0xec02c000 0x0 0x18>;
#reset-cells = <1>;
};
rst_vp: reset-controller@ffecc30000 {
compatible = "thead,th1520-reset-vp";
reg = <0xff 0xecc30000 0x0 0x14>;
#reset-cells = <1>;
};
clk: clock-controller@ffef010000 {
compatible = "thead,th1520-clk-ap";
reg = <0xff 0xef010000 0x0 0x1000>;
@@ -509,6 +546,18 @@
#clock-cells = <1>;
};
rst_ap: reset-controller@ffef014000 {
compatible = "thead,th1520-reset-ap";
reg = <0xff 0xef014000 0x0 0x1000>;
#reset-cells = <1>;
};
rst_dsp: reset-controller@ffef040028 {
compatible = "thead,th1520-reset-dsp";
reg = <0xff 0xef040028 0x0 0x4>;
#reset-cells = <1>;
};
gpu: gpu@ffef400000 {
compatible = "thead,th1520-gpu", "img,img-bxm-4-64",
"img,img-rogue";
@@ -681,6 +730,13 @@
};
};
rst_ao: reset-controller@fffff44000 {
compatible = "thead,th1520-reset-ao";
reg = <0xff 0xfff44000 0x0 0x2000>;
#reset-cells = <1>;
status = "reserved";
};
padctrl_aosys: pinctrl@fffff4a000 {
compatible = "thead,th1520-pinctrl";
reg = <0xff 0xfff4a000 0x0 0x2000>;