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drm/i915: do cck get/put inside vlv_get_cck_clock()

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Move towards VLV/CHV clock interfaces that handle sideband get/put
inside them instead of at the caller.

With this, we can switch to the simpler vlv_punit_get()/vlv_punit_put()
in vlv_get_cdclk().

We'll need to move vlv_init_gpll_ref_freq() outside of the existing
get/put in vlv_rps_init() and chv_rps_init().

Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://lore.kernel.org/r/480b654b6c736a03343dfd17eb130c39fd82c637.1757688216.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula
2025-09-12 17:48:41 +03:00
parent c8cf6e3cc2
commit 7d11281178
3 changed files with 9 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/drm/i915/display/intel_cdclk.c
View File

@@ -609,17 +609,13 @@ static void vlv_get_cdclk(struct intel_display *display,
u32 val;
cdclk_config->vco = vlv_get_hpll_vco(display->drm);
vlv_iosf_sb_get(display->drm, BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
cdclk_config->cdclk = vlv_get_cck_clock(display->drm, "cdclk",
CCK_DISPLAY_CLOCK_CONTROL,
cdclk_config->vco);
vlv_punit_get(display->drm);
val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);
vlv_iosf_sb_put(display->drm,
BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
vlv_punit_put(display->drm);
if (display->platform.valleyview)
cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >>

7
drivers/gpu/drm/i915/display/intel_display.c
View File

@@ -163,7 +163,10 @@ int vlv_get_cck_clock(struct drm_device *drm,
u32 val;
int divider;
vlv_cck_get(drm);
val = vlv_cck_read(drm, reg);
vlv_cck_put(drm);
divider = val & CCK_FREQUENCY_VALUES;
drm_WARN(drm, (val & CCK_FREQUENCY_STATUS) !=
@@ -182,12 +185,8 @@ int vlv_get_cck_clock_hpll(struct drm_device *drm,
if (dev_priv->hpll_freq == 0)
dev_priv->hpll_freq = vlv_get_hpll_vco(drm);
vlv_cck_get(drm);
hpll = vlv_get_cck_clock(drm, name, reg, dev_priv->hpll_freq);
vlv_cck_put(drm);
return hpll;
}

8
drivers/gpu/drm/i915/gt/intel_rps.c
View File

@@ -1703,13 +1703,13 @@ static void vlv_rps_init(struct intel_rps *rps)
{
struct drm_i915_private *i915 = rps_to_i915(rps);
vlv_init_gpll_ref_freq(rps);
vlv_iosf_sb_get(&i915->drm,
BIT(VLV_IOSF_SB_PUNIT) |
BIT(VLV_IOSF_SB_NC) |
BIT(VLV_IOSF_SB_CCK));
vlv_init_gpll_ref_freq(rps);
rps->max_freq = vlv_rps_max_freq(rps);
rps->rp0_freq = rps->max_freq;
drm_dbg(&i915->drm, "max GPU freq: %d MHz (%u)\n",
@@ -1737,13 +1737,13 @@ static void chv_rps_init(struct intel_rps *rps)
{
struct drm_i915_private *i915 = rps_to_i915(rps);
vlv_init_gpll_ref_freq(rps);
vlv_iosf_sb_get(&i915->drm,
BIT(VLV_IOSF_SB_PUNIT) |
BIT(VLV_IOSF_SB_NC) |
BIT(VLV_IOSF_SB_CCK));
vlv_init_gpll_ref_freq(rps);
rps->max_freq = chv_rps_max_freq(rps);
rps->rp0_freq = rps->max_freq;
drm_dbg(&i915->drm, "max GPU freq: %d MHz (%u)\n",