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Merge branch 'disable-clkout-on-rtl8211f-d-i-vd-cg'

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Vladimir Oltean says:

====================
Disable CLKOUT on RTL8211F(D)(I)-VD-CG

The Realtek RTL8211F(D)(I)-VD-CG is similar to other RTL8211F models in
that the CLKOUT signal can be turned off - a feature requested to reduce
EMI, and implemented via "realtek,clkout-disable" as documented in
Documentation/devicetree/bindings/net/realtek,rtl82xx.yaml.

It is also dissimilar to said PHY models because it has no PHYCR2
register, and disabling CLKOUT is done through some other register.

The strategy adopted in this 6-patch series is to make the PHY driver
not think in terms of "priv->has_phycr2" and "priv->phycr2", but of more
high-level features ("priv->disable_clk_out") while maintaining behaviour.
Then, the logic is extended for the new PHY.

Very loosely based on previous work from Clark Wang, who took a
different approach, to pretend that the RTL8211FVD_CLKOUT_REG is
actually this PHY's PHYCR2.
====================

Link: https://patch.msgid.link/20251117234033.345679-1-vladimir.oltean@nxp.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski
2025-11-19 20:24:25 -08:00
parent 672cb5c2a9 4465ae435d
commit 7c9dd38602
1 changed files with 103 additions and 58 deletions
Download Patch File Download Diff File Expand all files Collapse all files

161
drivers/net/phy/realtek/realtek_main.c
View File

@@ -90,6 +90,14 @@
#define RTL8211F_LEDCR_MASK GENMASK(4, 0)
#define RTL8211F_LEDCR_SHIFT 5
/* RTL8211F(D)(I)-VD-CG CLKOUT configuration is specified via magic values
* to undocumented register pages. The names here do not reflect the datasheet.
* Unlike other PHY models, CLKOUT configuration does not go through PHYCR2.
*/
#define RTL8211FVD_CLKOUT_PAGE 0xd05
#define RTL8211FVD_CLKOUT_REG 0x11
#define RTL8211FVD_CLKOUT_EN BIT(8)
/* RTL8211F RGMII configuration */
#define RTL8211F_RGMII_PAGE 0xd08
@@ -193,9 +201,8 @@ MODULE_AUTHOR("Johnson Leung");
MODULE_LICENSE("GPL");
struct rtl821x_priv {
u16 phycr1;
u16 phycr2;
bool has_phycr2;
bool enable_aldps;
bool disable_clk_out;
struct clk *clk;
/* rtl8211f */
u16 iner;
@@ -245,8 +252,6 @@ static int rtl821x_probe(struct phy_device *phydev)
{
struct device *dev = &phydev->mdio.dev;
struct rtl821x_priv *priv;
u32 phy_id = phydev->drv->phy_id;
int ret;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
@@ -257,24 +262,10 @@ static int rtl821x_probe(struct phy_device *phydev)
return dev_err_probe(dev, PTR_ERR(priv->clk),
"failed to get phy clock\n");
ret = phy_read_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR1);
if (ret < 0)
return ret;
priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF);
if (of_property_read_bool(dev->of_node, "realtek,aldps-enable"))
priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF;
priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID);
if (priv->has_phycr2) {
ret = phy_read_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR2);
if (ret < 0)
return ret;
priv->phycr2 = ret & RTL8211F_CLKOUT_EN;
if (of_property_read_bool(dev->of_node, "realtek,clkout-disable"))
priv->phycr2 &= ~RTL8211F_CLKOUT_EN;
}
priv->enable_aldps = of_property_read_bool(dev->of_node,
"realtek,aldps-enable");
priv->disable_clk_out = of_property_read_bool(dev->of_node,
"realtek,clkout-disable");
phydev->priv = priv;
@@ -587,22 +578,11 @@ static int rtl8211c_config_init(struct phy_device *phydev)
CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
}
static int rtl8211f_config_init(struct phy_device *phydev)
static int rtl8211f_config_rgmii_delay(struct phy_device *phydev)
{
struct rtl821x_priv *priv = phydev->priv;
struct device *dev = &phydev->mdio.dev;
u16 val_txdly, val_rxdly;
int ret;
ret = phy_modify_paged_changed(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR1,
RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF,
priv->phycr1);
if (ret < 0) {
dev_err(dev, "aldps mode configuration failed: %pe\n",
ERR_PTR(ret));
return ret;
}
switch (phydev->interface) {
case PHY_INTERFACE_MODE_RGMII:
val_txdly = 0;
@@ -632,53 +612,118 @@ static int rtl8211f_config_init(struct phy_device *phydev)
RTL8211F_TXCR, RTL8211F_TX_DELAY,
val_txdly);
if (ret < 0) {
dev_err(dev, "Failed to update the TX delay register\n");
phydev_err(phydev, "Failed to update the TX delay register: %pe\n",
ERR_PTR(ret));
return ret;
} else if (ret) {
dev_dbg(dev,
"%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n",
str_enable_disable(val_txdly));
phydev_dbg(phydev,
"%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n",
str_enable_disable(val_txdly));
} else {
dev_dbg(dev,
"2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n",
str_enabled_disabled(val_txdly));
phydev_dbg(phydev,
"2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n",
str_enabled_disabled(val_txdly));
}
ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE,
RTL8211F_RXCR, RTL8211F_RX_DELAY,
val_rxdly);
if (ret < 0) {
dev_err(dev, "Failed to update the RX delay register\n");
phydev_err(phydev, "Failed to update the RX delay register: %pe\n",
ERR_PTR(ret));
return ret;
} else if (ret) {
dev_dbg(dev,
"%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n",
str_enable_disable(val_rxdly));
phydev_dbg(phydev,
"%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n",
str_enable_disable(val_rxdly));
} else {
dev_dbg(dev,
"2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n",
str_enabled_disabled(val_rxdly));
phydev_dbg(phydev,
"2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n",
str_enabled_disabled(val_rxdly));
}
if (!priv->has_phycr2)
return 0;
}
static int rtl8211f_config_clk_out(struct phy_device *phydev)
{
struct rtl821x_priv *priv = phydev->priv;
int ret;
/* The value is preserved if the device tree property is absent */
if (!priv->disable_clk_out)
return 0;
/* Disable PHY-mode EEE so LPI is passed to the MAC */
ret = phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR2,
RTL8211F_PHYCR2_PHY_EEE_ENABLE, 0);
if (phydev->drv->phy_id == RTL_8211FVD_PHYID)
ret = phy_modify_paged(phydev, RTL8211FVD_CLKOUT_PAGE,
RTL8211FVD_CLKOUT_REG,
RTL8211FVD_CLKOUT_EN, 0);
else
ret = phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE,
RTL8211F_PHYCR2, RTL8211F_CLKOUT_EN, 0);
if (ret)
return ret;
ret = phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE,
RTL8211F_PHYCR2, RTL8211F_CLKOUT_EN,
priv->phycr2);
if (ret < 0) {
return genphy_soft_reset(phydev);
}
/* Advance Link Down Power Saving (ALDPS) mode changes crystal/clock behaviour,
* which causes the RXC clock signal to stop for tens to hundreds of
* milliseconds.
*
* Some MACs need the RXC clock to support their internal RX logic, so ALDPS is
* only enabled based on an opt-in device tree property.
*/
static int rtl8211f_config_aldps(struct phy_device *phydev)
{
struct rtl821x_priv *priv = phydev->priv;
u16 mask = RTL8211F_ALDPS_PLL_OFF |
RTL8211F_ALDPS_ENABLE |
RTL8211F_ALDPS_XTAL_OFF;
/* The value is preserved if the device tree property is absent */
if (!priv->enable_aldps)
return 0;
return phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR1,
mask, mask);
}
static int rtl8211f_config_phy_eee(struct phy_device *phydev)
{
/* RTL8211FVD has no PHYCR2 register */
if (phydev->drv->phy_id == RTL_8211FVD_PHYID)
return 0;
/* Disable PHY-mode EEE so LPI is passed to the MAC */
return phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR2,
RTL8211F_PHYCR2_PHY_EEE_ENABLE, 0);
}
static int rtl8211f_config_init(struct phy_device *phydev)
{
struct device *dev = &phydev->mdio.dev;
int ret;
ret = rtl8211f_config_aldps(phydev);
if (ret) {
dev_err(dev, "aldps mode configuration failed: %pe\n",
ERR_PTR(ret));
return ret;
}
ret = rtl8211f_config_rgmii_delay(phydev);
if (ret)
return ret;
ret = rtl8211f_config_clk_out(phydev);
if (ret) {
dev_err(dev, "clkout configuration failed: %pe\n",
ERR_PTR(ret));
return ret;
}
return genphy_soft_reset(phydev);
return rtl8211f_config_phy_eee(phydev);
}
static int rtl821x_suspend(struct phy_device *phydev)