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arm64: dts: qcom: sm6350: Add GPUCC node
Add and configure a node for the GPU clock controller. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230315-topic-lagoon_gpu-v2-3-afcdfb18bb13@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Bjorn Andersson
parent
3091e5820a
commit
75a511b1e5
@@ -5,6 +5,7 @@
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*/
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#include <dt-bindings/clock/qcom,gcc-sm6350.h>
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#include <dt-bindings/clock/qcom,gpucc-sm6350.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,sm6350-camcc.h>
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#include <dt-bindings/dma/qcom-gpi.h>
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@@ -1308,6 +1309,20 @@
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};
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};
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gpucc: clock-controller@3d90000 {
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compatible = "qcom,sm6350-gpucc";
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reg = <0 0x03d90000 0 0x9000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_GPU_GPLL0_CLK>,
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<&gcc GCC_GPU_GPLL0_DIV_CLK>;
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clock-names = "bi_tcxo",
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"gcc_gpu_gpll0_clk_src",
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"gcc_gpu_gpll0_div_clk_src";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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mpss: remoteproc@4080000 {
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compatible = "qcom,sm6350-mpss-pas";
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reg = <0x0 0x04080000 0x0 0x4040>;
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