admin/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2025-12-07 20:06:24 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge tag 'mips_6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Browse Source 
Pull MIPS updates from Thomas Bogendoerfer:

 - switch longson32 platform to DT and use MIPS_GENERIC framework

 - cleanups/fixes for lantiq DTs

 - other cleanups and fixes

* tag 'mips_6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (30 commits)
  mips: math-emu: replace deprecated strcpy() in me-debugfs
  MIPS: configs: Consolidate Loongson1 defconfigs
  MIPS: Unify Loongson1 PRID_REV
  MIPS: loongson32: Switch to generic core
  MIPS: loongson: Add built-in DTB support
  MIPS: dts: loongson: Add CQ-T300B board
  MIPS: dts: loongson: Add Smartloong-1C board
  MIPS: dts: loongson: Add LSGZ_1B_DEV board
  MIPS: dts: loongson: Add LS1B-DEMO board
  dt-bindings: mips: loongson: Add LS1B-DEMO and CQ-T300B
  mips: lantiq: danube: rename stp node on EASY50712 reference board
  mips: lantiq: xway: sysctrl: rename stp clock
  MIPS: RB532: Replace deprecated strcpy() with memcpy() and strscpy()
  MIPS: Loongson64: Replace deprecated strcpy() with strscpy_pad()
  MIPS: generic: Replace deprecated strcpy() in ocelot_detect()
  MIPS: octeon: Replace deprecated strcpy() in octeon_model_get_string_buffer()
  MIPS: octeon: Replace memset(0) + deprecated strcpy() with strscpy_pad()
  MIPS: arc: Replace deprecated strcpy() with memcpy()
  MIPS: txx9: Replace deprecated strcpy() with strscpy()
  MIPS: sni: Replace deprecated strcpy() in sni_console_setup()
  ...
This commit is contained in:
Linus Torvalds
2025-10-05 10:09:55 -07:00
parent 742adaa16d c662a6fef1
commit 6a74422b97
108 changed files with 1356 additions and 1406 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/mips/cpus.yaml
View File

@@ -33,6 +33,7 @@ properties:
- mips,mips1004Kc
- mips,mips24KEc
- mips,mips24Kc
- mips,mips34Kc
- mips,mips4KEc
- mips,mips4Kc
- mips,mips74Kc

2
Documentation/devicetree/bindings/mips/loongson/devices.yaml
View File

@@ -40,6 +40,7 @@ properties:
- description: LS1B based boards
items:
- enum:
- loongson,ls1b-demo
- loongson,lsgz-1b-dev
- const: loongson,ls1b
@@ -47,6 +48,7 @@ properties:
items:
- enum:
- loongmasses,smartloong-1c
- loongson,cq-t300b
- const: loongson,ls1c
additionalProperties: true

3
MAINTAINERS
View File

@@ -17267,7 +17267,8 @@ M: Keguang Zhang <keguang.zhang@gmail.com>
L: linux-mips@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/*/loongson,ls1*.yaml
F: arch/mips/include/asm/mach-loongson32/
F: arch/mips/boot/dts/loongson/loongson1*
F: arch/mips/configs/loongson1_defconfig
F: arch/mips/loongson32/
F: drivers/*/*loongson1*
F: drivers/mtd/nand/raw/loongson-nand-controller.c

64
arch/mips/Kconfig
View File

@@ -479,6 +479,23 @@ config LANTIQ
config MACH_LOONGSON32
bool "Loongson 32-bit family of machines"
select MACH_GENERIC_CORE
select USE_OF
select BUILTIN_DTB
select BOOT_ELF32
select CEVT_R4K
select CSRC_R4K
select COMMON_CLK
select DMA_NONCOHERENT
select GENERIC_IRQ_SHOW_LEVEL
select IRQ_MIPS_CPU
select LS1X_IRQ
select SYS_HAS_CPU_LOONGSON32
select SYS_HAS_EARLY_PRINTK
select USE_GENERIC_EARLY_PRINTK_8250
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_ZBOOT
help
This enables support for the Loongson-1 family of machines.
@@ -1385,25 +1402,20 @@ config CPU_LOONGSON2F
have a similar programming interface with FPGA northbridge used in
Loongson2E.
config CPU_LOONGSON1B
bool "Loongson 1B"
depends on SYS_HAS_CPU_LOONGSON1B
select CPU_LOONGSON32
config CPU_LOONGSON32
bool "Loongson 32-bit CPU"
depends on SYS_HAS_CPU_LOONGSON32
select CPU_MIPS32
select CPU_MIPSR2
select CPU_HAS_PREFETCH
select CPU_HAS_LOAD_STORE_LR
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
select CPU_SUPPORTS_CPUFREQ
select LEDS_GPIO_REGISTER
help
The Loongson 1B is a 32-bit SoC, which implements the MIPS32
Release 1 instruction set and part of the MIPS32 Release 2
instruction set.
config CPU_LOONGSON1C
bool "Loongson 1C"
depends on SYS_HAS_CPU_LOONGSON1C
select CPU_LOONGSON32
select LEDS_GPIO_REGISTER
help
The Loongson 1C is a 32-bit SoC, which implements the MIPS32
Release 1 instruction set and part of the MIPS32 Release 2
instruction set.
The Loongson GS232 microarchitecture implements the MIPS32 Release 1
instruction set and part of the MIPS32 Release 2 instruction set.
config CPU_MIPS32_R1
bool "MIPS32 Release 1"
@@ -1838,15 +1850,6 @@ config CPU_LOONGSON2EF
select CPU_SUPPORTS_HUGEPAGES
select RTC_MC146818_LIB
config CPU_LOONGSON32
bool
select CPU_MIPS32
select CPU_MIPSR2
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
select CPU_SUPPORTS_CPUFREQ
config CPU_BMIPS32_3300
select SMP_UP if SMP
bool
@@ -1884,10 +1887,7 @@ config SYS_HAS_CPU_LOONGSON2F
select CPU_SUPPORTS_CPUFREQ
select CPU_SUPPORTS_ADDRWINCFG if 64BIT
config SYS_HAS_CPU_LOONGSON1B
bool
config SYS_HAS_CPU_LOONGSON1C
config SYS_HAS_CPU_LOONGSON32
bool
config SYS_HAS_CPU_MIPS32_R1
@@ -2986,8 +2986,8 @@ choice
prompt "Kernel command line type"
depends on !CMDLINE_OVERRIDE
default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
!MACH_LOONGSON64 && !MIPS_MALTA && \
!CAVIUM_OCTEON_SOC
!MACH_LOONGSON64 && !MACH_LOONGSON32 && \
!MIPS_MALTA && !CAVIUM_OCTEON_SOC
default MIPS_CMDLINE_FROM_BOOTLOADER
config MIPS_CMDLINE_FROM_DTB

20
arch/mips/alchemy/common/clock.c
View File

@@ -211,30 +211,34 @@ static int alchemy_clk_aux_setr(struct clk_hw *hw,
return 0;
}
static long alchemy_clk_aux_roundr(struct clk_hw *hw,
unsigned long rate,
unsigned long *parent_rate)
static int alchemy_clk_aux_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct alchemy_auxpll_clk *a = to_auxpll_clk(hw);
unsigned long mult;
if (!rate || !*parent_rate)
return 0;
if (!req->rate || !req->best_parent_rate) {
req->rate = 0;
mult = rate / (*parent_rate);
return 0;
}
mult = req->rate / req->best_parent_rate;
if (mult && (mult < 7))
mult = 7;
if (mult > a->maxmult)
mult = a->maxmult;
return (*parent_rate) * mult;
req->rate = req->best_parent_rate * mult;
return 0;
}
static const struct clk_ops alchemy_clkops_aux = {
.recalc_rate = alchemy_clk_aux_recalc,
.set_rate = alchemy_clk_aux_setr,
.round_rate = alchemy_clk_aux_roundr,
.determine_rate = alchemy_clk_aux_determine_rate,
};
static struct clk __init *alchemy_clk_setup_aux(const char *parent_name,

1
arch/mips/boot/dts/Makefile
View File

@@ -8,6 +8,7 @@ subdir-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += img
subdir-$(CONFIG_MACH_INGENIC) += ingenic
subdir-$(CONFIG_LANTIQ) += lantiq
subdir-$(CONFIG_MACH_LOONGSON64) += loongson
subdir-$(CONFIG_MACH_LOONGSON32) += loongson
subdir-$(CONFIG_SOC_VCOREIII) += mscc
subdir-$(CONFIG_MIPS_MALTA) += mti
subdir-$(CONFIG_LEGACY_BOARD_SEAD3) += mti

3
arch/mips/boot/dts/brcm/bcm7346.dtsi
View File

@@ -531,7 +531,8 @@
};
memc-ddr@2000 {
compatible = "brcm,brcmstb-memc-ddr";
compatible = "brcm,brcmstb-memc-ddr-rev-a.0.0",
"brcm,brcmstb-memc-ddr";
reg = <0x2000 0x300>;
};

3
arch/mips/boot/dts/brcm/bcm7360.dtsi
View File

@@ -450,7 +450,8 @@
};
memc-ddr@2000 {
compatible = "brcm,brcmstb-memc-ddr";
compatible = "brcm,brcmstb-memc-ddr-rev-a.0.0",
"brcm,brcmstb-memc-ddr";
reg = <0x2000 0x300>;
};

3
arch/mips/boot/dts/brcm/bcm7362.dtsi
View File

@@ -446,7 +446,8 @@
};
memc-ddr@2000 {
compatible = "brcm,brcmstb-memc-ddr";
compatible = "brcm,brcmstb-memc-ddr-rev-a.0.0",
"brcm,brcmstb-memc-ddr";
reg = <0x2000 0x300>;
};

6
arch/mips/boot/dts/brcm/bcm7425.dtsi
View File

@@ -542,7 +542,8 @@
};
memc-ddr@2000 {
compatible = "brcm,brcmstb-memc-ddr";
compatible = "brcm,brcmstb-memc-ddr-rev-a.0.0",
"brcm,brcmstb-memc-ddr";
reg = <0x2000 0x300>;
};
@@ -569,7 +570,8 @@
};
memc-ddr@2000 {
compatible = "brcm,brcmstb-memc-ddr";
compatible = "brcm,brcmstb-memc-ddr-rev-a.0.0",
"brcm,brcmstb-memc-ddr";
reg = <0x2000 0x300>;
};

6
arch/mips/boot/dts/brcm/bcm7435.dtsi
View File

@@ -558,7 +558,8 @@
};
memc-ddr@2000 {
compatible = "brcm,brcmstb-memc-ddr";
compatible = "brcm,brcmstb-memc-ddr-rev-a.0.0",
"brcm,brcmstb-memc-ddr";
reg = <0x2000 0x300>;
};
@@ -585,7 +586,8 @@
};
memc-ddr@2000 {
compatible = "brcm,brcmstb-memc-ddr";
compatible = "brcm,brcmstb-memc-ddr-rev-a.0.0",
"brcm,brcmstb-memc-ddr";
reg = <0x2000 0x300>;
};

6
arch/mips/boot/dts/lantiq/danube.dtsi
View File

@@ -5,8 +5,12 @@
compatible = "lantiq,xway", "lantiq,danube";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "mips,mips24Kc";
reg = <0>;
};
};
@@ -100,6 +104,8 @@
0x1000000 0 0x00000000 0xae00000 0 0x200000>; /* io space */
reg = <0x7000000 0x8000 /* config space */
0xe105400 0x400>; /* pci bridge */
device_type = "pci";
};
};
};

4
arch/mips/boot/dts/lantiq/danube_easy50712.dts
View File

@@ -4,6 +4,8 @@
/include/ "danube.dtsi"
/ {
model = "Intel EASY50712";
chosen {
bootargs = "console=ttyLTQ0,115200 init=/etc/preinit";
};
@@ -94,7 +96,7 @@
lantiq,tx-burst-length = <4>;
};
stp0: stp@e100bb0 {
stp0: gpio@e100bb0 {
#gpio-cells = <2>;
compatible = "lantiq,gpio-stp-xway";
gpio-controller;

10
arch/mips/boot/dts/loongson/Makefile
View File

@@ -1,7 +1,17 @@
# SPDX-License-Identifier: GPL-2.0
ifneq ($(CONFIG_BUILTIN_DTB_NAME),)
dtb-y := $(addsuffix .dtb, $(CONFIG_BUILTIN_DTB_NAME))
else
dtb-$(CONFIG_MACH_LOONGSON64) += loongson64_2core_2k1000.dtb
dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_4core_ls7a.dtb
dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_4core_rs780e.dtb
dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_8core_rs780e.dtb
dtb-$(CONFIG_MACH_LOONGSON64) += loongson64g_4core_ls7a.dtb
dtb-$(CONFIG_MACH_LOONGSON64) += loongson64v_4core_virtio.dtb
dtb-$(CONFIG_MACH_LOONGSON32) += cq-t300b.dtb
dtb-$(CONFIG_MACH_LOONGSON32) += ls1b-demo.dtb
dtb-$(CONFIG_MACH_LOONGSON32) += lsgz_1b_dev.dtb
dtb-$(CONFIG_MACH_LOONGSON32) += smartloong-1c.dtb
endif

110
arch/mips/boot/dts/loongson/cq-t300b.dts Normal file
View File

@@ -0,0 +1,110 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2023-2025 Keguang Zhang <keguang.zhang@gmail.com>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "loongson1c.dtsi"
/ {
compatible = "loongson,cq-t300b", "loongson,ls1c";
model = "CQ-T300B Board";
memory@0 {
device_type = "memory";
reg = <0x0 0x8000000>;
};
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
serial0 = &uart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
led0 {
label = "led0";
gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
led1 {
label = "led1";
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
linux,default-trigger = "nand-disk";
};
};
};
&xtal {
clock-frequency = <24000000>;
};
&emac {
phy-handle = <&phy0>;
phy-mode = "rmii";
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@13 {
reg = <0x13>;
};
};
};
&nand {
status = "okay";
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "kernel";
reg = <0x0 0x1000000>;
};
partition@1000000 {
label = "rootfs";
reg = <0x1000000 0x3f000000>;
};
};
};
};
&ehci {
status = "okay";
};
&ohci {
status = "okay";
};
&rtc {
status = "okay";
};
&uart2 {
status = "okay";
};
&watchdog {
status = "okay";
};

136
arch/mips/boot/dts/loongson/loongson1.dtsi Normal file
View File

@@ -0,0 +1,136 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2023-2025 Keguang Zhang <keguang.zhang@gmail.com>
*/
/dts-v1/;
#include <dt-bindings/clock/loongson,ls1x-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
xtal: clock {
compatible = "fixed-clock";
clock-output-names = "xtal";
#clock-cells = <0>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
reg = <0>;
device_type = "cpu";
clocks = <&clkc LS1X_CLKID_CPU>;
#clock-cells = <1>;
};
};
cpu_intc: interrupt-controller {
compatible = "mti,cpu-interrupt-controller";
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <0>;
};
soc: bus@1fd00000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1fd00000 0x130000>;
intc0: interrupt-controller@1040 {
compatible = "loongson,ls1x-intc";
reg = <0x1040 0x18>;
interrupt-controller;
interrupt-parent = <&cpu_intc>;
interrupts = <2>;
#interrupt-cells = <2>;
};
intc1: interrupt-controller@1058 {
compatible = "loongson,ls1x-intc";
reg = <0x1058 0x18>;
interrupt-controller;
interrupt-parent = <&cpu_intc>;
interrupts = <3>;
#interrupt-cells = <2>;
};
intc2: interrupt-controller@1070 {
compatible = "loongson,ls1x-intc";
reg = <0x1070 0x18>;
interrupt-controller;
interrupt-parent = <&cpu_intc>;
interrupts = <4>;
#interrupt-cells = <2>;
};
intc3: interrupt-controller@1088 {
compatible = "loongson,ls1x-intc";
reg = <0x1088 0x18>;
interrupt-controller;
interrupt-parent = <&cpu_intc>;
interrupts = <5>;
#interrupt-cells = <2>;
};
gpio0: gpio@10c0 {
compatible = "loongson,ls1x-gpio";
reg = <0x10c0 0x4>;
gpio-controller;
#gpio-cells = <2>;
};
gpio1: gpio@10c4 {
compatible = "loongson,ls1x-gpio";
reg = <0x10c4 0x4>;
gpio-controller;
#gpio-cells = <2>;
};
};
apb: bus@1fe40000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1fe40000 0xc0000>;
uart0: serial@0 {
compatible = "ns16550a";
reg = <0x0 0x8>;
clocks = <&clkc LS1X_CLKID_APB>;
interrupt-parent = <&intc0>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart1: serial@4000 {
compatible = "ns16550a";
reg = <0x4000 0x8>;
clocks = <&clkc LS1X_CLKID_APB>;
interrupt-parent = <&intc0>;
status = "disabled";
};
uart2: serial@8000 {
compatible = "ns16550a";
reg = <0x8000 0x8>;
clocks = <&clkc LS1X_CLKID_APB>;
interrupt-parent = <&intc0>;
status = "disabled";
};
uart3: serial@c000 {
compatible = "ns16550a";
reg = <0xc000 0x8>;
clocks = <&clkc LS1X_CLKID_APB>;
interrupt-parent = <&intc0>;
status = "disabled";
};
};
};

198
arch/mips/boot/dts/loongson/loongson1b.dtsi Normal file
View File

@@ -0,0 +1,198 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2023-2025 Keguang Zhang <keguang.zhang@gmail.com>
*/
/dts-v1/;
#include "loongson1.dtsi"
/ {
cpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-shared;
opp-44000000 {
opp-hz = /bits/ 64 <44000000>;
};
opp-47142000 {
opp-hz = /bits/ 64 <47142000>;
};
opp-50769000 {
opp-hz = /bits/ 64 <50769000>;
};
opp-55000000 {
opp-hz = /bits/ 64 <55000000>;
};
opp-60000000 {
opp-hz = /bits/ 64 <60000000>;
};
opp-66000000 {
opp-hz = /bits/ 64 <66000000>;
};
opp-73333000 {
opp-hz = /bits/ 64 <73333000>;
};
opp-82500000 {
opp-hz = /bits/ 64 <82500000>;
};
opp-94285000 {
opp-hz = /bits/ 64 <94285000>;
};
opp-110000000 {
opp-hz = /bits/ 64 <110000000>;
};
opp-132000000 {
opp-hz = /bits/ 64 <132000000>;
};
opp-165000000 {
opp-hz = /bits/ 64 <165000000>;
};
opp-220000000 {
opp-hz = /bits/ 64 <220000000>;
};
};
clkc: clock-controller@1fe78030 {
compatible = "loongson,ls1b-clk";
reg = <0x1fe78030 0x8>;
clocks = <&xtal>;
#clock-cells = <1>;
};
};
&soc {
syscon: syscon@420 {
compatible = "loongson,ls1b-syscon", "syscon";
reg = <0x420 0x8>;
};
dma: dma-controller@1160 {
compatible = "loongson,ls1b-apbdma";
reg = <0x1160 0x4>;
interrupt-parent = <&intc0>;
interrupts = <13 IRQ_TYPE_EDGE_RISING>,
<14 IRQ_TYPE_EDGE_RISING>,
<15 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ch0", "ch1", "ch2";
#dma-cells = <1>;
};
ehci: usb@100000 {
compatible = "generic-ehci";
reg = <0x100000 0x100>;
interrupt-parent = <&intc1>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
ohci: usb@108000 {
compatible = "generic-ohci";
reg = <0x108000 0x100>;
interrupt-parent = <&intc1>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
gmac0: ethernet@110000 {
compatible = "loongson,ls1b-gmac", "snps,dwmac-3.50a";
reg = <0x110000 0x10000>;
clocks = <&clkc LS1X_CLKID_AHB>;
clock-names = "stmmaceth";
interrupt-parent = <&intc1>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
loongson,ls1-syscon = <&syscon>;
snps,pbl = <1>;
status = "disabled";
};
gmac1: ethernet@120000 {
compatible = "loongson,ls1b-gmac", "snps,dwmac-3.50a";
reg = <0x120000 0x10000>;
clocks = <&clkc LS1X_CLKID_AHB>;
clock-names = "stmmaceth";
interrupt-parent = <&intc1>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
loongson,ls1-syscon = <&syscon>;
snps,pbl = <1>;
status = "disabled";
};
};
&apb {
clocksource: timer@1c030 {
compatible = "loongson,ls1b-pwmtimer";
reg = <0x1c030 0x10>;
clocks = <&clkc LS1X_CLKID_APB>;
interrupt-parent = <&intc0>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
};
watchdog: watchdog@1c060 {
compatible = "loongson,ls1b-wdt";
reg = <0x1c060 0xc>;
clocks = <&clkc LS1X_CLKID_APB>;
status = "disabled";
};
rtc: rtc@24000 {
compatible = "loongson,ls1b-rtc";
reg = <0x24000 0x78>;
interrupt-parent = <&intc0>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
ac97: audio-controller@34000 {
compatible = "loongson,ls1b-ac97";
reg = <0x34000 0x60>, <0x32420 0x4>, <0x34c4c 0x4>;
reg-names = "ac97", "audio-tx", "audio-rx";
dmas = <&dma 1>, <&dma 2>;
dma-names = "tx", "rx";
#sound-dai-cells = <0>;
status = "disabled";
};
nand: nand-controller@38000 {
compatible = "loongson,ls1b-nand-controller";
reg = <0x38000 0x24>, <0x38040 0x4>;
reg-names = "nand", "nand-dma";
dmas = <&dma 0>;
dma-names = "rxtx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
nand@0 {
reg = <0>;
label = "ls1x-nand";
nand-use-soft-ecc-engine;
nand-ecc-algo = "hamming";
};
};
};
&cpu0 {
operating-points-v2 = <&cpu_opp_table>;
};
&gpio0 {
ngpios = <31>;
};
&gpio1 {
ngpios = <30>;
};
&uart1 {
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
};
&uart2 {
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
};
&uart3 {
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
};

141
arch/mips/boot/dts/loongson/loongson1c.dtsi Normal file
View File

@@ -0,0 +1,141 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2023-2025 Keguang Zhang <keguang.zhang@gmail.com>
*/
/dts-v1/;
#include "loongson1.dtsi"
/ {
clkc: clock-controller@1fe78030 {
compatible = "loongson,ls1c-clk";
reg = <0x1fe78030 0x8>;
clocks = <&xtal>;
#clock-cells = <1>;
};
};
&soc {
syscon: syscon@420 {
compatible = "loongson,ls1c-syscon", "syscon";
reg = <0x420 0x8>;
};
intc4: interrupt-controller@10a0 {
compatible = "loongson,ls1x-intc";
reg = <0x10a0 0x18>;
interrupt-controller;
interrupt-parent = <&cpu_intc>;
interrupts = <6>;
#interrupt-cells = <2>;
};
gpio2: gpio@10c8 {
compatible = "loongson,ls1x-gpio";
reg = <0x10c8 0x4>;
gpio-controller;
ngpios = <32>;
#gpio-cells = <2>;
};
gpio3: gpio@10cc {
compatible = "loongson,ls1x-gpio";
reg = <0x10cc 0x4>;
gpio-controller;
ngpios = <32>;
#gpio-cells = <2>;
};
dma: dma-controller@1160 {
compatible = "loongson,ls1c-apbdma", "loongson,ls1b-apbdma";
reg = <0x1160 0x4>;
interrupt-parent = <&intc0>;
interrupts = <13 IRQ_TYPE_EDGE_RISING>,
<14 IRQ_TYPE_EDGE_RISING>,
<15 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ch0", "ch1", "ch2";
#dma-cells = <1>;
};
emac: ethernet@110000 {
compatible = "loongson,ls1c-emac", "snps,dwmac-3.50a";
reg = <0x110000 0x10000>;
clocks = <&clkc LS1X_CLKID_AHB>;
clock-names = "stmmaceth";
interrupt-parent = <&intc1>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
loongson,ls1-syscon = <&syscon>;
snps,pbl = <1>;
status = "disabled";
};
ehci: usb@120000 {
compatible = "generic-ehci";
reg = <0x120000 0x100>;
interrupt-parent = <&intc1>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
ohci: usb@128000 {
compatible = "generic-ohci";
reg = <0x128000 0x100>;
interrupt-parent = <&intc1>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
&apb {
watchdog: watchdog@1c060 {
compatible = "loongson,ls1c-wdt";
reg = <0x1c060 0xc>;
clocks = <&clkc LS1X_CLKID_APB>;
status = "disabled";
};
rtc: rtc@24000 {
compatible = "loongson,ls1c-rtc";
reg = <0x24000 0x78>;
status = "disabled";
};
nand: nand-controller@38000 {
compatible = "loongson,ls1c-nand-controller";
reg = <0x38000 0x24>, <0x38040 0x4>;
reg-names = "nand", "nand-dma";
dmas = <&dma 0>;
dma-names = "rxtx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
nand@0 {
reg = <0>;
label = "ls1x-nand";
nand-use-soft-ecc-engine;
nand-ecc-algo = "hamming";
};
};
};
&gpio0 {
ngpios = <32>;
};
&gpio1 {
ngpios = <32>;
};
&uart1 {
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
};
&uart2 {
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
};
&uart3 {
interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
};

125
arch/mips/boot/dts/loongson/ls1b-demo.dts Normal file
View File

@@ -0,0 +1,125 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2023-2025 Keguang Zhang <keguang.zhang@gmail.com>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "loongson1b.dtsi"
/ {
compatible = "loongson,ls1b-demo", "loongson,ls1b";
model = "LS1B-DEMO Board";
memory@0 {
device_type = "memory";
reg = <0x0 0x10000000>;
};
aliases {
ethernet0 = &gmac0;
ethernet1 = &gmac1;
gpio0 = &gpio0;
gpio1 = &gpio1;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:38400n8";
};
codec: audio-codec {
compatible = "realtek,alc203";
#sound-dai-cells = <0>;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "ls1b-alc203";
simple-audio-card,format = "ac97";
simple-audio-card,widgets =
"Speaker", "Line Out Jack",
"Headphone", "Headphone Jack",
"Microphone", "Microphone Jack";
simple-audio-card,routing =
"Line Out Jack", "TX",
"Headphone Jack", "TX",
"RX", "Microphone Jack";
simple-audio-card,cpu {
sound-dai = <&ac97>;
};
simple-audio-card,codec {
sound-dai = <&codec>;
};
};
};
&xtal {
clock-frequency = <33000000>;
};
&gmac0 {
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0x0>;
};
};
};
&nand {
status = "okay";
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "kernel";
reg = <0x0 0x1000000>;
};
partition@1000000 {
label = "rootfs";
reg = <0x1000000 0x7000000>;
};
};
};
};
&ac97 {
status = "okay";
};
&ehci {
status = "okay";
};
&ohci {
status = "okay";
};
&rtc {
status = "okay";
};
&uart0 {
status = "okay";
};
&watchdog {
status = "okay";
};

162
arch/mips/boot/dts/loongson/lsgz_1b_dev.dts Normal file
View File

@@ -0,0 +1,162 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2023-2025 Keguang Zhang <keguang.zhang@gmail.com>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "loongson1b.dtsi"
/ {
compatible = "loongson,lsgz-1b-dev", "loongson,ls1b";
model = "LSGZ_1B_DEV Board";
memory@0 {
device_type = "memory";
reg = <0x0 0x4000000>;
};
aliases {
ethernet0 = &gmac0;
ethernet1 = &gmac1;
gpio0 = &gpio0;
gpio1 = &gpio1;
serial0 = &uart2;
serial1 = &uart3;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
led9 {
label = "led9";
gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
led6 {
label = "led6";
gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
linux,default-trigger = "nand-disk";
};
};
codec: audio-codec {
compatible = "realtek,alc203";
#sound-dai-cells = <0>;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "ls1b-alc655";
simple-audio-card,format = "ac97";
simple-audio-card,widgets =
"Speaker", "Line Out Jack",
"Line", "Line In Jack",
"Microphone", "Microphone Jack";
simple-audio-card,routing =
"Line Out Jack", "TX",
"RX", "Line In Jack",
"RX", "Microphone Jack";
simple-audio-card,cpu {
sound-dai = <&ac97>;
};
simple-audio-card,codec {
sound-dai = <&codec>;
};
};
};
&xtal {
clock-frequency = <33000000>;
};
&gmac0 {
phy-handle = <&phy0>;
phy-mode = "mii";
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@0 {
reg = <0x0>;
};
};
};
&gmac1 {
phy-handle = <&phy1>;
phy-mode = "mii";
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
phy1: ethernet-phy@0 {
reg = <0x0>;
};
};
};
&nand {
status = "okay";
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "kernel";
reg = <0x0 0x1000000>;
};
partition@1000000 {
label = "rootfs";
reg = <0x1000000 0x7000000>;
};
};
};
};
&ac97 {
status = "okay";
};
&ehci {
status = "okay";
};
&ohci {
status = "okay";
};
&rtc {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart3 {
status = "okay";
};
&watchdog {
status = "okay";
};

110
arch/mips/boot/dts/loongson/smartloong-1c.dts Normal file
View File

@@ -0,0 +1,110 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2023-2025 Keguang Zhang <keguang.zhang@gmail.com>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "loongson1c.dtsi"
/ {
compatible = "loongmasses,smartloong-1c", "loongson,ls1c";
model = "Smartloong-1C Board";
memory@0 {
device_type = "memory";
reg = <0x0 0x4000000>;
};
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
serial0 = &uart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
led0 {
label = "led0";
gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
led1 {
label = "led1";
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
linux,default-trigger = "nand-disk";
};
};
};
&xtal {
clock-frequency = <24000000>;
};
&emac {
phy-handle = <&phy0>;
phy-mode = "rmii";
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@13 {
reg = <0x13>;
};
};
};
&nand {
status = "okay";
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "kernel";
reg = <0x0 0x1000000>;
};
partition@1000000 {
label = "rootfs";
reg = <0x1000000 0x7000000>;
};
};
};
};
&ehci {
status = "okay";
};
&ohci {
status = "okay";
};
&rtc {
status = "okay";
};
&uart2 {
status = "okay";
};
&watchdog {
status = "okay";
};

31
arch/mips/cavium-octeon/executive/octeon-model.c
View File

@@ -25,6 +25,7 @@
* Contact Cavium Networks for more information
***********************license end**************************************/
#include <linux/string.h>
#include <asm/octeon/octeon.h>
enum octeon_feature_bits __octeon_feature_bits __read_mostly;
@@ -208,16 +209,16 @@ static const char *__init octeon_model_get_string_buffer(uint32_t chip_id,
*/
switch (chip_id & 0xf) {
case 0:
strcpy(pass, "1.X");
strscpy(pass, "1.X");
break;
case 1:
strcpy(pass, "2.X");
strscpy(pass, "2.X");
break;
case 3:
strcpy(pass, "3.X");
strscpy(pass, "3.X");
break;
default:
strcpy(pass, "X.X");
strscpy(pass, "X.X");
break;
}
break;
@@ -232,13 +233,13 @@ static const char *__init octeon_model_get_string_buffer(uint32_t chip_id,
*/
switch (chip_id & 0xf) {
case 0:
strcpy(pass, "1.0");
strscpy(pass, "1.0");
break;
case 2:
strcpy(pass, "1.1");
strscpy(pass, "1.1");
break;
default:
strcpy(pass, "X.X");
strscpy(pass, "X.X");
break;
}
break;
@@ -253,13 +254,13 @@ static const char *__init octeon_model_get_string_buffer(uint32_t chip_id,
*/
switch (chip_id & 0xf) {
case 0:
strcpy(pass, "1.0");
strscpy(pass, "1.0");
break;
case 2:
strcpy(pass, "1.1");
strscpy(pass, "1.1");
break;
default:
strcpy(pass, "X.X");
strscpy(pass, "X.X");
break;
}
break;
@@ -273,16 +274,16 @@ static const char *__init octeon_model_get_string_buffer(uint32_t chip_id,
if ((chip_id & 0xFF) < 0x8) {
switch (chip_id & 0x3) {
case 0:
strcpy(pass, "1.0");
strscpy(pass, "1.0");
break;
case 1:
strcpy(pass, "1.1");
strscpy(pass, "1.1");
break;
case 3:
strcpy(pass, "1.2");
strscpy(pass, "1.2");
break;
default:
strcpy(pass, "1.X");
strscpy(pass, "1.X");
break;
}
}
@@ -447,7 +448,7 @@ static const char *__init octeon_model_get_string_buffer(uint32_t chip_id,
default:
family = "XX";
core_model = "XX";
strcpy(pass, "X.X");
strscpy(pass, "X.X");
suffix = "XXX";
break;
}

4
arch/mips/cavium-octeon/octeon-platform.c
View File

@@ -13,6 +13,7 @@
#include <linux/of_fdt.h>
#include <linux/platform_device.h>
#include <linux/libfdt.h>
#include <linux/string.h>
#include <asm/octeon/octeon.h>
#include <asm/octeon/cvmx-helper-board.h>
@@ -538,8 +539,7 @@ static void __init octeon_fdt_set_phy(int eth, int phy_addr)
if (octeon_has_88e1145()) {
fdt_nop_property(initial_boot_params, phy, "marvell,reg-init");
memset(new_name, 0, sizeof(new_name));
strcpy(new_name, "marvell,88e1145");
strscpy_pad(new_name, "marvell,88e1145");
p = fdt_getprop(initial_boot_params, phy, "compatible",
&current_len);
if (p && current_len >= strlen(new_name))

2
arch/mips/cavium-octeon/smp.c
View File

@@ -334,7 +334,7 @@ static void octeon_cpu_die(unsigned int cpu)
new_mask = *p;
}
pr_info("Reset core %d. Available Coremask = 0x%x \n", coreid, new_mask);
pr_info("Reset core %d. Available Coremask = 0x%x\n", coreid, new_mask);
mb();
cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
cvmx_write_csr(CVMX_CIU_PP_RST, 0);

94
arch/mips/configs/loongson1b_defconfig → arch/mips/configs/loongson1_defconfig
View File

@@ -1,7 +1,6 @@
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_KERNEL_XZ=y
CONFIG_SYSVIPC=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
@@ -12,15 +11,16 @@ CONFIG_NAMESPACES=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_EXPERT=y
CONFIG_PERF_EVENTS=y
# CONFIG_COMPAT_BRK is not set
CONFIG_MACH_LOONGSON32=y
# CONFIG_SECCOMP is not set
# CONFIG_SUSPEND is not set
# CONFIG_SECCOMP is not set
# CONFIG_GCC_PLUGINS is not set
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_BLOCK_LEGACY_AUTOLOAD is not set
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -31,6 +31,7 @@ CONFIG_SYN_COOKIES=y
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
# CONFIG_ETHTOOL_NETLINK is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_STANDALONE is not set
@@ -38,32 +39,75 @@ CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_LOONGSON1=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_SCSI=m
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=m
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_ALACRITECH is not set
# CONFIG_NET_VENDOR_AMAZON is not set
# CONFIG_NET_VENDOR_AQUANTIA is not set
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_VENDOR_ASIX is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CADENCE is not set
# CONFIG_NET_VENDOR_CAVIUM is not set
# CONFIG_NET_VENDOR_CORTINA is not set
# CONFIG_NET_VENDOR_DAVICOM is not set
# CONFIG_NET_VENDOR_ENGLEDER is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_FUNGIBLE is not set
# CONFIG_NET_VENDOR_GOOGLE is not set
# CONFIG_NET_VENDOR_HISILICON is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_LITEX is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_META is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MICROCHIP is not set
# CONFIG_NET_VENDOR_MICROSEMI is not set
# CONFIG_NET_VENDOR_MICROSOFT is not set
# CONFIG_NET_VENDOR_NI is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_NETRONOME is not set
# CONFIG_NET_VENDOR_PENSANDO is not set
# CONFIG_NET_VENDOR_QUALCOMM is not set
# CONFIG_NET_VENDOR_RENESAS is not set
# CONFIG_NET_VENDOR_ROCKER is not set
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_SOCIONEXT is not set
CONFIG_STMMAC_ETH=y
# CONFIG_DWMAC_GENERIC is not set
# CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_VERTEXCOM is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WANGXUN is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_NET_VENDOR_XILINX is not set
CONFIG_DAVICOM_PHY=y
CONFIG_REALTEK_PHY=y
# CONFIG_USB_NET_DRIVERS is not set
# CONFIG_WLAN is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_VT_CONSOLE is not set
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_LEGACY_PTY_COUNT=8
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
# CONFIG_PTP_1588_CLOCK is not set
CONFIG_GPIOLIB=y
CONFIG_GPIO_LOONGSON1=y
# CONFIG_HWMON is not set
@@ -71,7 +115,15 @@ CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_NOWAYOUT=y
CONFIG_WATCHDOG_SYSFS=y
CONFIG_LOONGSON1_WDT=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_SOUND=y
CONFIG_SND=y
# CONFIG_SND_SUPPORT_OLD_API is not set
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_MIPS is not set
# CONFIG_SND_USB is not set
CONFIG_SND_SOC=y
CONFIG_SND_LOONGSON1_AC97=y
CONFIG_SND_SIMPLE_CARD=y
CONFIG_HID_GENERIC=m
CONFIG_USB_HID=m
CONFIG_USB=y
@@ -86,17 +138,20 @@ CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_MTD=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_LOONGSON1=y
# CONFIG_RTC_NVMEM is not set
CONFIG_RTC_DRV_LOONGSON=y
CONFIG_DMADEVICES=y
CONFIG_LOONGSON1_APB_DMA=y
# CONFIG_VIRTIO_MENU is not set
# CONFIG_VHOST_MENU is not set
# CONFIG_MIPS_PLATFORM_DEVICES is not set
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT2_FS_SECURITY=y
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_EXT3_FS_SECURITY=y
# CONFIG_NVMEM is not set
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
# CONFIG_DNOTIFY is not set
CONFIG_VFAT_FS=y
CONFIG_PROC_KCORE=y
@@ -105,16 +160,21 @@ CONFIG_TMPFS_POSIX_ACL=y
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
CONFIG_UBIFS_ATIME_SUPPORT=y
# CONFIG_UBIFS_FS_SECURITY is not set
CONFIG_NFS_FS=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=m
CONFIG_NLS_ISO8859_1=m
# CONFIG_CRYPTO_ECHAINIV is not set
# CONFIG_CRYPTO_HW is not set
# CONFIG_XZ_DEC_X86 is not set
# CONFIG_XZ_DEC_POWERPC is not set
# CONFIG_XZ_DEC_ARM is not set
# CONFIG_XZ_DEC_ARMTHUMB is not set
# CONFIG_XZ_DEC_ARM64 is not set
# CONFIG_XZ_DEC_SPARC is not set
# CONFIG_XZ_DEC_RISCV is not set
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DEBUG_FS=y
# CONFIG_DEBUG_MISC is not set
CONFIG_MAGIC_SYSRQ=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_FTRACE is not set
# CONFIG_EARLY_PRINTK is not set

121
arch/mips/configs/loongson1c_defconfig
View File

@@ -1,121 +0,0 @@
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_KERNEL_XZ=y
CONFIG_SYSVIPC=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=16
CONFIG_NAMESPACES=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_EXPERT=y
CONFIG_PERF_EVENTS=y
# CONFIG_COMPAT_BRK is not set
CONFIG_MACH_LOONGSON32=y
CONFIG_LOONGSON1_LS1C=y
# CONFIG_SECCOMP is not set
# CONFIG_SUSPEND is not set
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_SYN_COOKIES=y
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_STANDALONE is not set
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_SCSI=m
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=m
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SMSC is not set
CONFIG_STMMAC_ETH=y
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_WLAN is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_LEGACY_PTY_COUNT=8
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_GPIOLIB=y
CONFIG_GPIO_LOONGSON1=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_NOWAYOUT=y
CONFIG_WATCHDOG_SYSFS=y
CONFIG_LOONGSON1_WDT=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_HID_GENERIC=m
CONFIG_USB_HID=m
CONFIG_USB=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_STORAGE=m
CONFIG_USB_SERIAL=m
CONFIG_USB_SERIAL_PL2303=m
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_LOONGSON1=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT2_FS_SECURITY=y
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_EXT3_FS_SECURITY=y
# CONFIG_DNOTIFY is not set
CONFIG_VFAT_FS=y
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
CONFIG_UBIFS_ATIME_SUPPORT=y
CONFIG_NFS_FS=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=m
CONFIG_NLS_ISO8859_1=m
# CONFIG_CRYPTO_ECHAINIV is not set
# CONFIG_CRYPTO_HW is not set
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DEBUG_FS=y
CONFIG_MAGIC_SYSRQ=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_FTRACE is not set
# CONFIG_EARLY_PRINTK is not set

22
arch/mips/fw/arc/cmdline.c
View File

@@ -42,12 +42,13 @@ static char __init *move_firmware_args(int argc, LONG *argv, char *cp)
{
char *s;
int actr, i;
size_t len;
actr = 1; /* Always ignore argv[0] */
while (actr < argc) {
for(i = 0; i < ARRAY_SIZE(used_arc); i++) {
int len = strlen(used_arc[i][0]);
for (i = 0; i < ARRAY_SIZE(used_arc); i++) {
len = strlen(used_arc[i][0]);
if (!strncmp(prom_argv(actr), used_arc[i][0], len)) {
/* Ok, we want it. First append the replacement... */
@@ -57,8 +58,9 @@ static char __init *move_firmware_args(int argc, LONG *argv, char *cp)
s = strchr(prom_argv(actr), '=');
if (s) {
s++;
strcpy(cp, s);
cp += strlen(s);
len = strlen(s);
memcpy(cp, s, len + 1);
cp += len;
}
*cp++ = ' ';
break;
@@ -74,6 +76,7 @@ void __init prom_init_cmdline(int argc, LONG *argv)
{
char *cp;
int actr, i;
size_t len;
actr = 1; /* Always ignore argv[0] */
@@ -86,14 +89,15 @@ void __init prom_init_cmdline(int argc, LONG *argv)
while (actr < argc) {
for (i = 0; i < ARRAY_SIZE(ignored); i++) {
int len = strlen(ignored[i]);
len = strlen(ignored[i]);
if (!strncmp(prom_argv(actr), ignored[i], len))
goto pic_cont;
}
/* Ok, we want it. */
strcpy(cp, prom_argv(actr));
cp += strlen(prom_argv(actr));
len = strlen(prom_argv(actr));
memcpy(cp, prom_argv(actr), len + 1);
cp += len;
*cp++ = ' ';
pic_cont:
@@ -105,6 +109,6 @@ void __init prom_init_cmdline(int argc, LONG *argv)
*cp = '\0';
#ifdef DEBUG_CMDLINE
printk(KERN_DEBUG "prom cmdline: %s\n", arcs_cmdline);
pr_debug("prom cmdline: %s\n", arcs_cmdline);
#endif
}

3
arch/mips/generic/board-ocelot.c
View File

@@ -4,6 +4,7 @@
*
* Copyright (c) 2017 Microsemi Corporation
*/
#include <linux/string.h>
#include <asm/machine.h>
#include <asm/prom.h>
@@ -41,7 +42,7 @@ static __init bool ocelot_detect(void)
if (prom_argc > 1 && strlen(prom_argv[1]) > 0)
/* ignore all built-in args if any f/w args given */
strcpy(arcs_cmdline, prom_argv[1]);
strscpy(arcs_cmdline, prom_argv[1]);
}
return true;

4
arch/mips/include/asm/addrspace.h
View File

@@ -15,7 +15,7 @@
/*
* Configure language
*/
#ifdef __ASSEMBLY__
#ifdef __ASSEMBLER__
#define _ATYPE_
#define _ATYPE32_
#define _ATYPE64_
@@ -34,7 +34,7 @@
/*
* 32-bit MIPS address spaces
*/
#ifdef __ASSEMBLY__
#ifdef __ASSEMBLER__
#define _ACAST32_
#define _ACAST64_
#else

6
arch/mips/include/asm/asm-eva.h
View File

@@ -10,7 +10,7 @@
#ifndef __ASM_ASM_EVA_H
#define __ASM_ASM_EVA_H
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
/* Kernel variants */
@@ -99,7 +99,7 @@
#endif /* CONFIG_EVA */
#else /* __ASSEMBLY__ */
#else /* __ASSEMBLER__ */
#define kernel_cache(op, base) cache op, base
#define kernel_pref(hint, base) pref hint, base
@@ -185,6 +185,6 @@
#endif /* CONFIG_EVA */
#endif /* __ASSEMBLY__ */
#endif /* __ASSEMBLER__ */
#endif /* __ASM_ASM_EVA_H */

8
arch/mips/include/asm/asm.h
View File

@@ -37,7 +37,7 @@
#define CFI_SECTIONS
#endif
#ifdef __ASSEMBLY__
#ifdef __ASSEMBLER__
/*
* LEAF - declare leaf routine
*/
@@ -123,7 +123,7 @@ symbol = value
#define ASM_PRINT(string)
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ASSEMBLER__ */
/*
* Stack alignment
@@ -228,7 +228,7 @@ symbol = value
#define LONG_INS ins
#define LONG_EXT ext
#ifdef __ASSEMBLY__
#ifdef __ASSEMBLER__
#define LONG .word
#endif
#define LONGSIZE 4
@@ -257,7 +257,7 @@ symbol = value
#define LONG_INS dins
#define LONG_EXT dext
#ifdef __ASSEMBLY__
#ifdef __ASSEMBLER__
#define LONG .dword
#endif
#define LONGSIZE 8

4
arch/mips/include/asm/bmips.h
View File

@@ -42,7 +42,7 @@
#define ZSCM_REG_BASE 0x97000000
#if !defined(__ASSEMBLY__)
#if !defined(__ASSEMBLER__)
#include <linux/cpumask.h>
#include <asm/r4kcache.h>
@@ -124,6 +124,6 @@ static inline void bmips_write_zscm_reg(unsigned int offset, unsigned long data)
barrier();
}
#endif /* !defined(__ASSEMBLY__) */
#endif /* !defined(__ASSEMBLER__) */
#endif /* _ASM_BMIPS_H */

3
arch/mips/include/asm/cpu-type.h
View File

@@ -24,8 +24,7 @@ static inline int __pure __get_cpu_type(const int cpu_type)
case CPU_LOONGSON64:
#endif
#if defined(CONFIG_SYS_HAS_CPU_LOONGSON1B) || \
defined(CONFIG_SYS_HAS_CPU_LOONGSON1C)
#ifdef CONFIG_SYS_HAS_CPU_LOONGSON32
case CPU_LOONGSON32:
#endif

7
arch/mips/include/asm/cpu.h
View File

@@ -248,8 +248,7 @@
#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
#define PRID_REV_VR4130 0x0080
#define PRID_REV_34K_V1_0_2 0x0022
#define PRID_REV_LOONGSON1B 0x0020
#define PRID_REV_LOONGSON1C 0x0020 /* Same as Loongson-1B */
#define PRID_REV_LOONGSON1 0x0020
#define PRID_REV_LOONGSON2E 0x0002
#define PRID_REV_LOONGSON2F 0x0003
#define PRID_REV_LOONGSON2K_R1_0 0x0000
@@ -288,7 +287,7 @@
#define FPIR_IMP_NONE 0x0000
#if !defined(__ASSEMBLY__)
#if !defined(__ASSEMBLER__)
enum cpu_type_enum {
CPU_UNKNOWN,
@@ -329,7 +328,7 @@ enum cpu_type_enum {
CPU_LAST
};
#endif /* !__ASSEMBLY */
#endif /* !__ASSEMBLER__ */
/*
* ISA Level encodings

2
arch/mips/include/asm/dec/ecc.h
View File

@@ -37,7 +37,7 @@
#define KN0X_ESR_SYNLO (0x7f<<0) /* syndrome from ECC logic */
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#include <linux/interrupt.h>

4
arch/mips/include/asm/dec/interrupts.h
View File

@@ -95,7 +95,7 @@
#define DEC_CPU_IRQ_ALL (0xff << CAUSEB_IP)
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
/*
* Interrupt table structures to hide differences between systems.
@@ -121,6 +121,6 @@ extern void cpu_all_int(void);
extern void dec_intr_unimplemented(void);
extern void asic_intr_unimplemented(void);
#endif /* __ASSEMBLY__ */
#endif /* __ASSEMBLER__ */
#endif

2
arch/mips/include/asm/dec/kn01.h
View File

@@ -71,7 +71,7 @@
#define KN01_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#include <linux/interrupt.h>
#include <linux/spinlock.h>

2
arch/mips/include/asm/dec/kn02.h
View File

@@ -80,7 +80,7 @@
#define KN02_IRQ_ALL 0xff
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#include <linux/types.h>

2
arch/mips/include/asm/dec/kn02xa.h
View File

@@ -70,7 +70,7 @@
#define KN02XA_EAR_RES_0 (0x3<<0) /* unused */
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#include <linux/interrupt.h>

4
arch/mips/include/asm/eva.h
View File

@@ -13,7 +13,7 @@
#include <kernel-entry-init.h>
#ifdef __ASSEMBLY__
#ifdef __ASSEMBLER__
#ifdef CONFIG_EVA
@@ -38,6 +38,6 @@ platform_eva_init
#endif /* CONFIG_EVA */
#endif /* __ASSEMBLY__ */
#endif /* __ASSEMBLER__ */
#endif

8
arch/mips/include/asm/ftrace.h
View File

@@ -15,7 +15,7 @@
#define MCOUNT_ADDR ((unsigned long)(_mcount))
#define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
extern void _mcount(void);
#define mcount _mcount
@@ -89,11 +89,11 @@ struct dyn_arch_ftrace {
void prepare_ftrace_return(unsigned long *parent_ra_addr, unsigned long self_ra,
unsigned long fp);
#endif /* __ASSEMBLY__ */
#endif /* __ASSEMBLER__ */
#endif /* CONFIG_FUNCTION_TRACER */
#ifdef CONFIG_FTRACE_SYSCALLS
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
/*
* Some syscall entry functions on mips start with "__sys_" (fork and clone,
* for instance). We should also match the sys_ variant with those.
@@ -105,6 +105,6 @@ static inline bool arch_syscall_match_sym_name(const char *sym,
return !strcmp(sym, name) ||
(!strncmp(sym, "__sys_", 6) && !strcmp(sym + 6, name + 4));
}
#endif /* __ASSEMBLY__ */
#endif /* __ASSEMBLER__ */
#endif /* CONFIG_FTRACE_SYSCALLS */
#endif /* _ASM_MIPS_FTRACE_H */

4
arch/mips/include/asm/hazards.h
View File

@@ -301,7 +301,7 @@ do { \
#endif
#ifdef __ASSEMBLY__
#ifdef __ASSEMBLER__
#define _ssnop ___ssnop
#define _ehb ___ehb
@@ -417,6 +417,6 @@ do { \
*/
extern void mips_ihb(void);
#endif /* __ASSEMBLY__ */
#endif /* __ASSEMBLER__ */
#endif /* _ASM_HAZARDS_H */

4
arch/mips/include/asm/irqflags.h
View File

@@ -11,7 +11,7 @@
#ifndef _ASM_IRQFLAGS_H
#define _ASM_IRQFLAGS_H
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#include <linux/compiler.h>
#include <linux/stringify.h>
@@ -142,7 +142,7 @@ static inline int arch_irqs_disabled(void)
return arch_irqs_disabled_flags(arch_local_save_flags());
}
#endif /* #ifndef __ASSEMBLY__ */
#endif /* #ifndef __ASSEMBLER__ */
/*
* Do the CPU's IRQ-state tracing from assembly code.

16
arch/mips/include/asm/jazz.h
View File

@@ -70,7 +70,7 @@
#define LED_E 0x9e
#define LED_F 0x8e
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
static __inline__ void pica_set_led(unsigned int bits)
{
@@ -79,7 +79,7 @@ static __inline__ void pica_set_led(unsigned int bits)
*led_register = bits;
}
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
/*
* Base address of the Sonic Ethernet adapter in Jazz machines.
@@ -100,7 +100,7 @@ static __inline__ void pica_set_led(unsigned int bits)
#define JAZZ_KEYBOARD_DATA 0xe0005000
#define JAZZ_KEYBOARD_COMMAND 0xe0005001
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
typedef struct {
unsigned char data;
@@ -121,7 +121,7 @@ typedef struct {
*/
#define keyboard_hardware jazz_keyboard_hardware
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
/*
* i8042 keyboard controller for most other Mips machines.
@@ -154,7 +154,7 @@ typedef struct {
/*
* DRAM configuration register
*/
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#ifdef __MIPSEL__
typedef struct {
unsigned int bank2 : 3;
@@ -174,7 +174,7 @@ typedef struct {
unsigned int bank2 : 3;
} dram_configuration;
#endif
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
#define PICA_DRAM_CONFIG 0xe00fffe0
@@ -260,7 +260,7 @@ typedef struct {
/*
* Access the R4030 DMA and I/O Controller
*/
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
static inline void r4030_delay(void)
{
@@ -299,7 +299,7 @@ static inline void r4030_write_reg32(unsigned long addr, unsigned val)
r4030_delay();
}
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
#define JAZZ_FDC_BASE 0xe0003000
#define JAZZ_RTC_BASE 0xe0004000

4
arch/mips/include/asm/jump_label.h
View File

@@ -10,7 +10,7 @@
#define arch_jump_label_transform_static arch_jump_label_transform
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#include <linux/types.h>
#include <asm/isa-rev.h>
@@ -76,5 +76,5 @@ struct jump_entry {
jump_label_t key;
};
#endif /* __ASSEMBLY__ */
#endif /* __ASSEMBLER__ */
#endif /* _ASM_MIPS_JUMP_LABEL_H */

2
arch/mips/include/asm/linkage.h
View File

@@ -2,7 +2,7 @@
#ifndef __ASM_LINKAGE_H
#define __ASM_LINKAGE_H
#ifdef __ASSEMBLY__
#ifdef __ASSEMBLER__
#include <asm/asm.h>
#endif

4
arch/mips/include/asm/mach-generic/spaces.h
View File

@@ -21,13 +21,13 @@
/*
* This gives the physical RAM offset.
*/
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
# if defined(CONFIG_MIPS_AUTO_PFN_OFFSET)
# define PHYS_OFFSET ((unsigned long)PFN_PHYS(ARCH_PFN_OFFSET))
# elif !defined(PHYS_OFFSET)
# define PHYS_OFFSET _AC(0, UL)
# endif
#endif /* __ASSEMBLY__ */
#endif /* __ASSEMBLER__ */
#ifdef CONFIG_32BIT
#define CAC_BASE _AC(0x80000000, UL)

107
arch/mips/include/asm/mach-loongson32/irq.h
View File

@@ -1,107 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
*
* IRQ mappings for Loongson 1
*/
#ifndef __ASM_MACH_LOONGSON32_IRQ_H
#define __ASM_MACH_LOONGSON32_IRQ_H
/*
* CPU core Interrupt Numbers
*/
#define MIPS_CPU_IRQ_BASE 0
#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x))
#define SOFTINT0_IRQ MIPS_CPU_IRQ(0)
#define SOFTINT1_IRQ MIPS_CPU_IRQ(1)
#define INT0_IRQ MIPS_CPU_IRQ(2)
#define INT1_IRQ MIPS_CPU_IRQ(3)
#define INT2_IRQ MIPS_CPU_IRQ(4)
#define INT3_IRQ MIPS_CPU_IRQ(5)
#define INT4_IRQ MIPS_CPU_IRQ(6)
#define TIMER_IRQ MIPS_CPU_IRQ(7) /* cpu timer */
#define MIPS_CPU_IRQS (MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_IRQ_BASE)
/*
* INT0~3 Interrupt Numbers
*/
#define LS1X_IRQ_BASE MIPS_CPU_IRQS
#define LS1X_IRQ(n, x) (LS1X_IRQ_BASE + (n << 5) + (x))
#define LS1X_UART0_IRQ LS1X_IRQ(0, 2)
#if defined(CONFIG_LOONGSON1_LS1B)
#define LS1X_UART1_IRQ LS1X_IRQ(0, 3)
#define LS1X_UART2_IRQ LS1X_IRQ(0, 4)
#define LS1X_UART3_IRQ LS1X_IRQ(0, 5)
#elif defined(CONFIG_LOONGSON1_LS1C)
#define LS1X_UART1_IRQ LS1X_IRQ(0, 4)
#define LS1X_UART2_IRQ LS1X_IRQ(0, 5)
#endif
#define LS1X_CAN0_IRQ LS1X_IRQ(0, 6)
#define LS1X_CAN1_IRQ LS1X_IRQ(0, 7)
#define LS1X_SPI0_IRQ LS1X_IRQ(0, 8)
#define LS1X_SPI1_IRQ LS1X_IRQ(0, 9)
#define LS1X_AC97_IRQ LS1X_IRQ(0, 10)
#define LS1X_DMA0_IRQ LS1X_IRQ(0, 13)
#define LS1X_DMA1_IRQ LS1X_IRQ(0, 14)
#define LS1X_DMA2_IRQ LS1X_IRQ(0, 15)
#if defined(CONFIG_LOONGSON1_LS1C)
#define LS1X_NAND_IRQ LS1X_IRQ(0, 16)
#endif
#define LS1X_PWM0_IRQ LS1X_IRQ(0, 17)
#define LS1X_PWM1_IRQ LS1X_IRQ(0, 18)
#define LS1X_PWM2_IRQ LS1X_IRQ(0, 19)
#define LS1X_PWM3_IRQ LS1X_IRQ(0, 20)
#define LS1X_RTC_INT0_IRQ LS1X_IRQ(0, 21)
#define LS1X_RTC_INT1_IRQ LS1X_IRQ(0, 22)
#define LS1X_RTC_INT2_IRQ LS1X_IRQ(0, 23)
#if defined(CONFIG_LOONGSON1_LS1B)
#define LS1X_TOY_INT0_IRQ LS1X_IRQ(0, 24)
#define LS1X_TOY_INT1_IRQ LS1X_IRQ(0, 25)
#define LS1X_TOY_INT2_IRQ LS1X_IRQ(0, 26)
#define LS1X_RTC_TICK_IRQ LS1X_IRQ(0, 27)
#define LS1X_TOY_TICK_IRQ LS1X_IRQ(0, 28)
#define LS1X_UART4_IRQ LS1X_IRQ(0, 29)
#define LS1X_UART5_IRQ LS1X_IRQ(0, 30)
#elif defined(CONFIG_LOONGSON1_LS1C)
#define LS1X_UART3_IRQ LS1X_IRQ(0, 29)
#define LS1X_ADC_IRQ LS1X_IRQ(0, 30)
#define LS1X_SDIO_IRQ LS1X_IRQ(0, 31)
#endif
#define LS1X_EHCI_IRQ LS1X_IRQ(1, 0)
#define LS1X_OHCI_IRQ LS1X_IRQ(1, 1)
#if defined(CONFIG_LOONGSON1_LS1B)
#define LS1X_GMAC0_IRQ LS1X_IRQ(1, 2)
#define LS1X_GMAC1_IRQ LS1X_IRQ(1, 3)
#elif defined(CONFIG_LOONGSON1_LS1C)
#define LS1X_OTG_IRQ LS1X_IRQ(1, 2)
#define LS1X_GMAC0_IRQ LS1X_IRQ(1, 3)
#define LS1X_CAM_IRQ LS1X_IRQ(1, 4)
#define LS1X_UART4_IRQ LS1X_IRQ(1, 5)
#define LS1X_UART5_IRQ LS1X_IRQ(1, 6)
#define LS1X_UART6_IRQ LS1X_IRQ(1, 7)
#define LS1X_UART7_IRQ LS1X_IRQ(1, 8)
#define LS1X_UART8_IRQ LS1X_IRQ(1, 9)
#define LS1X_UART9_IRQ LS1X_IRQ(1, 13)
#define LS1X_UART10_IRQ LS1X_IRQ(1, 14)
#define LS1X_UART11_IRQ LS1X_IRQ(1, 15)
#define LS1X_I2C0_IRQ LS1X_IRQ(1, 17)
#define LS1X_I2C1_IRQ LS1X_IRQ(1, 18)
#define LS1X_I2C2_IRQ LS1X_IRQ(1, 19)
#endif
#if defined(CONFIG_LOONGSON1_LS1B)
#define INTN 4
#elif defined(CONFIG_LOONGSON1_LS1C)
#define INTN 5
#endif
#define LS1X_IRQS (LS1X_IRQ(INTN, 31) + 1 - LS1X_IRQ_BASE)
#define NR_IRQS (MIPS_CPU_IRQS + LS1X_IRQS)
#endif /* __ASM_MACH_LOONGSON32_IRQ_H */

50
arch/mips/include/asm/mach-loongson32/loongson1.h
View File

@@ -1,50 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
*
* Register mappings for Loongson 1
*/
#ifndef __ASM_MACH_LOONGSON32_LOONGSON1_H
#define __ASM_MACH_LOONGSON32_LOONGSON1_H
#if defined(CONFIG_LOONGSON1_LS1B)
#define DEFAULT_MEMSIZE 64 /* If no memsize provided */
#elif defined(CONFIG_LOONGSON1_LS1C)
#define DEFAULT_MEMSIZE 32
#endif
/* Loongson 1 Register Bases */
#define LS1X_MUX_BASE 0x1fd00420
#define LS1X_INTC_BASE 0x1fd01040
#define LS1X_GPIO0_BASE 0x1fd010c0
#define LS1X_GPIO1_BASE 0x1fd010c4
#define LS1X_DMAC_BASE 0x1fd01160
#define LS1X_CBUS_BASE 0x1fd011c0
#define LS1X_EHCI_BASE 0x1fe00000
#define LS1X_OHCI_BASE 0x1fe08000
#define LS1X_GMAC0_BASE 0x1fe10000
#define LS1X_GMAC1_BASE 0x1fe20000
#define LS1X_UART0_BASE 0x1fe40000
#define LS1X_UART1_BASE 0x1fe44000
#define LS1X_UART2_BASE 0x1fe48000
#define LS1X_UART3_BASE 0x1fe4c000
#define LS1X_CAN0_BASE 0x1fe50000
#define LS1X_CAN1_BASE 0x1fe54000
#define LS1X_I2C0_BASE 0x1fe58000
#define LS1X_I2C1_BASE 0x1fe68000
#define LS1X_I2C2_BASE 0x1fe70000
#define LS1X_PWM0_BASE 0x1fe5c000
#define LS1X_PWM1_BASE 0x1fe5c010
#define LS1X_PWM2_BASE 0x1fe5c020
#define LS1X_PWM3_BASE 0x1fe5c030
#define LS1X_WDT_BASE 0x1fe5c060
#define LS1X_RTC_BASE 0x1fe64000
#define LS1X_AC97_BASE 0x1fe74000
#define LS1X_NAND_BASE 0x1fe78000
#define LS1X_CLK_BASE 0x1fe78030
#include <regs-mux.h>
#endif /* __ASM_MACH_LOONGSON32_LOONGSON1_H */

23
arch/mips/include/asm/mach-loongson32/platform.h
View File

@@ -1,23 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
*/
#ifndef __ASM_MACH_LOONGSON32_PLATFORM_H
#define __ASM_MACH_LOONGSON32_PLATFORM_H
#include <linux/platform_device.h>
extern struct platform_device ls1x_uart_pdev;
extern struct platform_device ls1x_eth0_pdev;
extern struct platform_device ls1x_eth1_pdev;
extern struct platform_device ls1x_ehci_pdev;
extern struct platform_device ls1x_gpio0_pdev;
extern struct platform_device ls1x_gpio1_pdev;
extern struct platform_device ls1x_rtc_pdev;
extern struct platform_device ls1x_wdt_pdev;
void __init ls1x_rtc_set_extclk(struct platform_device *pdev);
void __init ls1x_serial_set_uartclk(struct platform_device *pdev);
#endif /* __ASM_MACH_LOONGSON32_PLATFORM_H */

124
arch/mips/include/asm/mach-loongson32/regs-mux.h
View File

@@ -1,124 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com>
*
* Loongson 1 MUX Register Definitions.
*/
#ifndef __ASM_MACH_LOONGSON32_REGS_MUX_H
#define __ASM_MACH_LOONGSON32_REGS_MUX_H
#define LS1X_MUX_REG(x) \
((void __iomem *)KSEG1ADDR(LS1X_MUX_BASE + (x)))
#define LS1X_MUX_CTRL0 LS1X_MUX_REG(0x0)
#define LS1X_MUX_CTRL1 LS1X_MUX_REG(0x4)
#if defined(CONFIG_LOONGSON1_LS1B)
/* MUX CTRL0 Register Bits */
#define UART0_USE_PWM23 BIT(28)
#define UART0_USE_PWM01 BIT(27)
#define UART1_USE_LCD0_5_6_11 BIT(26)
#define I2C2_USE_CAN1 BIT(25)
#define I2C1_USE_CAN0 BIT(24)
#define NAND3_USE_UART5 BIT(23)
#define NAND3_USE_UART4 BIT(22)
#define NAND3_USE_UART1_DAT BIT(21)
#define NAND3_USE_UART1_CTS BIT(20)
#define NAND3_USE_PWM23 BIT(19)
#define NAND3_USE_PWM01 BIT(18)
#define NAND2_USE_UART5 BIT(17)
#define NAND2_USE_UART4 BIT(16)
#define NAND2_USE_UART1_DAT BIT(15)
#define NAND2_USE_UART1_CTS BIT(14)
#define NAND2_USE_PWM23 BIT(13)
#define NAND2_USE_PWM01 BIT(12)
#define NAND1_USE_UART5 BIT(11)
#define NAND1_USE_UART4 BIT(10)
#define NAND1_USE_UART1_DAT BIT(9)
#define NAND1_USE_UART1_CTS BIT(8)
#define NAND1_USE_PWM23 BIT(7)
#define NAND1_USE_PWM01 BIT(6)
#define GMAC1_USE_UART1 BIT(4)
#define GMAC1_USE_UART0 BIT(3)
#define LCD_USE_UART0_DAT BIT(2)
#define LCD_USE_UART15 BIT(1)
#define LCD_USE_UART0 BIT(0)
/* MUX CTRL1 Register Bits */
#define USB_RESET BIT(31)
#define SPI1_CS_USE_PWM01 BIT(24)
#define SPI1_USE_CAN BIT(23)
#define DISABLE_DDR_CONFSPACE BIT(20)
#define DDR32TO16EN BIT(16)
#define GMAC1_SHUT BIT(13)
#define GMAC0_SHUT BIT(12)
#define USB_SHUT BIT(11)
#define UART1_3_USE_CAN1 BIT(5)
#define UART1_2_USE_CAN0 BIT(4)
#define GMAC1_USE_TXCLK BIT(3)
#define GMAC0_USE_TXCLK BIT(2)
#define GMAC1_USE_PWM23 BIT(1)
#define GMAC0_USE_PWM01 BIT(0)
#elif defined(CONFIG_LOONGSON1_LS1C)
/* SHUT_CTRL Register Bits */
#define UART_SPLIT GENMASK(31, 30)
#define OUTPUT_CLK GENMASK(29, 26)
#define ADC_SHUT BIT(25)
#define SDIO_SHUT BIT(24)
#define DMA2_SHUT BIT(23)
#define DMA1_SHUT BIT(22)
#define DMA0_SHUT BIT(21)
#define SPI1_SHUT BIT(20)
#define SPI0_SHUT BIT(19)
#define I2C2_SHUT BIT(18)
#define I2C1_SHUT BIT(17)
#define I2C0_SHUT BIT(16)
#define AC97_SHUT BIT(15)
#define I2S_SHUT BIT(14)
#define UART3_SHUT BIT(13)
#define UART2_SHUT BIT(12)
#define UART1_SHUT BIT(11)
#define UART0_SHUT BIT(10)
#define CAN1_SHUT BIT(9)
#define CAN0_SHUT BIT(8)
#define ECC_SHUT BIT(7)
#define GMAC_SHUT BIT(6)
#define USBHOST_SHUT BIT(5)
#define USBOTG_SHUT BIT(4)
#define SDRAM_SHUT BIT(3)
#define SRAM_SHUT BIT(2)
#define CAM_SHUT BIT(1)
#define LCD_SHUT BIT(0)
#define UART_SPLIT_SHIFT 30
#define OUTPUT_CLK_SHIFT 26
/* MISC_CTRL Register Bits */
#define USBHOST_RSTN BIT(31)
#define PHY_INTF_SELI GENMASK(30, 28)
#define AC97_EN BIT(25)
#define SDIO_DMA_EN GENMASK(24, 23)
#define ADC_DMA_EN BIT(22)
#define SDIO_USE_SPI1 BIT(17)
#define SDIO_USE_SPI0 BIT(16)
#define SRAM_CTRL GENMASK(15, 0)
#define PHY_INTF_SELI_SHIFT 28
#define SDIO_DMA_EN_SHIFT 23
#define SRAM_CTRL_SHIFT 0
#define LS1X_CBUS_REG(n, x) \
((void __iomem *)KSEG1ADDR(LS1X_CBUS_BASE + (n * 0x04) + (x)))
#define LS1X_CBUS_FIRST(n) LS1X_CBUS_REG(n, 0x00)
#define LS1X_CBUS_SECOND(n) LS1X_CBUS_REG(n, 0x10)
#define LS1X_CBUS_THIRD(n) LS1X_CBUS_REG(n, 0x20)
#define LS1X_CBUS_FOURTHT(n) LS1X_CBUS_REG(n, 0x30)
#define LS1X_CBUS_FIFTHT(n) LS1X_CBUS_REG(n, 0x40)
#endif
#endif /* __ASM_MACH_LOONGSON32_REGS_MUX_H */

4
arch/mips/include/asm/mips-boards/bonito64.h
View File

@@ -21,7 +21,7 @@
#ifndef _ASM_MIPS_BOARDS_BONITO64_H
#define _ASM_MIPS_BOARDS_BONITO64_H
#ifdef __ASSEMBLY__
#ifdef __ASSEMBLER__
/* offsets from base register */
#define BONITO(x) (x)
@@ -36,7 +36,7 @@ extern unsigned long _pcictrl_bonito_pcicfg;
#define BONITO(x) *(volatile u32 *)(_pcictrl_bonito + (x))
#endif /* __ASSEMBLY__ */
#endif /* __ASSEMBLER__ */
#define BONITO_BOOT_BASE 0x1fc00000

6
arch/mips/include/asm/mipsmtregs.h
View File

@@ -10,7 +10,7 @@
#include <asm/mipsregs.h>
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
/*
* C macros
@@ -176,7 +176,7 @@
/* TCHalt */
#define TCHALT_H (_ULCAST_(1))
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
static inline unsigned core_nvpes(void)
{
@@ -469,6 +469,6 @@ do { \
__BUILD_SET_C0(mvpcontrol)
#endif /* Not __ASSEMBLY__ */
#endif /* Not __ASSEMBLER__ */
#endif

6
arch/mips/include/asm/mipsregs.h
View File

@@ -32,7 +32,7 @@
/*
* Configure language
*/
#ifdef __ASSEMBLY__
#ifdef __ASSEMBLER__
#define _ULCAST_
#define _U64CAST_
#else
@@ -1346,7 +1346,7 @@
#define FPU_CSR_RD 0x3 /* towards -Infinity */
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
/*
* Macros for handling the ISA mode bit for MIPS16 and microMIPS.
@@ -3095,6 +3095,6 @@ static inline unsigned int get_ebase_cpunum(void)
return read_c0_ebase() & MIPS_EBASE_CPUNUM;
}
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
#endif /* _ASM_MIPSREGS_H */

4
arch/mips/include/asm/msa.h
View File

@@ -8,7 +8,7 @@
#include <asm/mipsregs.h>
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#include <asm/inst.h>
@@ -218,7 +218,7 @@ __BUILD_MSA_CTL_REG(request, 5)
__BUILD_MSA_CTL_REG(map, 6)
__BUILD_MSA_CTL_REG(unmap, 7)
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
#define MSA_IR 0
#define MSA_CSR 1

4
arch/mips/include/asm/pci/bridge.h
View File

@@ -43,7 +43,7 @@
* Bridge address map
*/
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#define ATE_V 0x01
#define ATE_CO 0x02
@@ -288,7 +288,7 @@ struct bridge_err_cmdword {
};
#define berr_field berr_un.berr_st
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
/*
* The values of these macros can and should be crosschecked

6
arch/mips/include/asm/pm.h
View File

@@ -8,7 +8,7 @@
#ifndef __ASM_PM_H
#define __ASM_PM_H
#ifdef __ASSEMBLY__
#ifdef __ASSEMBLER__
#include <asm/asm-offsets.h>
#include <asm/asm.h>
@@ -130,7 +130,7 @@
RESUME_RESTORE_REGS_RETURN
.endm
#else /* __ASSEMBLY__ */
#else /* __ASSEMBLER__ */
/**
* struct mips_static_suspend_state - Core saved CPU state across S2R.
@@ -150,6 +150,6 @@ struct mips_static_suspend_state {
unsigned long sp;
};
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
#endif /* __ASM_PM_HELPERS_H */

2
arch/mips/include/asm/prefetch.h
View File

@@ -42,7 +42,7 @@
#define Pref_WriteBackInvalidate 25
#define Pref_PrepareForStore 30
#ifdef __ASSEMBLY__
#ifdef __ASSEMBLER__
.macro __pref hint addr
#ifdef CONFIG_CPU_HAS_PREFETCH

4
arch/mips/include/asm/regdef.h
View File

@@ -103,7 +103,7 @@
#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
#ifdef __ASSEMBLY__
#ifdef __ASSEMBLER__
#if _MIPS_SIM == _MIPS_SIM_ABI32
/*
@@ -192,6 +192,6 @@
#define ra $31 /* return address */
#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
#endif /* __ASSEMBLY__ */
#endif /* __ASSEMBLER__ */
#endif /* _ASM_REGDEF_H */

4
arch/mips/include/asm/sibyte/board.h
View File

@@ -19,7 +19,7 @@
#include <asm/sibyte/bigsur.h>
#endif
#ifdef __ASSEMBLY__
#ifdef __ASSEMBLER__
#ifdef LEDS_PHYS
#define setleds(t0, t1, c0, c1, c2, c3) \
@@ -46,6 +46,6 @@ extern void setleds(char *str);
#define setleds(s) do { } while (0)
#endif /* LEDS_PHYS */
#endif /* __ASSEMBLY__ */
#endif /* __ASSEMBLER__ */
#endif /* _SIBYTE_BOARD_H */

2
arch/mips/include/asm/sibyte/sb1250.h
View File

@@ -19,7 +19,7 @@
#define SB1250_DUART_MINOR_BASE 64
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#include <asm/addrspace.h>

6
arch/mips/include/asm/sibyte/sb1250_defs.h
View File

@@ -199,7 +199,7 @@
* Note: you'll need to define uint32_t and uint64_t in your headers.
*/
#if !defined(__ASSEMBLY__)
#if !defined(__ASSEMBLER__)
#define _SB_MAKE64(x) ((uint64_t)(x))
#define _SB_MAKE32(x) ((uint32_t)(x))
#else
@@ -238,9 +238,9 @@
*/
#if defined(__mips64) && !defined(__ASSEMBLY__)
#if defined(__mips64) && !defined(__ASSEMBLER__)
#define SBWRITECSR(csr, val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val)
#define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr)))
#endif /* __ASSEMBLY__ */
#endif /* __ASSEMBLER__ */
#endif

6
arch/mips/include/asm/smp-cps.h
View File

@@ -9,7 +9,7 @@
#define CPS_ENTRY_PATCH_INSNS 6
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
struct vpe_boot_config {
unsigned long pc;
@@ -55,9 +55,9 @@ static inline bool mips_cps_smp_in_use(void) { return false; }
#endif /* !CONFIG_MIPS_CPS */
#else /* __ASSEMBLY__ */
#else /* __ASSEMBLER__ */
.extern mips_cps_bootcfg;
#endif /* __ASSEMBLY__ */
#endif /* __ASSEMBLER__ */
#endif /* __MIPS_ASM_SMP_CPS_H__ */

18
arch/mips/include/asm/sn/addrs.h
View File

@@ -10,10 +10,10 @@
#define _ASM_SN_ADDRS_H
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#include <linux/smp.h>
#include <linux/types.h>
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
#include <asm/addrspace.h>
#include <asm/sn/kldir.h>
@@ -25,15 +25,15 @@
#endif
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#define UINT64_CAST (unsigned long)
#else /* __ASSEMBLY__ */
#else /* __ASSEMBLER__ */
#define UINT64_CAST
#endif /* __ASSEMBLY__ */
#endif /* __ASSEMBLER__ */
#define NASID_GET_META(_n) ((_n) >> NASID_LOCAL_BITS)
@@ -254,7 +254,7 @@
#define LOCAL_HUB_ADDR(_x) (IALIAS_BASE + (_x))
#define REMOTE_HUB_ADDR(_n, _x) ((NODE_SWIN_BASE(_n, 1) + 0x800000 + (_x)))
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#define LOCAL_HUB_PTR(_x) ((u64 *)LOCAL_HUB_ADDR((_x)))
#define REMOTE_HUB_PTR(_n, _x) ((u64 *)REMOTE_HUB_ADDR((_n), (_x)))
@@ -265,7 +265,7 @@
#define REMOTE_HUB_S(_n, _r, _d) __raw_writeq((_d), \
REMOTE_HUB_PTR((_n), (_r)))
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
/*
* Software structure locations -- permanently fixed
@@ -315,7 +315,7 @@
#define KLI_KERN_XP 8
#define KLI_KERN_PARTID 9
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#define KLD_BASE(nasid) ((kldir_ent_t *) KLDIR_ADDR(nasid))
#define KLD_LAUNCH(nasid) (KLD_BASE(nasid) + KLI_LAUNCH)
@@ -371,7 +371,7 @@
#define KERN_VARS_ADDR(nasid) KLD_KERN_VARS(nasid)->pointer
#define KERN_VARS_SIZE(nasid) KLD_KERN_VARS(nasid)->size
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
#endif /* _ASM_SN_ADDRS_H */

4
arch/mips/include/asm/sn/gda.h
View File

@@ -39,7 +39,7 @@
#define G_PARTIDOFF 40
#define G_TABLEOFF 128
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
typedef struct gda {
u32 g_magic; /* GDA magic number */
@@ -63,7 +63,7 @@ typedef struct gda {
#define GDA ((gda_t*) GDA_ADDR(get_nasid()))
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
/*
* Define: PART_GDA_VERSION
* Purpose: Define the minimum version of the GDA required, lower

4
arch/mips/include/asm/sn/kldir.h
View File

@@ -15,7 +15,7 @@
#define KLDIR_ENT_SIZE 0x40
#define KLDIR_MAX_ENTRIES (0x400 / 0x40)
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
typedef struct kldir_ent_s {
u64 magic; /* Indicates validity of entry */
off_t offset; /* Offset from start of node space */
@@ -27,7 +27,7 @@ typedef struct kldir_ent_s {
/* NOTE: These 16 bytes are used in the Partition KLDIR
entry to store partition info. Refer to klpart.h for this. */
} kldir_ent_t;
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
#ifdef CONFIG_SGI_IP27
#include <asm/sn/sn0/kldir.h>

4
arch/mips/include/asm/sn/klkernvars.h
View File

@@ -12,7 +12,7 @@
#define KV_MAGIC 0x5f4b565f
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#include <asm/sn/types.h>
@@ -24,6 +24,6 @@ typedef struct kern_vars_s {
unsigned long kv_rw_baseaddr;
} kern_vars_t;
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
#endif /* __ASM_SN_KLKERNVARS_H */

4
arch/mips/include/asm/sn/launch.h
View File

@@ -59,7 +59,7 @@
* clears the BUSY flag after control is returned to it.
*/
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
typedef int launch_state_t;
typedef void (*launch_proc_t)(u64 call_parm);
@@ -101,6 +101,6 @@ typedef struct launch_s {
#define LAUNCH_FLASH (*(void (*)(void)) \
IP27PROM_FLASHLEDS)
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
#endif /* _ASM_SN_LAUNCH_H */

8
arch/mips/include/asm/sn/nmi.h
View File

@@ -48,7 +48,7 @@
*
*/
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
typedef struct nmi_s {
volatile unsigned long magic; /* Magic number */
@@ -59,13 +59,13 @@ typedef struct nmi_s {
volatile unsigned long gmaster; /* Flag true only on global master*/
} nmi_t;
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
/* Following definitions are needed both in the prom & the kernel
* to identify the format of the nmi cpu register save area in the
* low memory on each node.
*/
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
struct reg_struct {
unsigned long gpr[32];
@@ -78,7 +78,7 @@ struct reg_struct {
unsigned long nmi_sr;
};
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
/* These are the assembly language offsets into the reg_struct structure */

14
arch/mips/include/asm/sn/sn0/addrs.h
View File

@@ -84,15 +84,15 @@
#define NASID_GET(_pa) (int) ((UINT64_CAST (_pa) >> \
NASID_SHFT) & NASID_BITMASK)
#if !defined(__ASSEMBLY__)
#if !defined(__ASSEMBLER__)
#define NODE_SWIN_BASE(nasid, widget) \
((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \
: RAW_NODE_SWIN_BASE(nasid, widget))
#else /* __ASSEMBLY__ */
#else /* __ASSEMBLER__ */
#define NODE_SWIN_BASE(nasid, widget) \
(NODE_IO_BASE(nasid) + (UINT64_CAST(widget) << SWIN_SIZE_BITS))
#endif /* __ASSEMBLY__ */
#endif /* __ASSEMBLER__ */
/*
* The following definitions pertain to the IO special address
@@ -139,11 +139,11 @@
/* Turn on sable logging for the processors whose bits are set. */
#define SABLE_LOG_TRIGGER(_map)
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#define KERN_NMI_ADDR(nasid, slice) \
TO_NODE_UNCAC((nasid), IP27_NMI_KREGS_OFFSET + \
(IP27_NMI_KREGS_CPU_SIZE * (slice)))
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
#ifdef PROM
@@ -248,7 +248,7 @@
#define KL_UART_DATA LOCAL_HUB_ADDR(MD_UREG0_1) /* UART data reg */
#define KL_I2C_REG MD_UREG0_0 /* I2C reg */
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
/* Address 0x400 to 0x1000 ualias points to cache error eframe + misc
* CACHE_ERR_SP_PTR could either contain an address to the stack, or
@@ -266,7 +266,7 @@
#define CACHE_ERR_SP (CACHE_ERR_SP_PTR - 16)
#define CACHE_ERR_AREA_SIZE (ARCS_SPB_OFFSET - CACHE_ERR_EFRAME)
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
#define _ARCSPROM

2
arch/mips/include/asm/sn/sn0/hub.h
View File

@@ -37,7 +37,7 @@
#define UATTR_MSPEC 2
#define UATTR_UNCAC 3
#ifdef __ASSEMBLY__
#ifdef __ASSEMBLER__
/*
* Returns the local nasid into res.
*/

36
arch/mips/include/asm/sn/sn0/hubio.h
View File

@@ -169,7 +169,7 @@
/*
* The IO LLP control status register and widget control register
*/
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
typedef union hubii_wid_u {
u64 wid_reg_value;
@@ -292,7 +292,7 @@ typedef union io_perf_cnt {
} perf_cnt_bits;
} io_perf_cnt_t;
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
#define LNK_STAT_WORKING 0x2
@@ -440,7 +440,7 @@ typedef union io_perf_cnt {
/*
* Fields in CRB Register A
*/
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
typedef union icrba_u {
u64 reg_value;
struct {
@@ -486,7 +486,7 @@ typedef union h1_icrba_u {
#define ICRBN_A_CERR_SHFT 54
#define ICRBN_A_ERR_MASK 0x3ff
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
#define IIO_ICRB_ADDR_SHFT 2 /* Shift to get proper address */
@@ -509,7 +509,7 @@ typedef union h1_icrba_u {
/*
* Fields in CRB Register B
*/
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
typedef union icrbb_u {
u64 reg_value;
struct {
@@ -608,7 +608,7 @@ typedef union h1_icrbb_u {
#define b_imsg icrbb_field_s.imsg
#define b_initiator icrbb_field_s.initiator
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
/*
* values for field xtsize
@@ -666,7 +666,7 @@ typedef union h1_icrbb_u {
* Fields in CRB Register C
*/
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
typedef union icrbc_s {
u64 reg_value;
@@ -698,13 +698,13 @@ typedef union icrbc_s {
#define c_barrop icrbc_field_s.barrop
#define c_doresp icrbc_field_s.doresp
#define c_gbr icrbc_field_s.gbr
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
/*
* Fields in CRB Register D
*/
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
typedef union icrbd_s {
u64 reg_value;
struct {
@@ -737,7 +737,7 @@ typedef union hubii_ifdr_u {
} hi_ifdr_fields;
} hubii_ifdr_t;
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
/*
* Hardware designed names for the BTE control registers.
@@ -784,7 +784,7 @@ typedef union hubii_ifdr_u {
* IO PIO Read Table Entry format
*/
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
typedef union iprte_a {
u64 entry;
@@ -806,7 +806,7 @@ typedef union iprte_a {
#define iprte_init iprte_fields.initiator
#define iprte_addr iprte_fields.addr
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
#define IPRTE_ADDRSHFT 3
@@ -814,7 +814,7 @@ typedef union iprte_a {
* Hub IIO PRB Register format.
*/
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
/*
* Note: Fields bnakctr, anakctr, xtalkctrmode, ovflow fields are
* "Status" fields, and should only be used in case of clean up after errors.
@@ -846,7 +846,7 @@ typedef union iprb_u {
#define iprb_anakctr iprb_fields_s.anakctr
#define iprb_xtalkctr iprb_fields_s.xtalkctr
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
/*
* values for mode field in iprb_t.
@@ -861,7 +861,7 @@ typedef union iprb_u {
/*
* IO CRB entry C_A to E_A : Partial (cache) CRBS
*/
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
typedef union icrbp_a {
u64 ip_reg; /* the entire register value */
struct {
@@ -895,7 +895,7 @@ typedef union icrbp_a {
} ip_fmt;
} icrbp_a_t;
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
/*
* A couple of defines to go with the above structure.
@@ -903,7 +903,7 @@ typedef union icrbp_a {
#define ICRBP_A_CERR_SHFT 54
#define ICRBP_A_ERR_MASK 0x3ff
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
typedef union hubii_idsr {
u64 iin_reg;
struct {
@@ -917,7 +917,7 @@ typedef union hubii_idsr {
level : 7;
} iin_fmt;
} hubii_idsr_t;
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
/*
* IO BTE Length/Status (IIO_IBLS) register bit field definitions

4
arch/mips/include/asm/sn/sn0/hubmd.h
View File

@@ -423,7 +423,7 @@
* Operations on page migration threshold register
*/
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
/*
* LED register macros
@@ -735,7 +735,7 @@ typedef union md_perf_cnt {
} md_perf_cnt_t;
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
#define DIR_ERROR_VALID_MASK 0xe000000000000000

6
arch/mips/include/asm/sn/sn0/hubni.h
View File

@@ -11,7 +11,7 @@
#ifndef _ASM_SGI_SN0_HUBNI_H
#define _ASM_SGI_SN0_HUBNI_H
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#include <linux/types.h>
#endif
@@ -226,7 +226,7 @@
#define NLT_EXIT_PORT_MASK (UINT64_CAST 0xf)
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
typedef union hubni_port_error_u {
u64 nipe_reg_value;
@@ -258,6 +258,6 @@ static inline int get_region_shift(void)
return NASID_TO_COARSEREG_SHFT;
}
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
#endif /* _ASM_SGI_SN0_HUBNI_H */

4
arch/mips/include/asm/sn/sn0/hubpi.h
View File

@@ -306,7 +306,7 @@
#define ERR_STACK_SIZE_BYTES(_sz) \
((_sz) ? (PI_MIN_STACK_SIZE << ((_sz) - 1)) : 0)
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
/*
* format of error stack and error status registers.
*/
@@ -359,7 +359,7 @@ typedef union pi_err_stat1 {
typedef u64 rtc_time_t;
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
/* Bits in PI_SYSAD_ERRCHK_EN */

2
arch/mips/include/asm/sn/types.h
View File

@@ -11,7 +11,7 @@
#include <linux/types.h>
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
typedef unsigned long cpuid_t;
typedef signed short nasid_t; /* node id in numa-as-id space */

2
arch/mips/include/asm/sync.h
View File

@@ -193,7 +193,7 @@
* Preprocessor magic to expand macros used as arguments before we insert them
* into assembly code.
*/
#ifdef __ASSEMBLY__
#ifdef __ASSEMBLER__
# define ___SYNC(type, reason, else) \
____SYNC(type, reason, else)
#else

4
arch/mips/include/asm/thread_info.h
View File

@@ -11,7 +11,7 @@
#ifdef __KERNEL__
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#include <asm/processor.h>
@@ -73,7 +73,7 @@ static inline struct thread_info *current_thread_info(void)
register unsigned long current_stack_pointer __asm__("sp");
#endif
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
/* thread information allocation */
#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_32BIT)

4
arch/mips/include/asm/unistd.h
View File

@@ -29,7 +29,7 @@
#define NR_syscalls (__NR_O32_Linux + __NR_O32_Linux_syscalls)
#endif
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#define __ARCH_WANT_NEW_STAT
#define __ARCH_WANT_OLD_READDIR
@@ -62,6 +62,6 @@
/* whitelists for checksyscalls */
#define __IGNORE_fadvise64_64
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
#endif /* _ASM_UNISTD_H */

4
arch/mips/include/asm/vdso/gettimeofday.h
View File

@@ -11,7 +11,7 @@
#ifndef __ASM_VDSO_GETTIMEOFDAY_H
#define __ASM_VDSO_GETTIMEOFDAY_H
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#include <asm/vdso/vdso.h>
#include <asm/clocksource.h>
@@ -215,6 +215,6 @@ static __always_inline const struct vdso_time_data *__arch_get_vdso_u_time_data(
}
#define __arch_get_vdso_u_time_data __arch_get_vdso_u_time_data
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
#endif /* __ASM_VDSO_GETTIMEOFDAY_H */

4
arch/mips/include/asm/vdso/processor.h
View File

@@ -5,7 +5,7 @@
#ifndef __ASM_VDSO_PROCESSOR_H
#define __ASM_VDSO_PROCESSOR_H
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#ifdef CONFIG_CPU_LOONGSON64
/*
@@ -22,6 +22,6 @@
#define cpu_relax() barrier()
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ASSEMBLER__ */
#endif /* __ASM_VDSO_PROCESSOR_H */

4
arch/mips/include/asm/vdso/vdso.h
View File

@@ -9,7 +9,7 @@
#define __VDSO_PAGES 4
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#include <asm/asm.h>
#include <asm/vdso.h>
@@ -69,4 +69,4 @@ static inline void __iomem *get_gic(const struct vdso_time_data *data)
#endif /* CONFIG_CLKSRC_MIPS_GIC */
#endif /* __ASSEMBLY__ */
#endif /* __ASSEMBLER__ */

4
arch/mips/include/asm/vdso/vsyscall.h
View File

@@ -4,13 +4,13 @@
#include <asm/page.h>
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
#include <vdso/datapage.h>
/* The asm-generic header needs to be included after the definitions above */
#include <asm-generic/vdso/vsyscall.h>
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
#endif /* __ASM_VDSO_VSYSCALL_H */

4
arch/mips/include/asm/xtalk/xtalk.h
View File

@@ -12,7 +12,7 @@
#ifndef _ASM_XTALK_XTALK_H
#define _ASM_XTALK_XTALK_H
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
/*
* User-level device driver visible types
*/
@@ -47,6 +47,6 @@ typedef struct xtalk_piomap_s *xtalk_piomap_t;
#define XIO_PORT(x) ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT))
#define XIO_PACK(p, o) ((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS))
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
#endif /* _ASM_XTALK_XTALK_H */

4
arch/mips/include/asm/xtalk/xwidget.h
View File

@@ -203,7 +203,7 @@ static const struct widget_ident __initconst widget_idents[] = {
* widget target flush register are widget dependent thus will not be
* defined here
*/
#ifndef __ASSEMBLY__
#ifndef __ASSEMBLER__
typedef u32 widgetreg_t;
/* widget configuration registers */
@@ -274,6 +274,6 @@ typedef struct xwidget_hwid_s {
((hwid2)->mfg_num == XWIDGET_MFG_NUM_NONE) || \
((hwid1)->mfg_num == (hwid2)->mfg_num)))
#endif /* !__ASSEMBLY__ */
#endif /* !__ASSEMBLER__ */
#endif /* _ASM_XTALK_XWIDGET_H */

6
arch/mips/kernel/cpu-probe.c
View File

@@ -1288,14 +1288,14 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
set_cpu_asid_mask(c, MIPS_ENTRYHI_ASID);
c->writecombine = _CACHE_UNCACHED_ACCELERATED;
break;
case PRID_IMP_LOONGSON_32: /* Loongson-1 */
case PRID_IMP_LOONGSON_32:
decode_configs(c);
c->cputype = CPU_LOONGSON32;
switch (c->processor_id & PRID_REV_MASK) {
case PRID_REV_LOONGSON1B:
__cpu_name[cpu] = "Loongson 1B";
case PRID_REV_LOONGSON1:
__cpu_name[cpu] = "ICT Loongson-1";
break;
}

2
arch/mips/lantiq/xway/sysctrl.c
View File

@@ -485,7 +485,7 @@ void __init ltq_soc_init(void)
/* add our generic xway clocks */
clkdev_add_pmu("10000000.fpi", NULL, 0, 0, PMU_FPI);
clkdev_add_pmu("1e100a00.gptu", NULL, 1, 0, PMU_GPT);
clkdev_add_pmu("1e100bb0.stp", NULL, 1, 0, PMU_STP);
clkdev_add_pmu("1e100bb0.gpio", NULL, 1, 0, PMU_STP);
clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1);
clkdev_add_pmu("1e104100.dma", NULL, 1, 0, PMU_DMA);
clkdev_add_pmu("1e100800.spi", NULL, 1, 0, PMU_SPI);

43
arch/mips/loongson32/Kconfig
View File

@@ -1,38 +1,9 @@
# SPDX-License-Identifier: GPL-2.0
if MACH_LOONGSON32
choice
prompt "Machine Type"
config LOONGSON1_LS1B
bool "Loongson LS1B board"
select CEVT_R4K if !MIPS_EXTERNAL_TIMER
select CSRC_R4K if !MIPS_EXTERNAL_TIMER
select SYS_HAS_CPU_LOONGSON1B
select DMA_NONCOHERENT
select BOOT_ELF32
select IRQ_MIPS_CPU
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_HAS_EARLY_PRINTK
select USE_GENERIC_EARLY_PRINTK_8250
select COMMON_CLK
config LOONGSON1_LS1C
bool "Loongson LS1C board"
select CEVT_R4K if !MIPS_EXTERNAL_TIMER
select CSRC_R4K if !MIPS_EXTERNAL_TIMER
select SYS_HAS_CPU_LOONGSON1C
select DMA_NONCOHERENT
select BOOT_ELF32
select IRQ_MIPS_CPU
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_HAS_EARLY_PRINTK
select USE_GENERIC_EARLY_PRINTK_8250
select COMMON_CLK
endchoice
endif # MACH_LOONGSON32
config BUILTIN_DTB_NAME
string "Source file for built-in DTB"
depends on BUILTIN_DTB
help
Base name (without suffix, relative to arch/mips/boot/dts/loongson)
for the DTS file that will be used to produce the DTB linked into
the kernel.

17
arch/mips/loongson32/Makefile
View File

@@ -1,18 +1 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# Common code for all Loongson 1 based systems
#
obj-$(CONFIG_MACH_LOONGSON32) += common/
#
# Loongson LS1B board
#
obj-$(CONFIG_LOONGSON1_LS1B) += ls1b/
#
# Loongson LS1C board
#
obj-$(CONFIG_LOONGSON1_LS1C) += ls1c/

1
arch/mips/loongson32/Platform
View File

@@ -1,3 +1,2 @@
cflags-$(CONFIG_CPU_LOONGSON32) += -march=mips32r2 -Wa,--trap
cflags-$(CONFIG_MACH_LOONGSON32) += -I$(srctree)/arch/mips/include/asm/mach-loongson32
load-$(CONFIG_CPU_LOONGSON32) += 0xffffffff80200000

6
arch/mips/loongson32/common/Makefile
View File

@@ -1,6 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# Makefile for common code of loongson1 based machines.
#
obj-y += time.o irq.o platform.o prom.o setup.o

191
arch/mips/loongson32/common/irq.c
View File

@@ -1,191 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
*/
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <asm/irq_cpu.h>
#include <loongson1.h>
#include <irq.h>
#define LS1X_INTC_REG(n, x) \
((void __iomem *)KSEG1ADDR(LS1X_INTC_BASE + (n * 0x18) + (x)))
#define LS1X_INTC_INTISR(n) LS1X_INTC_REG(n, 0x0)
#define LS1X_INTC_INTIEN(n) LS1X_INTC_REG(n, 0x4)
#define LS1X_INTC_INTSET(n) LS1X_INTC_REG(n, 0x8)
#define LS1X_INTC_INTCLR(n) LS1X_INTC_REG(n, 0xc)
#define LS1X_INTC_INTPOL(n) LS1X_INTC_REG(n, 0x10)
#define LS1X_INTC_INTEDGE(n) LS1X_INTC_REG(n, 0x14)
static void ls1x_irq_ack(struct irq_data *d)
{
unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
__raw_writel(__raw_readl(LS1X_INTC_INTCLR(n))
| (1 << bit), LS1X_INTC_INTCLR(n));
}
static void ls1x_irq_mask(struct irq_data *d)
{
unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
__raw_writel(__raw_readl(LS1X_INTC_INTIEN(n))
& ~(1 << bit), LS1X_INTC_INTIEN(n));
}
static void ls1x_irq_mask_ack(struct irq_data *d)
{
unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
__raw_writel(__raw_readl(LS1X_INTC_INTIEN(n))
& ~(1 << bit), LS1X_INTC_INTIEN(n));
__raw_writel(__raw_readl(LS1X_INTC_INTCLR(n))
| (1 << bit), LS1X_INTC_INTCLR(n));
}
static void ls1x_irq_unmask(struct irq_data *d)
{
unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
__raw_writel(__raw_readl(LS1X_INTC_INTIEN(n))
| (1 << bit), LS1X_INTC_INTIEN(n));
}
static int ls1x_irq_settype(struct irq_data *d, unsigned int type)
{
unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
switch (type) {
case IRQ_TYPE_LEVEL_HIGH:
__raw_writel(__raw_readl(LS1X_INTC_INTPOL(n))
| (1 << bit), LS1X_INTC_INTPOL(n));
__raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n))
& ~(1 << bit), LS1X_INTC_INTEDGE(n));
break;
case IRQ_TYPE_LEVEL_LOW:
__raw_writel(__raw_readl(LS1X_INTC_INTPOL(n))
& ~(1 << bit), LS1X_INTC_INTPOL(n));
__raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n))
& ~(1 << bit), LS1X_INTC_INTEDGE(n));
break;
case IRQ_TYPE_EDGE_RISING:
__raw_writel(__raw_readl(LS1X_INTC_INTPOL(n))
| (1 << bit), LS1X_INTC_INTPOL(n));
__raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n))
| (1 << bit), LS1X_INTC_INTEDGE(n));
break;
case IRQ_TYPE_EDGE_FALLING:
__raw_writel(__raw_readl(LS1X_INTC_INTPOL(n))
& ~(1 << bit), LS1X_INTC_INTPOL(n));
__raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n))
| (1 << bit), LS1X_INTC_INTEDGE(n));
break;
case IRQ_TYPE_EDGE_BOTH:
__raw_writel(__raw_readl(LS1X_INTC_INTPOL(n))
& ~(1 << bit), LS1X_INTC_INTPOL(n));
__raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n))
| (1 << bit), LS1X_INTC_INTEDGE(n));
break;
case IRQ_TYPE_NONE:
break;
default:
return -EINVAL;
}
return 0;
}
static struct irq_chip ls1x_irq_chip = {
.name = "LS1X-INTC",
.irq_ack = ls1x_irq_ack,
.irq_mask = ls1x_irq_mask,
.irq_mask_ack = ls1x_irq_mask_ack,
.irq_unmask = ls1x_irq_unmask,
.irq_set_type = ls1x_irq_settype,
};
static void ls1x_irq_dispatch(int n)
{
u32 int_status, irq;
/* Get pending sources, masked by current enables */
int_status = __raw_readl(LS1X_INTC_INTISR(n)) &
__raw_readl(LS1X_INTC_INTIEN(n));
if (int_status) {
irq = LS1X_IRQ(n, __ffs(int_status));
do_IRQ(irq);
}
}
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending;
pending = read_c0_cause() & read_c0_status() & ST0_IM;
if (pending & CAUSEF_IP7)
do_IRQ(TIMER_IRQ);
else if (pending & CAUSEF_IP2)
ls1x_irq_dispatch(0); /* INT0 */
else if (pending & CAUSEF_IP3)
ls1x_irq_dispatch(1); /* INT1 */
else if (pending & CAUSEF_IP4)
ls1x_irq_dispatch(2); /* INT2 */
else if (pending & CAUSEF_IP5)
ls1x_irq_dispatch(3); /* INT3 */
else if (pending & CAUSEF_IP6)
ls1x_irq_dispatch(4); /* INT4 */
else
spurious_interrupt();
}
static void __init ls1x_irq_init(int base)
{
int n;
/* Disable interrupts and clear pending,
* setup all IRQs as high level triggered
*/
for (n = 0; n < INTN; n++) {
__raw_writel(0x0, LS1X_INTC_INTIEN(n));
__raw_writel(0xffffffff, LS1X_INTC_INTCLR(n));
__raw_writel(0xffffffff, LS1X_INTC_INTPOL(n));
/* set DMA0, DMA1 and DMA2 to edge trigger */
__raw_writel(n ? 0x0 : 0xe000, LS1X_INTC_INTEDGE(n));
}
for (n = base; n < NR_IRQS; n++) {
irq_set_chip_and_handler(n, &ls1x_irq_chip,
handle_level_irq);
}
if (request_irq(INT0_IRQ, no_action, IRQF_NO_THREAD, "cascade", NULL))
pr_err("Failed to request irq %d (cascade)\n", INT0_IRQ);
if (request_irq(INT1_IRQ, no_action, IRQF_NO_THREAD, "cascade", NULL))
pr_err("Failed to request irq %d (cascade)\n", INT1_IRQ);
if (request_irq(INT2_IRQ, no_action, IRQF_NO_THREAD, "cascade", NULL))
pr_err("Failed to request irq %d (cascade)\n", INT2_IRQ);
if (request_irq(INT3_IRQ, no_action, IRQF_NO_THREAD, "cascade", NULL))
pr_err("Failed to request irq %d (cascade)\n", INT3_IRQ);
#if defined(CONFIG_LOONGSON1_LS1C)
if (request_irq(INT4_IRQ, no_action, IRQF_NO_THREAD, "cascade", NULL))
pr_err("Failed to request irq %d (cascade)\n", INT4_IRQ);
#endif
}
void __init arch_init_irq(void)
{
mips_cpu_irq_init();
ls1x_irq_init(LS1X_IRQ_BASE);
}

285
arch/mips/loongson32/common/platform.c
View File

@@ -1,285 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2011-2016 Zhang, Keguang <keguang.zhang@gmail.com>
*/
#include <linux/clk.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/mtd/partitions.h>
#include <linux/sizes.h>
#include <linux/phy.h>
#include <linux/serial_8250.h>
#include <linux/stmmac.h>
#include <linux/usb/ehci_pdriver.h>
#include <platform.h>
#include <loongson1.h>
/* 8250/16550 compatible UART */
#define LS1X_UART(_id) \
{ \
.mapbase = LS1X_UART ## _id ## _BASE, \
.irq = LS1X_UART ## _id ## _IRQ, \
.iotype = UPIO_MEM, \
.flags = UPF_IOREMAP | UPF_FIXED_TYPE, \
.type = PORT_16550A, \
}
static struct plat_serial8250_port ls1x_serial8250_pdata[] = {
LS1X_UART(0),
LS1X_UART(1),
LS1X_UART(2),
LS1X_UART(3),
{},
};
struct platform_device ls1x_uart_pdev = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = ls1x_serial8250_pdata,
},
};
void __init ls1x_serial_set_uartclk(struct platform_device *pdev)
{
struct clk *clk;
struct plat_serial8250_port *p;
clk = clk_get(&pdev->dev, pdev->name);
if (IS_ERR(clk)) {
pr_err("unable to get %s clock, err=%ld",
pdev->name, PTR_ERR(clk));
return;
}
clk_prepare_enable(clk);
for (p = pdev->dev.platform_data; p->flags != 0; ++p)
p->uartclk = clk_get_rate(clk);
}
/* Synopsys Ethernet GMAC */
static struct stmmac_mdio_bus_data ls1x_mdio_bus_data = {
.phy_mask = 0,
};
static struct stmmac_dma_cfg ls1x_eth_dma_cfg = {
.pbl = 1,
};
int ls1x_eth_mux_init(struct platform_device *pdev, void *priv)
{
struct plat_stmmacenet_data *plat_dat = NULL;
u32 val;
val = __raw_readl(LS1X_MUX_CTRL1);
#if defined(CONFIG_LOONGSON1_LS1B)
plat_dat = dev_get_platdata(&pdev->dev);
if (plat_dat->bus_id) {
__raw_writel(__raw_readl(LS1X_MUX_CTRL0) | GMAC1_USE_UART1 |
GMAC1_USE_UART0, LS1X_MUX_CTRL0);
switch (plat_dat->phy_interface) {
case PHY_INTERFACE_MODE_RGMII:
val &= ~(GMAC1_USE_TXCLK | GMAC1_USE_PWM23);
break;
case PHY_INTERFACE_MODE_MII:
val |= (GMAC1_USE_TXCLK | GMAC1_USE_PWM23);
break;
default:
pr_err("unsupported mii mode %d\n",
plat_dat->phy_interface);
return -ENOTSUPP;
}
val &= ~GMAC1_SHUT;
} else {
switch (plat_dat->phy_interface) {
case PHY_INTERFACE_MODE_RGMII:
val &= ~(GMAC0_USE_TXCLK | GMAC0_USE_PWM01);
break;
case PHY_INTERFACE_MODE_MII:
val |= (GMAC0_USE_TXCLK | GMAC0_USE_PWM01);
break;
default:
pr_err("unsupported mii mode %d\n",
plat_dat->phy_interface);
return -ENOTSUPP;
}
val &= ~GMAC0_SHUT;
}
__raw_writel(val, LS1X_MUX_CTRL1);
#elif defined(CONFIG_LOONGSON1_LS1C)
plat_dat = dev_get_platdata(&pdev->dev);
val &= ~PHY_INTF_SELI;
if (plat_dat->phy_interface == PHY_INTERFACE_MODE_RMII)
val |= 0x4 << PHY_INTF_SELI_SHIFT;
__raw_writel(val, LS1X_MUX_CTRL1);
val = __raw_readl(LS1X_MUX_CTRL0);
__raw_writel(val & (~GMAC_SHUT), LS1X_MUX_CTRL0);
#endif
return 0;
}
static struct plat_stmmacenet_data ls1x_eth0_pdata = {
.bus_id = 0,
.phy_addr = -1,
#if defined(CONFIG_LOONGSON1_LS1B)
.phy_interface = PHY_INTERFACE_MODE_MII,
#elif defined(CONFIG_LOONGSON1_LS1C)
.phy_interface = PHY_INTERFACE_MODE_RMII,
#endif
.mdio_bus_data = &ls1x_mdio_bus_data,
.dma_cfg = &ls1x_eth_dma_cfg,
.has_gmac = 1,
.tx_coe = 1,
.rx_queues_to_use = 1,
.tx_queues_to_use = 1,
.init = ls1x_eth_mux_init,
};
static struct resource ls1x_eth0_resources[] = {
[0] = {
.start = LS1X_GMAC0_BASE,
.end = LS1X_GMAC0_BASE + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.name = "macirq",
.start = LS1X_GMAC0_IRQ,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device ls1x_eth0_pdev = {
.name = "stmmaceth",
.id = 0,
.num_resources = ARRAY_SIZE(ls1x_eth0_resources),
.resource = ls1x_eth0_resources,
.dev = {
.platform_data = &ls1x_eth0_pdata,
},
};
#ifdef CONFIG_LOONGSON1_LS1B
static struct plat_stmmacenet_data ls1x_eth1_pdata = {
.bus_id = 1,
.phy_addr = -1,
.phy_interface = PHY_INTERFACE_MODE_MII,
.mdio_bus_data = &ls1x_mdio_bus_data,
.dma_cfg = &ls1x_eth_dma_cfg,
.has_gmac = 1,
.tx_coe = 1,
.rx_queues_to_use = 1,
.tx_queues_to_use = 1,
.init = ls1x_eth_mux_init,
};
static struct resource ls1x_eth1_resources[] = {
[0] = {
.start = LS1X_GMAC1_BASE,
.end = LS1X_GMAC1_BASE + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.name = "macirq",
.start = LS1X_GMAC1_IRQ,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device ls1x_eth1_pdev = {
.name = "stmmaceth",
.id = 1,
.num_resources = ARRAY_SIZE(ls1x_eth1_resources),
.resource = ls1x_eth1_resources,
.dev = {
.platform_data = &ls1x_eth1_pdata,
},
};
#endif /* CONFIG_LOONGSON1_LS1B */
/* GPIO */
static struct resource ls1x_gpio0_resources[] = {
[0] = {
.start = LS1X_GPIO0_BASE,
.end = LS1X_GPIO0_BASE + SZ_4 - 1,
.flags = IORESOURCE_MEM,
},
};
struct platform_device ls1x_gpio0_pdev = {
.name = "ls1x-gpio",
.id = 0,
.num_resources = ARRAY_SIZE(ls1x_gpio0_resources),
.resource = ls1x_gpio0_resources,
};
static struct resource ls1x_gpio1_resources[] = {
[0] = {
.start = LS1X_GPIO1_BASE,
.end = LS1X_GPIO1_BASE + SZ_4 - 1,
.flags = IORESOURCE_MEM,
},
};
struct platform_device ls1x_gpio1_pdev = {
.name = "ls1x-gpio",
.id = 1,
.num_resources = ARRAY_SIZE(ls1x_gpio1_resources),
.resource = ls1x_gpio1_resources,
};
/* USB EHCI */
static u64 ls1x_ehci_dmamask = DMA_BIT_MASK(32);
static struct resource ls1x_ehci_resources[] = {
[0] = {
.start = LS1X_EHCI_BASE,
.end = LS1X_EHCI_BASE + SZ_32K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = LS1X_EHCI_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct usb_ehci_pdata ls1x_ehci_pdata = {
};
struct platform_device ls1x_ehci_pdev = {
.name = "ehci-platform",
.id = -1,
.num_resources = ARRAY_SIZE(ls1x_ehci_resources),
.resource = ls1x_ehci_resources,
.dev = {
.dma_mask = &ls1x_ehci_dmamask,
.platform_data = &ls1x_ehci_pdata,
},
};
/* Real Time Clock */
struct platform_device ls1x_rtc_pdev = {
.name = "ls1x-rtc",
.id = -1,
};
/* Watchdog */
static struct resource ls1x_wdt_resources[] = {
{
.start = LS1X_WDT_BASE,
.end = LS1X_WDT_BASE + SZ_16 - 1,
.flags = IORESOURCE_MEM,
},
};
struct platform_device ls1x_wdt_pdev = {
.name = "ls1x-wdt",
.id = -1,
.num_resources = ARRAY_SIZE(ls1x_wdt_resources),
.resource = ls1x_wdt_resources,
};

42
arch/mips/loongson32/common/prom.c
View File

@@ -1,42 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
*
* Modified from arch/mips/pnx833x/common/prom.c.
*/
#include <linux/io.h>
#include <linux/init.h>
#include <linux/memblock.h>
#include <linux/serial_reg.h>
#include <asm/fw/fw.h>
#include <loongson1.h>
unsigned long memsize;
void __init prom_init(void)
{
void __iomem *uart_base;
fw_init_cmdline();
memsize = fw_getenvl("memsize");
if(!memsize)
memsize = DEFAULT_MEMSIZE;
if (strstr(arcs_cmdline, "console=ttyS3"))
uart_base = ioremap(LS1X_UART3_BASE, 0x0f);
else if (strstr(arcs_cmdline, "console=ttyS2"))
uart_base = ioremap(LS1X_UART2_BASE, 0x0f);
else if (strstr(arcs_cmdline, "console=ttyS1"))
uart_base = ioremap(LS1X_UART1_BASE, 0x0f);
else
uart_base = ioremap(LS1X_UART0_BASE, 0x0f);
setup_8250_early_printk_port((unsigned long)uart_base, 0, 0);
}
void __init plat_mem_setup(void)
{
memblock_add(0x0, (memsize << 20));
}

26
arch/mips/loongson32/common/setup.c
View File

@@ -1,26 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
*/
#include <linux/io.h>
#include <linux/init.h>
#include <linux/smp.h>
#include <asm/cpu-info.h>
#include <asm/bootinfo.h>
const char *get_system_type(void)
{
unsigned int processor_id = (&current_cpu_data)->processor_id;
switch (processor_id & PRID_REV_MASK) {
case PRID_REV_LOONGSON1B:
#if defined(CONFIG_LOONGSON1_LS1B)
return "LOONGSON LS1B";
#elif defined(CONFIG_LOONGSON1_LS1C)
return "LOONGSON LS1C";
#endif
default:
return "LOONGSON (unknown)";
}
}

23
arch/mips/loongson32/common/time.c
View File

@@ -1,23 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com>
*/
#include <linux/clk.h>
#include <linux/of_clk.h>
#include <asm/time.h>
void __init plat_time_init(void)
{
struct clk *clk = NULL;
/* initialize LS1X clocks */
of_clk_init(NULL);
/* setup mips r4k timer */
clk = clk_get(NULL, "cpu_clk");
if (IS_ERR(clk))
panic("unable to get cpu clock, err=%ld", PTR_ERR(clk));
mips_hpt_frequency = clk_get_rate(clk) / 2;
}

6
arch/mips/loongson32/ls1b/Makefile
View File

@@ -1,6 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# Makefile for loongson1B based machines.
#
obj-y += board.o

55
arch/mips/loongson32/ls1b/board.c
View File

@@ -1,55 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2011-2016 Zhang, Keguang <keguang.zhang@gmail.com>
*/
#include <linux/leds.h>
#include <linux/mtd/partitions.h>
#include <linux/sizes.h>
#include <loongson1.h>
#include <platform.h>
static const struct gpio_led ls1x_gpio_leds[] __initconst = {
{
.name = "LED9",
.default_trigger = "heartbeat",
.gpio = 38,
.active_low = 1,
.default_state = LEDS_GPIO_DEFSTATE_OFF,
}, {
.name = "LED6",
.default_trigger = "nand-disk",
.gpio = 39,
.active_low = 1,
.default_state = LEDS_GPIO_DEFSTATE_OFF,
},
};
static const struct gpio_led_platform_data ls1x_led_pdata __initconst = {
.num_leds = ARRAY_SIZE(ls1x_gpio_leds),
.leds = ls1x_gpio_leds,
};
static struct platform_device *ls1b_platform_devices[] __initdata = {
&ls1x_uart_pdev,
&ls1x_eth0_pdev,
&ls1x_eth1_pdev,
&ls1x_ehci_pdev,
&ls1x_gpio0_pdev,
&ls1x_gpio1_pdev,
&ls1x_rtc_pdev,
&ls1x_wdt_pdev,
};
static int __init ls1b_platform_init(void)
{
ls1x_serial_set_uartclk(&ls1x_uart_pdev);
gpio_led_register_device(-1, &ls1x_led_pdata);
return platform_add_devices(ls1b_platform_devices,
ARRAY_SIZE(ls1b_platform_devices));
}
arch_initcall(ls1b_platform_init);

6
arch/mips/loongson32/ls1c/Makefile
View File

@@ -1,6 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# Makefile for loongson1C based machines.
#
obj-y += board.o

23
arch/mips/loongson32/ls1c/board.c
View File

@@ -1,23 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2016 Yang Ling <gnaygnil@gmail.com>
*/
#include <platform.h>
static struct platform_device *ls1c_platform_devices[] __initdata = {
&ls1x_uart_pdev,
&ls1x_eth0_pdev,
&ls1x_rtc_pdev,
&ls1x_wdt_pdev,
};
static int __init ls1c_platform_init(void)
{
ls1x_serial_set_uartclk(&ls1x_uart_pdev);
return platform_add_devices(ls1c_platform_devices,
ARRAY_SIZE(ls1c_platform_devices));
}
arch_initcall(ls1c_platform_init);

Some files were not shown because too many files have changed in this diff Show More