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drm/tidss: Restructure dispc_vp_prepare() and dispc_vp_enable()

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tidss_crtc.c calls dispc_vp_prepare() and dispc_vp_enable() in that
order, next to each other. dispc_vp_prepare() does preparations for
enabling the crtc, by writing some registers, and dispc_vp_enable() does
more preparations. As the last thing, dispc_vp_enable() enables the CRTC
by writing the enable bit.

There might have been a reason at some point in the history for this
split, but I can't find any point to it. They also do a bit of
overlapping work: both call dispc_vp_find_bus_fmt(). They could as well
be a single function.

But instead of combining them, this patch moves everything from
dispc_vp_enable() to dispc_vp_prepare(), except the actual CRTC enable
bit write. The reason for this is that unlike all the preparatory
register writes, CRTC enable has an immediate effect, starting the
timing generator and the CRTC as a whole. Thus it may be important to
time the enable just right (as we do in the next patch).

No functional changes.

Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Link: https://patch.msgid.link/20250905-tidss-fix-timestamp-v1-1-c2aedf31e2c9@ideasonboard.com
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
This commit is contained in:
Tomi Valkeinen
2025-09-05 16:58:06 +03:00
parent 975ca62a01
commit 6939508c90
3 changed files with 8 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/tidss/tidss_crtc.c
View File

@@ -243,7 +243,7 @@ static void tidss_crtc_atomic_enable(struct drm_crtc *crtc,
dispc_vp_prepare(tidss->dispc, tcrtc->hw_videoport, crtc->state);
dispc_vp_enable(tidss->dispc, tcrtc->hw_videoport, crtc->state);
dispc_vp_enable(tidss->dispc, tcrtc->hw_videoport);
spin_lock_irqsave(&ddev->event_lock, flags);

22
drivers/gpu/drm/tidss/tidss_dispc.c
View File

@@ -1164,6 +1164,9 @@ void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport,
{
const struct tidss_crtc_state *tstate = to_tidss_crtc_state(state);
const struct dispc_bus_format *fmt;
const struct drm_display_mode *mode = &state->adjusted_mode;
bool align, onoff, rf, ieo, ipc, ihs, ivs;
u32 hsw, hfp, hbp, vsw, vfp, vbp;
fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format,
tstate->bus_flags);
@@ -1176,22 +1179,6 @@ void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport,
dispc_enable_am65x_oldi(dispc, hw_videoport, fmt);
}
}
void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport,
const struct drm_crtc_state *state)
{
const struct drm_display_mode *mode = &state->adjusted_mode;
const struct tidss_crtc_state *tstate = to_tidss_crtc_state(state);
bool align, onoff, rf, ieo, ipc, ihs, ivs;
const struct dispc_bus_format *fmt;
u32 hsw, hfp, hbp, vsw, vfp, vbp;
fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format,
tstate->bus_flags);
if (WARN_ON(!fmt))
return;
dispc_set_num_datalines(dispc, hw_videoport, fmt->data_width);
@@ -1247,7 +1234,10 @@ void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport,
mode->crtc_hdisplay - 1) |
FIELD_PREP(DISPC_VP_SIZE_SCREEN_VDISPLAY_MASK,
mode->crtc_vdisplay - 1));
}
void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport)
{
VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1,
DISPC_VP_CONTROL_ENABLE_MASK);
}

3
drivers/gpu/drm/tidss/tidss_dispc.h
View File

@@ -119,8 +119,7 @@ void dispc_ovr_enable_layer(struct dispc_device *dispc,
void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport,
const struct drm_crtc_state *state);
void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport,
const struct drm_crtc_state *state);
void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport);
void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport);
void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport);
bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport);