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tools/power turbostat: Enhance perf probe
check_perf_access() will now check both IPC and LLC perf counters if they are enabled. If any fail, it now disables perf and all perf counters. Signed-off-by: Len Brown <len.brown@intel.com>
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@@ -2438,6 +2438,13 @@ static void bic_disable_msr_access(void)
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free_sys_msr_counters();
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}
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static void bic_disable_perf_access(void)
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{
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CLR_BIC(BIC_IPC, &bic_enabled);
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CLR_BIC(BIC_LLC_RPS, &bic_enabled);
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CLR_BIC(BIC_LLC_HIT, &bic_enabled);
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}
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static long perf_event_open(struct perf_event_attr *hw_event, pid_t pid, int cpu, int group_fd, unsigned long flags)
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{
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assert(!no_perf);
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@@ -8327,26 +8334,23 @@ void print_dev_latency(void)
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close(fd);
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}
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static int has_instr_count_access(void)
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static int has_perf_instr_count_access(void)
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{
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int fd;
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int has_access;
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if (no_perf)
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return 0;
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fd = open_perf_counter(base_cpu, PERF_TYPE_HARDWARE, PERF_COUNT_HW_INSTRUCTIONS, -1, 0);
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has_access = fd != -1;
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if (fd != -1)
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close(fd);
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if (!has_access)
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if (fd == -1)
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warnx("Failed to access %s. Some of the counters may not be available\n"
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"\tRun as root to enable them or use %s to disable the access explicitly",
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"instructions retired perf counter", "--no-perf");
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"\tRun as root to enable them or use %s to disable the access explicitly", "perf instructions retired counter",
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"'--hide IPC' or '--no-perf'");
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return has_access;
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return (fd != -1);
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}
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int add_rapl_perf_counter(int cpu, struct rapl_counter_info_t *rci, const struct rapl_counter_arch_info *cai,
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@@ -9080,6 +9084,28 @@ void probe_pm_features(void)
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decode_misc_feature_control();
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}
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/* perf_llc_probe
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*
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* return 1 on success, else 0
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*/
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int has_perf_llc_access(void)
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{
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int fd;
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if (no_perf)
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return 0;
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fd = open_perf_counter(base_cpu, PERF_TYPE_HARDWARE, PERF_COUNT_HW_CACHE_REFERENCES, -1, PERF_FORMAT_GROUP);
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if (fd != -1)
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close(fd);
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if (fd == -1)
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warnx("Failed to access %s. Some of the counters may not be available\n"
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"\tRun as root to enable them or use %s to disable the access explicitly", "perf LLC counters", "'--hide LLC' or '--no-perf'");
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return (fd != -1);
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}
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void perf_llc_init(void)
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{
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int cpu;
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@@ -9535,8 +9561,16 @@ void check_msr_access(void)
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void check_perf_access(void)
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{
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if (no_perf || !BIC_IS_ENABLED(BIC_IPC) || !has_instr_count_access())
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CLR_BIC(BIC_IPC, &bic_enabled);
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if (BIC_IS_ENABLED(BIC_IPC))
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if (!has_perf_instr_count_access())
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no_perf = 1;
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if (BIC_IS_ENABLED(BIC_LLC_RPS) || BIC_IS_ENABLED(BIC_LLC_HIT))
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if (!has_perf_llc_access())
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no_perf = 1;
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if (no_perf)
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bic_disable_perf_access();
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}
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bool perf_has_hybrid_devices(void)
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