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arm64: dts: renesas: Add R8A78000 SoC support
Add initial support for the Renesas R-Car X5H (R8A78000) SoC. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Vinh Nguyen <vinh.nguyen.xz@renesas.com> Signed-off-by: Minh Le <minh.le.aj@renesas.com> Signed-off-by: Huy Bui <huy.bui.wm@renesas.com> Signed-off-by: Khanh Le <khanh.le.xr@renesas.com> Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com> [Kuninori: tidyup for upstreaming] Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/87frcca3fn.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Hai Pham
committed by
Geert Uytterhoeven
Geert Uytterhoeven
parent
8895b0e600
commit
63500d12cf
787
arch/arm64/boot/dts/renesas/r8a78000.dtsi
Normal file
787
arch/arm64/boot/dts/renesas/r8a78000.dtsi
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@@ -0,0 +1,787 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the R-Car X5H (R8A78000) SoC
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*
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* Copyright (C) 2025 Renesas Electronics Corp.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "renesas,r8a78000";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&a720_0>;
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};
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core1 {
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cpu = <&a720_1>;
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};
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core2 {
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cpu = <&a720_2>;
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};
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core3 {
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cpu = <&a720_3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&a720_4>;
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};
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core1 {
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cpu = <&a720_5>;
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};
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core2 {
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cpu = <&a720_6>;
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};
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core3 {
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cpu = <&a720_7>;
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};
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};
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cluster2 {
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core0 {
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cpu = <&a720_8>;
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};
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core1 {
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cpu = <&a720_9>;
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};
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core2 {
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cpu = <&a720_10>;
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};
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core3 {
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cpu = <&a720_11>;
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};
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};
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cluster3 {
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core0 {
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cpu = <&a720_12>;
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};
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core1 {
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cpu = <&a720_13>;
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};
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core2 {
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cpu = <&a720_14>;
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};
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core3 {
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cpu = <&a720_15>;
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};
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};
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cluster4 {
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core0 {
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cpu = <&a720_16>;
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};
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core1 {
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cpu = <&a720_17>;
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};
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core2 {
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cpu = <&a720_18>;
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};
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core3 {
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cpu = <&a720_19>;
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};
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};
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cluster5 {
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core0 {
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cpu = <&a720_20>;
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};
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core1 {
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cpu = <&a720_21>;
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};
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core2 {
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cpu = <&a720_22>;
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};
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core3 {
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cpu = <&a720_23>;
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};
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};
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cluster6 {
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core0 {
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cpu = <&a720_24>;
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};
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core1 {
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cpu = <&a720_25>;
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};
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core2 {
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cpu = <&a720_26>;
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};
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core3 {
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cpu = <&a720_27>;
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};
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};
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cluster7 {
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core0 {
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cpu = <&a720_28>;
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};
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core1 {
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cpu = <&a720_29>;
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};
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core2 {
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cpu = <&a720_30>;
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};
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core3 {
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cpu = <&a720_31>;
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};
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};
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};
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a720_0: cpu@0 {
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compatible = "arm,cortex-a720ae";
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reg = <0x0 0x0>;
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device_type = "cpu";
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next-level-cache = <&L2_CA720_0>;
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};
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a720_1: cpu@100 {
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compatible = "arm,cortex-a720ae";
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reg = <0x0 0x100>;
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device_type = "cpu";
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next-level-cache = <&L2_CA720_1>;
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};
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a720_2: cpu@200 {
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compatible = "arm,cortex-a720ae";
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reg = <0x0 0x200>;
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device_type = "cpu";
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next-level-cache = <&L2_CA720_2>;
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};
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a720_3: cpu@300 {
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compatible = "arm,cortex-a720ae";
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reg = <0x0 0x300>;
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device_type = "cpu";
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next-level-cache = <&L2_CA720_3>;
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};
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a720_4: cpu@10000 {
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compatible = "arm,cortex-a720ae";
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reg = <0x0 0x10000>;
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device_type = "cpu";
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next-level-cache = <&L2_CA720_4>;
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};
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a720_5: cpu@10100 {
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compatible = "arm,cortex-a720ae";
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reg = <0x0 0x10100>;
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device_type = "cpu";
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next-level-cache = <&L2_CA720_5>;
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};
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a720_6: cpu@10200 {
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compatible = "arm,cortex-a720ae";
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reg = <0x0 0x10200>;
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device_type = "cpu";
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next-level-cache = <&L2_CA720_6>;
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};
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a720_7: cpu@10300 {
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compatible = "arm,cortex-a720ae";
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reg = <0x0 0x10300>;
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device_type = "cpu";
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next-level-cache = <&L2_CA720_7>;
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};
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a720_8: cpu@20000 {
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compatible = "arm,cortex-a720ae";
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reg = <0x0 0x20000>;
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device_type = "cpu";
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next-level-cache = <&L2_CA720_8>;
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};
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a720_9: cpu@20100 {
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compatible = "arm,cortex-a720ae";
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reg = <0x0 0x20100>;
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device_type = "cpu";
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next-level-cache = <&L2_CA720_9>;
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};
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a720_10: cpu@20200 {
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compatible = "arm,cortex-a720ae";
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reg = <0x0 0x20200>;
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device_type = "cpu";
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next-level-cache = <&L2_CA720_10>;
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};
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a720_11: cpu@20300 {
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compatible = "arm,cortex-a720ae";
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reg = <0x0 0x20300>;
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device_type = "cpu";
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next-level-cache = <&L2_CA720_11>;
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};
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a720_12: cpu@30000 {
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compatible = "arm,cortex-a720ae";
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reg = <0x0 0x30000>;
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device_type = "cpu";
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next-level-cache = <&L2_CA720_12>;
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};
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a720_13: cpu@30100 {
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compatible = "arm,cortex-a720ae";
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reg = <0x0 0x30100>;
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device_type = "cpu";
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next-level-cache = <&L2_CA720_13>;
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};
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a720_14: cpu@30200 {
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compatible = "arm,cortex-a720ae";
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reg = <0x0 0x30200>;
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device_type = "cpu";
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next-level-cache = <&L2_CA720_14>;
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};
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a720_15: cpu@30300 {
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compatible = "arm,cortex-a720ae";
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reg = <0x0 0x30300>;
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device_type = "cpu";
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next-level-cache = <&L2_CA720_15>;
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};
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a720_16: cpu@40000 {
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compatible = "arm,cortex-a720ae";
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reg = <0x0 0x40000>;
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device_type = "cpu";
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next-level-cache = <&L2_CA720_16>;
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};
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a720_17: cpu@40100 {
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compatible = "arm,cortex-a720ae";
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reg = <0x0 0x40100>;
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device_type = "cpu";
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next-level-cache = <&L2_CA720_17>;
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};
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a720_18: cpu@40200 {
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compatible = "arm,cortex-a720ae";
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reg = <0x0 0x40200>;
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device_type = "cpu";
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next-level-cache = <&L2_CA720_18>;
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};
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a720_19: cpu@40300 {
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compatible = "arm,cortex-a720ae";
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reg = <0x0 0x40300>;
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device_type = "cpu";
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next-level-cache = <&L2_CA720_19>;
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};
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a720_20: cpu@50000 {
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compatible = "arm,cortex-a720ae";
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reg = <0x0 0x50000>;
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device_type = "cpu";
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next-level-cache = <&L2_CA720_20>;
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};
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a720_21: cpu@50100 {
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compatible = "arm,cortex-a720ae";
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reg = <0x0 0x50100>;
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device_type = "cpu";
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next-level-cache = <&L2_CA720_21>;
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};
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a720_22: cpu@50200 {
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compatible = "arm,cortex-a720ae";
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reg = <0x0 0x50200>;
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device_type = "cpu";
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next-level-cache = <&L2_CA720_22>;
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};
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a720_23: cpu@50300 {
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compatible = "arm,cortex-a720ae";
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reg = <0x0 0x50300>;
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device_type = "cpu";
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next-level-cache = <&L2_CA720_23>;
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};
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a720_24: cpu@60000 {
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compatible = "arm,cortex-a720ae";
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reg = <0x0 0x60000>;
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device_type = "cpu";
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next-level-cache = <&L2_CA720_24>;
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};
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a720_25: cpu@60100 {
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compatible = "arm,cortex-a720ae";
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reg = <0x0 0x60100>;
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device_type = "cpu";
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next-level-cache = <&L2_CA720_25>;
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};
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a720_26: cpu@60200 {
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compatible = "arm,cortex-a720ae";
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reg = <0x0 0x60200>;
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device_type = "cpu";
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next-level-cache = <&L2_CA720_26>;
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};
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a720_27: cpu@60300 {
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compatible = "arm,cortex-a720ae";
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reg = <0x0 0x60300>;
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device_type = "cpu";
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next-level-cache = <&L2_CA720_27>;
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};
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a720_28: cpu@70000 {
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compatible = "arm,cortex-a720ae";
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reg = <0x0 0x70000>;
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device_type = "cpu";
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next-level-cache = <&L2_CA720_28>;
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};
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a720_29: cpu@70100 {
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compatible = "arm,cortex-a720ae";
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reg = <0x0 0x70100>;
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device_type = "cpu";
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next-level-cache = <&L2_CA720_29>;
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};
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a720_30: cpu@70200 {
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compatible = "arm,cortex-a720ae";
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reg = <0x0 0x70200>;
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device_type = "cpu";
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next-level-cache = <&L2_CA720_30>;
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};
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a720_31: cpu@70300 {
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compatible = "arm,cortex-a720ae";
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reg = <0x0 0x70300>;
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device_type = "cpu";
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next-level-cache = <&L2_CA720_31>;
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};
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L2_CA720_0: cache-controller-200 {
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compatible = "cache";
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cache-unified;
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cache-level = <2>;
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next-level-cache = <&L3_CA720_0>;
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};
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L2_CA720_1: cache-controller-201 {
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compatible = "cache";
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cache-unified;
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cache-level = <2>;
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next-level-cache = <&L3_CA720_0>;
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};
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L2_CA720_2: cache-controller-202 {
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compatible = "cache";
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cache-unified;
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cache-level = <2>;
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next-level-cache = <&L3_CA720_0>;
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};
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L2_CA720_3: cache-controller-203 {
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compatible = "cache";
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cache-unified;
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cache-level = <2>;
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next-level-cache = <&L3_CA720_0>;
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};
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L2_CA720_4: cache-controller-204 {
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compatible = "cache";
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cache-unified;
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cache-level = <2>;
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next-level-cache = <&L3_CA720_1>;
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};
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L2_CA720_5: cache-controller-205 {
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compatible = "cache";
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cache-unified;
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cache-level = <2>;
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next-level-cache = <&L3_CA720_1>;
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};
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L2_CA720_6: cache-controller-206 {
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compatible = "cache";
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cache-unified;
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cache-level = <2>;
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next-level-cache = <&L3_CA720_1>;
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};
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L2_CA720_7: cache-controller-207 {
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compatible = "cache";
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cache-unified;
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cache-level = <2>;
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next-level-cache = <&L3_CA720_1>;
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};
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L2_CA720_8: cache-controller-208 {
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compatible = "cache";
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cache-unified;
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cache-level = <2>;
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next-level-cache = <&L3_CA720_2>;
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};
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L2_CA720_9: cache-controller-209 {
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compatible = "cache";
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cache-unified;
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cache-level = <2>;
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next-level-cache = <&L3_CA720_2>;
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};
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L2_CA720_10: cache-controller-210 {
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compatible = "cache";
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cache-unified;
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cache-level = <2>;
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next-level-cache = <&L3_CA720_2>;
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};
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L2_CA720_11: cache-controller-211 {
|
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compatible = "cache";
|
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cache-unified;
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cache-level = <2>;
|
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next-level-cache = <&L3_CA720_2>;
|
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};
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L2_CA720_12: cache-controller-212 {
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compatible = "cache";
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cache-unified;
|
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cache-level = <2>;
|
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next-level-cache = <&L3_CA720_3>;
|
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};
|
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|
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L2_CA720_13: cache-controller-213 {
|
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compatible = "cache";
|
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cache-unified;
|
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cache-level = <2>;
|
||||
next-level-cache = <&L3_CA720_3>;
|
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};
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L2_CA720_14: cache-controller-214 {
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compatible = "cache";
|
||||
cache-unified;
|
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cache-level = <2>;
|
||||
next-level-cache = <&L3_CA720_3>;
|
||||
};
|
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|
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L2_CA720_15: cache-controller-215 {
|
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compatible = "cache";
|
||||
cache-unified;
|
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cache-level = <2>;
|
||||
next-level-cache = <&L3_CA720_3>;
|
||||
};
|
||||
|
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L2_CA720_16: cache-controller-216 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_CA720_4>;
|
||||
};
|
||||
|
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L2_CA720_17: cache-controller-217 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_CA720_4>;
|
||||
};
|
||||
|
||||
L2_CA720_18: cache-controller-218 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_CA720_4>;
|
||||
};
|
||||
|
||||
L2_CA720_19: cache-controller-219 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_CA720_4>;
|
||||
};
|
||||
|
||||
L2_CA720_20: cache-controller-220 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_CA720_5>;
|
||||
};
|
||||
|
||||
L2_CA720_21: cache-controller-221 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_CA720_5>;
|
||||
};
|
||||
|
||||
L2_CA720_22: cache-controller-222 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_CA720_5>;
|
||||
};
|
||||
|
||||
L2_CA720_23: cache-controller-223 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_CA720_5>;
|
||||
};
|
||||
|
||||
L2_CA720_24: cache-controller-224 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_CA720_6>;
|
||||
};
|
||||
|
||||
L2_CA720_25: cache-controller-225 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_CA720_6>;
|
||||
};
|
||||
|
||||
L2_CA720_26: cache-controller-226 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_CA720_6>;
|
||||
};
|
||||
|
||||
L2_CA720_27: cache-controller-227 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_CA720_6>;
|
||||
};
|
||||
|
||||
L2_CA720_28: cache-controller-228 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_CA720_7>;
|
||||
};
|
||||
|
||||
L2_CA720_29: cache-controller-229 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_CA720_7>;
|
||||
};
|
||||
|
||||
L2_CA720_30: cache-controller-230 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_CA720_7>;
|
||||
};
|
||||
|
||||
L2_CA720_31: cache-controller-231 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_CA720_7>;
|
||||
};
|
||||
|
||||
L3_CA720_0: cache-controller-30 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <3>;
|
||||
};
|
||||
|
||||
L3_CA720_1: cache-controller-31 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <3>;
|
||||
};
|
||||
|
||||
L3_CA720_2: cache-controller-32 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <3>;
|
||||
};
|
||||
|
||||
L3_CA720_3: cache-controller-33 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <3>;
|
||||
};
|
||||
|
||||
L3_CA720_4: cache-controller-34 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <3>;
|
||||
};
|
||||
|
||||
L3_CA720_5: cache-controller-35 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <3>;
|
||||
};
|
||||
|
||||
L3_CA720_6: cache-controller-36 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <3>;
|
||||
};
|
||||
|
||||
L3_CA720_7: cache-controller-37 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-level = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* In the early phase, there is no clock control support,
|
||||
* so assume that the clocks are enabled by default.
|
||||
* Therefore, dummy clocks are used.
|
||||
*/
|
||||
dummy_clk_sgasyncd16: dummy-clk-sgasyncd16 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <66666000>;
|
||||
};
|
||||
|
||||
dummy_clk_sgasyncd4: dummy-clk-sgasyncd4 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <266660000>;
|
||||
};
|
||||
|
||||
extal_clk: extal-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* clock-frequency must be set on board */
|
||||
};
|
||||
|
||||
extalr_clk: extalr-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* clock-frequency must be set on board */
|
||||
};
|
||||
|
||||
/* External SCIF clock - to be overridden by boards that provide it */
|
||||
scif_clk: scif-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>; /* optional */
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
prr: chipid@189e0044 {
|
||||
compatible = "renesas,prr";
|
||||
reg = <0 0x189e0044 0 4>;
|
||||
};
|
||||
|
||||
/* Application Processors manage View-1 of a GIC-720AE */
|
||||
gic: interrupt-controller@39000000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0 0x39000000 0 0x10000>,
|
||||
<0 0x39080000 0 0x800000>;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
scif0: serial@c0700000 {
|
||||
compatible = "renesas,scif-r8a78000",
|
||||
"renesas,rcar-gen5-scif", "renesas,scif";
|
||||
reg = <0 0xc0700000 0 0x40>;
|
||||
interrupts = <GIC_SPI 4074 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scif1: serial@c0704000 {
|
||||
compatible = "renesas,scif-r8a78000",
|
||||
"renesas,rcar-gen5-scif", "renesas,scif";
|
||||
reg = <0 0xc0704000 0 0x40>;
|
||||
interrupts = <GIC_SPI 4075 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scif3: serial@c0708000 {
|
||||
compatible = "renesas,scif-r8a78000",
|
||||
"renesas,rcar-gen5-scif", "renesas,scif";
|
||||
reg = <0 0xc0708000 0 0x40>;
|
||||
interrupts = <GIC_SPI 4076 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scif4: serial@c070c000 {
|
||||
compatible = "renesas,scif-r8a78000",
|
||||
"renesas,rcar-gen5-scif", "renesas,scif";
|
||||
reg = <0 0xc070c000 0 0x40>;
|
||||
interrupts = <GIC_SPI 4077 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hscif0: serial@c0710000 {
|
||||
compatible = "renesas,hscif-r8a78000",
|
||||
"renesas,rcar-gen5-hscif", "renesas,hscif";
|
||||
reg = <0 0xc0710000 0 0x60>;
|
||||
interrupts = <GIC_SPI 4078 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hscif1: serial@c0714000 {
|
||||
compatible = "renesas,hscif-r8a78000",
|
||||
"renesas,rcar-gen5-hscif", "renesas,hscif";
|
||||
reg = <0 0xc0714000 0 0x60>;
|
||||
interrupts = <GIC_SPI 4079 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hscif2: serial@c0718000 {
|
||||
compatible = "renesas,hscif-r8a78000",
|
||||
"renesas,rcar-gen5-hscif", "renesas,hscif";
|
||||
reg = <0 0xc0718000 0 0x60>;
|
||||
interrupts = <GIC_SPI 4080 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hscif3: serial@c071c000 {
|
||||
compatible = "renesas,hscif-r8a78000",
|
||||
"renesas,rcar-gen5-hscif", "renesas,hscif";
|
||||
reg = <0 0xc071c000 0 0x60>;
|
||||
interrupts = <GIC_SPI 4081 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
|
||||
};
|
||||
};
|
||||
Reference in New Issue
Block a user